forked from M-Labs/artiq-zynq
121 lines
3.5 KiB
Python
121 lines
3.5 KiB
Python
from migen import *
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from misoc.interconnect.csr import *
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from misoc.interconnect import stream
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from sim_pipeline import CXPCRC32
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from src.gateware.cxp_pipeline import *
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class CXPCRC32Inserter(Module):
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def __init__(self):
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self.sink = stream.Endpoint(word_layout)
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self.source = stream.Endpoint(word_layout)
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# # #
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self.submodules.crc = crc = CXPCRC32(word_dw)
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act(
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"IDLE",
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crc.reset.eq(1),
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self.sink.ack.eq(1),
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If(
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self.sink.stb,
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self.sink.ack.eq(0),
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NextState("COPY"),
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),
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)
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fsm.act(
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"COPY",
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crc.ce.eq(self.sink.stb & self.source.ack),
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crc.data.eq(self.sink.data),
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self.sink.connect(self.source),
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self.source.eop.eq(0),
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If(
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self.sink.stb & self.sink.eop & self.source.ack,
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NextState("INSERT"),
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),
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)
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fsm.act(
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"INSERT",
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self.source.stb.eq(1),
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self.source.eop.eq(1),
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self.source.data.eq(crc.value),
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If(self.source.ack, NextState("IDLE")),
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)
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class StreamPacket_Wrapper(Module):
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def __init__(self):
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self.sink = stream.Endpoint(word_layout)
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self.source = stream.Endpoint(word_layout)
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# # #
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act(
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"IDLE",
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self.sink.ack.eq(1),
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If(
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self.sink.stb,
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self.sink.ack.eq(0),
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NextState("INSERT_HEADER_0"),
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),
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)
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fsm.act(
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"INSERT_HEADER_0",
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self.sink.ack.eq(0),
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self.source.stb.eq(1),
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self.source.data.eq(Replicate(KCode["pak_start"], 4)),
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self.source.k.eq(Replicate(1, 4)),
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If(self.source.ack, NextState("INSERT_HEADER_1")),
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)
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fsm.act(
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"INSERT_HEADER_1",
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self.sink.ack.eq(0),
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self.source.stb.eq(1),
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self.source.data.eq(Replicate(C(0x01, char_width), 4)),
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self.source.k.eq(Replicate(0, 4)),
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If(self.source.ack, NextState("COPY")),
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)
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fsm.act(
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"COPY",
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self.sink.connect(self.source),
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self.source.eop.eq(0),
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If(
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self.sink.stb & self.sink.eop & self.source.ack,
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NextState("INSERT_FOOTER"),
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),
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)
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fsm.act(
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"INSERT_FOOTER",
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self.sink.ack.eq(0),
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self.source.stb.eq(1),
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self.source.data.eq(Replicate(KCode["pak_end"], 4)),
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self.source.k.eq(Replicate(1, 4)),
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# Simulate RX don't have eop tagged
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# self.source.eop.eq(1),
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If(self.source.ack, NextState("IDLE")),
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)
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# With KCode & 0x01*4
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class StreamData_Generator(Module):
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def __init__(self):
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# should be big enough for all test
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self.submodules.buffer = buffer = stream.SyncFIFO(word_layout, 32)
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self.submodules.crc_inserter = crc_inserter = CXPCRC32Inserter()
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self.submodules.wrapper = wrapper = StreamPacket_Wrapper()
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# # #
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pipeline = [buffer, crc_inserter, wrapper]
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for s, d in zip(pipeline, pipeline[1:]):
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self.comb += s.source.connect(d.sink)
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self.sink = pipeline[0].sink
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self.source = pipeline[-1].source
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