forked from M-Labs/artiq-zynq
93 lines
2.7 KiB
Python
93 lines
2.7 KiB
Python
from migen import *
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from migen.genlib.cdc import PulseSynchronizer, MultiReg
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from misoc.interconnect.csr import *
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class DDMTDSampler(Module):
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def __init__(self, cd_ref, main_clk_se):
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self.ref_beating = Signal()
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self.main_beating = Signal()
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# # #
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ref_clk = Signal()
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self.specials +=[
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# ISERDESE2 can only be driven from fabric via IDELAYE2 (see UG471)
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Instance("IDELAYE2",
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p_DELAY_SRC="DATAIN",
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p_HIGH_PERFORMANCE_MODE="TRUE",
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p_REFCLK_FREQUENCY=208.3, # REFCLK frequency from IDELAYCTRL
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p_IDELAY_VALUE=0,
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i_DATAIN=cd_ref.clk,
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o_DATAOUT=ref_clk
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),
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Instance("ISERDESE2",
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p_IOBDELAY="IFD", # use DDLY as input
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p_DATA_RATE="SDR",
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p_DATA_WIDTH=2, # min is 2
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p_NUM_CE=1,
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i_DDLY=ref_clk,
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i_CE1=1,
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i_CLK=ClockSignal("helper"),
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i_CLKDIV=ClockSignal("helper"),
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o_Q1=self.ref_beating
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),
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Instance("ISERDESE2",
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p_DATA_RATE="SDR",
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p_DATA_WIDTH=2, # min is 2
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p_NUM_CE=1,
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i_D=main_clk_se,
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i_CE1=1,
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i_CLK=ClockSignal("helper"),
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i_CLKDIV=ClockSignal("helper"),
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o_Q1=self.main_beating,
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),
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]
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class DDMTDDeglitcherFirstEdge(Module):
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def __init__(self, input_signal, blind_period=400):
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self.detect = Signal()
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rising = Signal()
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input_signal_r = Signal()
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# # #
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self.sync.helper += [
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input_signal_r.eq(input_signal),
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rising.eq(input_signal & ~input_signal_r)
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]
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blind_counter = Signal(max=blind_period)
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self.sync.helper += [
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If(blind_counter != 0, blind_counter.eq(blind_counter - 1)),
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If(input_signal_r, blind_counter.eq(blind_period - 1)),
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self.detect.eq(rising & (blind_counter == 0))
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]
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class DDMTD(Module):
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def __init__(self, counter, input_signal):
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# in helper clock domain
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self.h_tag = Signal(len(counter))
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self.h_tag_update = Signal()
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# # #
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deglitcher = DDMTDDeglitcherFirstEdge(input_signal)
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self.submodules += deglitcher
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self.sync.helper += [
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self.h_tag_update.eq(0),
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If(deglitcher.detect,
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self.h_tag_update.eq(1),
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self.h_tag.eq(counter)
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)
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] |