from migen import *
from misoc.interconnect import stream

from sim_pipeline import *
from sim_generator import StreamData_Generator

from src.gateware.cxp_pipeline import *

class CXP_Links(Module):
    def __init__(self):
        # TODO: select the correct buffer to read from
        # NOTE: although there are double buffer in each connect, the reading must be faster than writing to avoid data loss

        self.downconn_sources = []
        self.stream_sinks = []
        for i in range(2):
            downconn = Pipeline()
            setattr(self.submodules, "cxp_conn"+str(i), downconn)
            self.downconn_sources.append(downconn)

            stream_pipeline = Stream_Pipeline()
            setattr(self.submodules, "stream_pipeline"+str(i), stream_pipeline)
            self.stream_sinks.append(stream_pipeline)

        self.submodules.crossbar = Streams_Crossbar(self.downconn_sources, self.stream_sinks)
        
class Pipeline(Module):
    def __init__(self):
        self.submodules.generator = generator = StreamData_Generator()
        self.submodules.dchar_decoder = dchar_decoder = Duplicated_Char_Decoder()
        self.submodules.data_decoder = data_decoder = RX_Bootstrap()
        self.submodules.eop_marker = eop_marker = EOP_Marker()

        # # #

        pipeline = [generator, dchar_decoder, data_decoder, eop_marker]
        for s, d in zip(pipeline, pipeline[1:]):
            self.comb += s.source.connect(d.sink)
        self.sink = pipeline[0].sink
        self.source = pipeline[-1].source

        # self.comb += self.source.ack.eq(1)


dut = CXP_Links()

def check_case(packet=[]):
    print("=================TEST========================")

    downconns = dut.downconn_sources
    stream_buffers = dut.stream_sinks
    ch = 0
    
    for i, p in enumerate(packet):
        for x in range(len(downconns)):
            if x == ch:
                yield downconns[x].sink.data.eq(p["data"])
                yield downconns[x].sink.k.eq(p["k"])
                yield downconns[x].sink.stb.eq(1)
            else:
                yield downconns[x].sink.data.eq(0)
                yield downconns[x].sink.k.eq(0)
                yield downconns[x].sink.stb.eq(0)
                yield downconns[x].sink.eop.eq(0)
        if "eop" in p:
            yield downconns[ch].sink.eop.eq(1)
            # compensate for delay
            # yield
            # yield downconns[ch].sink.data.eq(0)
            # yield downconns[ch].sink.k.eq(0)
            # yield downconns[ch].sink.stb.eq(0)
            # yield downconns[ch].sink.eop.eq(0)
            # yield
            # yield
            # yield
            ch = (ch + 1) % len(downconns)
        else:
            yield downconns[ch].sink.eop.eq(0)

        # check cycle result
        yield
        # source = dut.stream_pipeline_sinks[0].source
        source = dut.stream_sinks[0].double_buffer.source
        print(
            f"\nCYCLE#{i} : source char = {yield source.data:#X} k = {yield source.k:#X} stb = {yield source.stb} ack = {yield source.ack} eop = {yield source.eop}"
            # f" source dchar = {yield source.dchar:#X} dchar_k = {yield source.dchar_k:#X}"
            f"\nCYCLE#{i} : read mask = {yield dut.crossbar.mux.sel}"
            # f"\nCYCLE#{i} : stream id = {yield decoder.stream_id:#X} pak_tag = {yield decoder.pak_tag:#X}"
            # f" stream_pak_size = {yield decoder.stream_pak_size:#X}"
        )
        # crc = downconns[1].generator.crc_inserter.crc
        # crc = dut.double_buffer.crc
        # print(
        #     f"CYCLE#{i} : crc error = {yield crc.error:#X} crc value = {yield crc.value:#X}"
        #     f" crc data = {yield crc.data:#X} engine next = {yield crc.engine.next:#X} ce = {yield crc.ce}"
        # )

            
    # extra clk cycles
    cyc = i + 1
    for i in range(cyc, cyc + 30):
        for x in range(len(downconns)):
            # yield won't reset every cycle
            yield downconns[x].sink.data.eq(0)
            yield downconns[x].sink.k.eq(0)
            yield downconns[x].sink.stb.eq(0)
            yield downconns[x].sink.eop.eq(0)
        yield
        print(
            f"\nCYCLE#{i} : source char = {yield source.data:#X} k = {yield source.k:#X} stb = {yield source.stb} ack = {yield source.ack} eop = {yield source.eop}"
            # f" source dchar = {yield source.dchar:#X} dchar_k = {yield source.dchar_k:#X}"
            f"\nCYCLE#{i} : read mask = {yield dut.crossbar .mux.sel}"
            # f"\nCYCLE#{i} : stream id = {yield decoder.stream_id:#X} pak_tag = {yield decoder.pak_tag:#X}"
            # f" stream_pak_size = {yield decoder.stream_pak_size:#X}"
        )
    assert True


def testbench():
    # stream_id = 0x01
    streams = [
        [
            {"data": 0x11111111, "k": Replicate(0, 4)},
            {"data": 0xB105F00D, "k": Replicate(0, 4)},
        ],
        [
            {"data": 0x22222222, "k": Replicate(0, 4)},
            {"data": 0xC001BEA0, "k": Replicate(0, 4)},
        ],
        [
            {"data": 0x33333333, "k": Replicate(0, 4)},
            {"data": 0xC0A79AE5, "k": Replicate(0, 4)},
        ],
    ]

    packet = []
    for i, s in enumerate(streams):
        s[-1]["eop"] = 0
        packet += [
            {"data": Replicate(C(i % 2, char_width), 4), "k": Replicate(0, 4)},
            {"data": Replicate(C(i, char_width), 4), "k": Replicate(0, 4)},
            {
                "data": Replicate(C(len(s) >> 8 & 0xFF, char_width), 4),
                "k": Replicate(0, 4),
            },
            {"data": Replicate(C(len(s) & 0xFF, char_width), 4), "k": Replicate(0, 4)},
            *s,
        ]


    yield from check_case(packet)


run_simulation(dut, testbench(), vcd_name="sim-cxp.vcd")