from migen import *
from misoc.interconnect import stream

class Frame(Module):
    def __init__(self):
        self.a = Signal()
        self.b = Signal()
        self.comb += [
            self.a.eq(self.b),
            # self.b.eq(self.a),
        ]

dut = Frame()

def check_case():
    yield dut.a.eq(1)
    yield 
    yield dut.a.eq(0)
    yield 
    for i in range(10):
        yield


def testbench():
    yield from check_case()


run_simulation(dut, testbench(), vcd_name="sim-cxp.vcd")