cxp comms: Control packet handler

ctrl: add buildin delay_ms
ctrl: add proper RX Downconn packet handling
ctrl: add send, receive & receive with timeout
ctrl: add write/read u32
ctrl: add cxp error enum

cxp_kernel.py

@@ -0,0 +1,58 @@
+"""
+Non-realtime drivers for CXP.
+"""
+
+# TODO: add api calls for CTRL packet similar i2c
+# TODO: add timing critical trigger ack
+
+
+from artiq.language.core import syscall, kernel
+from artiq.language.types import TBool, TInt32, TNone
+from artiq.coredevice.rtio import rtio_output
+from artiq.experiment import *
+
+
+class CoaXPress:
+    def __init__(self, channel, core_device="core"):
+        # __device_mgr is private 
+        # self.core = dmgr.get(core_device)
+
+        # you can get the channel via `print(len(rtio_channels))` before calling
+        # `rtio_channels.append(rtio.Channel.from_phy(cxp_interface))`
+        self.channel = channel
+        # the first 8 bits is reserved for the rtlink.OInterface.addr not for channel no.
+        self.target_o = channel << 8
+
+    @staticmethod
+    def get_rtio_channels(channel, **kwargs):
+        return [(channel, None)]
+
+    @kernel
+    def trigger(self, linktrig, trigdelay):
+        rtio_output(self.target_o, linktrig | trigdelay << 1)
+
+
+@syscall(flags={"nounwind", "nowrite"})
+def cxp_readu32(channel: TInt32, addr: TInt32) -> TNone:
+    raise NotImplementedError("syscall not simulated")
+
+@syscall(flags={"nounwind", "nowrite"})
+def cxp_writeu32(channel: TInt32, addr: TInt32, val: TInt32) -> TNone:
+    raise NotImplementedError("syscall not simulated")
+
+
+
+class IdleKernel(EnvExperiment):
+    def build(self):
+        self.setattr_device("core")
+        self.setattr_device("led0")
+
+        # declare the class before using it in kernel
+        self.cxp = CoaXPress(0x0)
+
+    @kernel
+    def run(self):
+        self.core.reset()
+        # cxp_readu32(0, 3)
+        # cxp_writeu32(0, 0, 0xABCD)
+        self.cxp.trigger(1, 10)

flake.lock

@@ -3,19 +3,19 @@
     "artiq": {
       "inputs": {
         "artiq-comtools": "artiq-comtools",
-        "mozilla-overlay": "mozilla-overlay",
         "nixpkgs": "nixpkgs",
+        "rust-overlay": "rust-overlay",
         "sipyco": "sipyco",
         "src-migen": "src-migen",
         "src-misoc": "src-misoc",
         "src-pythonparser": "src-pythonparser"
       },
       "locked": {
-        "lastModified": 1716972728,
-        "narHash": "sha256-88J+eckZamtwhcCQkPpKLu6R1hmgj5+C9n2U5i+sHUE=",
+        "lastModified": 1725373154,
+        "narHash": "sha256-fq9EW9fDWrV0v1vNj7ZqDNpNYx8+OxoFdPwpvkPf67g=",
         "ref": "refs/heads/master",
-        "rev": "49e402780bebba437c6098047ab1dc68eaf5a17c",
-        "revCount": 8808,
+        "rev": "0c1ffa9f4f6a3e7864459923ec4b9cc45f16327a",
+        "revCount": 9005,
         "type": "git",
         "url": "https://github.com/m-labs/artiq.git"
       },
@@ -37,11 +37,11 @@
         ]
       },
       "locked": {
-        "lastModified": 1707216368,
-        "narHash": "sha256-ZXoqzG2QsVsybALLYXs473avXcyKSZNh2kIgcPo60XQ=",
+        "lastModified": 1720768567,
+        "narHash": "sha256-3VoK7o5MtHtbHLrc6Pv+eQWFtaz5Gd/YWyV5TD3c5Ss=",
         "owner": "m-labs",
         "repo": "artiq-comtools",
-        "rev": "e5d0204490bccc07ef9141b0d7c405ab01cb8273",
+        "rev": "f93570d8f2ed5a3cfb3e1c16ab00f2540551e994",
         "type": "github"
       },
       "original": {
@@ -55,11 +55,11 @@
         "systems": "systems"
       },
       "locked": {
-        "lastModified": 1694529238,
-        "narHash": "sha256-zsNZZGTGnMOf9YpHKJqMSsa0dXbfmxeoJ7xHlrt+xmY=",
+        "lastModified": 1710146030,
+        "narHash": "sha256-SZ5L6eA7HJ/nmkzGG7/ISclqe6oZdOZTNoesiInkXPQ=",
         "owner": "numtide",
         "repo": "flake-utils",
-        "rev": "ff7b65b44d01cf9ba6a71320833626af21126384",
+        "rev": "b1d9ab70662946ef0850d488da1c9019f3a9752a",
         "type": "github"
       },
       "original": {
@@ -100,34 +100,34 @@
         "type": "github"
       }
     },
-    "mozilla-overlay_3": {
-      "flake": false,
+    "nixpkgs": {
       "locked": {
-        "lastModified": 1704373101,
-        "narHash": "sha256-+gi59LRWRQmwROrmE1E2b3mtocwueCQqZ60CwLG+gbg=",
-        "owner": "mozilla",
-        "repo": "nixpkgs-mozilla",
-        "rev": "9b11a87c0cc54e308fa83aac5b4ee1816d5418a2",
+        "lastModified": 1724224976,
+        "narHash": "sha256-Z/ELQhrSd7bMzTO8r7NZgi9g5emh+aRKoCdaAv5fiO0=",
+        "owner": "NixOS",
+        "repo": "nixpkgs",
+        "rev": "c374d94f1536013ca8e92341b540eba4c22f9c62",
         "type": "github"
       },
       "original": {
-        "owner": "mozilla",
-        "repo": "nixpkgs-mozilla",
+        "owner": "NixOS",
+        "ref": "nixos-unstable",
+        "repo": "nixpkgs",
         "type": "github"
       }
     },
-    "nixpkgs": {
+    "nixpkgs_old": {
       "locked": {
-        "lastModified": 1716542732,
-        "narHash": "sha256-0Y9fRr0CUqWT4KgBITmaGwlnNIGMYuydu2L8iLTfHU4=",
-        "owner": "NixOS",
+        "lastModified": 1720535198,
+        "narHash": "sha256-zwVvxrdIzralnSbcpghA92tWu2DV2lwv89xZc8MTrbg=",
+        "owner": "nixos",
         "repo": "nixpkgs",
-        "rev": "d12251ef6e8e6a46e05689eeccd595bdbd3c9e60",
+        "rev": "205fd4226592cc83fd4c0885a3e4c9c400efabb5",
         "type": "github"
       },
       "original": {
-        "owner": "NixOS",
-        "ref": "nixos-24.05",
+        "owner": "nixos",
+        "ref": "nixos-23.11",
         "repo": "nixpkgs",
         "type": "github"
       }
@@ -135,10 +135,33 @@
     "root": {
       "inputs": {
         "artiq": "artiq",
-        "mozilla-overlay": "mozilla-overlay_2",
+        "mozilla-overlay": "mozilla-overlay",
+        "nixpkgs_old": "nixpkgs_old",
         "zynq-rs": "zynq-rs"
       }
     },
+    "rust-overlay": {
+      "inputs": {
+        "nixpkgs": [
+          "artiq",
+          "nixpkgs"
+        ]
+      },
+      "locked": {
+        "lastModified": 1719454714,
+        "narHash": "sha256-MojqG0lyUINkEk0b3kM2drsU5vyaF8DFZe/FAlZVOGs=",
+        "owner": "oxalica",
+        "repo": "rust-overlay",
+        "rev": "d1c527659cf076ecc4b96a91c702d080b213801e",
+        "type": "github"
+      },
+      "original": {
+        "owner": "oxalica",
+        "ref": "snapshot/2024-08-01",
+        "repo": "rust-overlay",
+        "type": "github"
+      }
+    },
     "sipyco": {
       "inputs": {
         "nixpkgs": [
@@ -147,11 +170,11 @@
         ]
       },
       "locked": {
-        "lastModified": 1708937641,
-        "narHash": "sha256-Hkb9VYFzFgkYxfbh4kYcDSn7DbMUYehoQDeTALrxo2Q=",
+        "lastModified": 1717637367,
+        "narHash": "sha256-4mSm9wl5EMgzzrW6w86IDUevkEOT99FESHGcxcyQbD0=",
         "owner": "m-labs",
         "repo": "sipyco",
-        "rev": "4a28b311ce0069454b4e8fe1e6049db11b9f1296",
+        "rev": "02b96ec2473a3c3d3c980899de2564ddce949dab",
         "type": "github"
       },
       "original": {
@@ -163,11 +186,11 @@
     "src-migen": {
       "flake": false,
       "locked": {
-        "lastModified": 1715484909,
-        "narHash": "sha256-4DCHBUBfc/VA+7NW2Hr0+JP4NnKPru2uVJyZjCCk0Ws=",
+        "lastModified": 1724304798,
+        "narHash": "sha256-tQ02N0eXY5W/Z7CrOy3Cu4WjDZDQWb8hYlzsFzr3Mus=",
         "owner": "m-labs",
         "repo": "migen",
-        "rev": "4790bb577681a8c3a8d226bc196a4e5deb39e4df",
+        "rev": "832a7240ba32af9cbd4fdd519ddcb4f912534726",
         "type": "github"
       },
       "original": {
@@ -227,18 +250,18 @@
     },
     "zynq-rs": {
       "inputs": {
-        "mozilla-overlay": "mozilla-overlay_3",
+        "mozilla-overlay": "mozilla-overlay_2",
         "nixpkgs": [
           "artiq",
           "nixpkgs"
         ]
       },
       "locked": {
-        "lastModified": 1716519432,
-        "narHash": "sha256-vgKBJCQRPCutJ4n+FtJNczMZULWW7J3B8icf/PUothw=",
+        "lastModified": 1720537402,
+        "narHash": "sha256-ybvaQ48SVBqYVqgYmGUdefGZkni7PJ90qYQPHnFOwDs=",
         "ref": "refs/heads/master",
-        "rev": "46dc25b89e46b9043129d77e3c9348916748e325",
-        "revCount": 645,
+        "rev": "b2b3e5c933cbc4b7cb14adde480d7561a3ae71ee",
+        "revCount": 648,
         "type": "git",
         "url": "https://git.m-labs.hk/m-labs/zynq-rs"
       },

flake.nix

@@ -6,23 +6,27 @@
   inputs.zynq-rs.url = git+https://git.m-labs.hk/m-labs/zynq-rs;
   inputs.zynq-rs.inputs.nixpkgs.follows = "artiq/nixpkgs";
 
-  outputs = { self, mozilla-overlay, zynq-rs, artiq }:
+  inputs.nixpkgs_old.url = "github:nixos/nixpkgs?ref=nixos-23.11";
+
+  outputs = { self, mozilla-overlay, zynq-rs, artiq, nixpkgs_old }:
   let
+    pkgs_old = import nixpkgs_old { system = "x86_64-linux";};
     pkgs = import artiq.inputs.nixpkgs { system = "x86_64-linux"; overlays = [ (import mozilla-overlay) ]; };
     zynqpkgs = zynq-rs.packages.x86_64-linux;
     artiqpkgs = artiq.packages.x86_64-linux;
-    llvmPackages_11 = zynq-rs.llvmPackages_11;
+    # llvmPackages_11 = zynq-rs.llvmPackages_11;
+    llvmPackages_11 = pkgs_old.llvmPackages_11;
 
     rust = zynq-rs.rust;
     rustPlatform = zynq-rs.rustPlatform;
 
     fastnumbers = pkgs.python3Packages.buildPythonPackage rec {
       pname = "fastnumbers";
-      version = "2.2.1";
+      version = "5.1.0";
 
       src = pkgs.python3Packages.fetchPypi {
         inherit pname version;
-        sha256 = "0j15i54p7nri6hkzn1wal9pxri4pgql01wgjccig6ar0v5jjbvsy";
+        sha256 = "sha256-4JLTP4uVwxcaL7NOV57+DFSwKQ3X+W/6onYkN2AdkKc=";
       };
     };
 
@@ -126,6 +130,7 @@
           lockFile = src/Cargo.lock;
           outputHashes = {
               "tar-no-std-0.1.8" = "sha256-xm17108v4smXOqxdLvHl9CxTCJslmeogjm4Y87IXFuM=";
+              "nalgebra-0.32.6" = "sha256-L/YudkVOtfGYoNQKBD7LMk/sMYgRDzPDdpGL5rO7G2I=";
             };
         };
 
@@ -341,6 +346,7 @@
       {
         inherit fastnumbers artiq-netboot ramda migen-axi binutils-arm;
       } //
+      (board-package-set { target = "zc706"; variant = "cxp_demo"; }) //
       (board-package-set { target = "zc706"; variant = "nist_clock"; }) //
       (board-package-set { target = "zc706"; variant = "nist_clock_master"; }) //
       (board-package-set { target = "zc706"; variant = "nist_clock_master_100mhz"; }) //
@@ -379,7 +385,7 @@
         zynqpkgs.mkbootimage
         openocd  
         openssh rsync
-        (python3.withPackages(ps: (with artiqpkgs; [ migen migen-axi misoc artiq artiq-netboot ps.jsonschema ps.pyftdi ])))
+        (python3.withPackages(ps: (with artiqpkgs; [ migen migen-axi misoc artiq artiq-netboot ps.jsonschema ps.pyftdi ps.pillow ])))
         artiqpkgs.artiq
         artiqpkgs.vivado
         binutils-arm

local_run.sh

@@ -13,7 +13,7 @@ fi
 
 impure=0
 load_bitstream=1
-board_type="kasli_soc"
+board_type="zc706"
 fw_type="runtime"
 
 while getopts "ilb:t:f:" opt; do
@@ -36,7 +36,7 @@ done
 if [ -z "$board_host" ]; then
     case $board_type in
     kasli_soc) board_host="192.168.1.56";;
-    zc706) board_host="192.168.1.52";;
+    zc706) board_host="192.168.1.14";;
     *) echo "Unknown board type"; exit 1;;
     esac
 fi
@@ -58,4 +58,4 @@ else
         load_bitstream_cmd="-g $result_dir/top.bit"
     fi
     artiq_netboot $load_bitstream_cmd -f $result_dir/$fw_type.bin -b $board_host
-fi
+fi

sim_frame.py

@@ -0,0 +1,134 @@
+from migen import *
+from misoc.interconnect import stream
+
+from sim_generator import CXPCRC32Inserter
+from sim_frame_gen import get_frame_packet
+
+from src.gateware.cxp_pipeline import *
+from src.gateware.cxp_frame_pipeline import *
+
+import numpy as np
+from PIL import Image
+
+
+class Frame(Module):
+    def __init__(self):
+        # to construct correct crc and ack/stb signal
+        self.submodules.buffer = buffer = stream.SyncFIFO(word_layout, 32)
+        self.submodules.crc_inserter = crc_inserter = CXPCRC32Inserter()
+        self.submodules.dchar_decoder = dchar_decoder = Duplicated_Char_Decoder()
+
+        # NOTE: eop is needed for crc to work correctly and RX_Bootstrap need to be followed by a EOP marker anyway
+        self.submodules.eop_marker = eop_marker = EOP_Marker()
+
+        self.submodules.stream_pipe = stream_pipe = Stream_Pipeline()
+
+        pipeline = [buffer, crc_inserter, dchar_decoder, eop_marker, stream_pipe]
+        for s, d in zip(pipeline, pipeline[1:]):
+            self.comb += s.source.connect(d.sink)
+        self.sink = pipeline[0].sink
+        self.source = pipeline[-1].source
+
+        # no backpressure for sim
+        self.sync += self.source.ack.eq(1)
+
+
+dut = Frame()
+
+
+def check_case(packet=[]):
+    print("=================TEST========================")
+
+    sink = dut.sink
+    stream_pipe = dut.stream_pipe
+
+    for i, p in enumerate(packet):
+        yield sink.data.eq(p["data"])
+        yield sink.k.eq(p["k"])
+        yield sink.stb.eq(1)
+        if "eop" in p:
+            yield sink.eop.eq(1)
+        else:
+            yield sink.eop.eq(0)
+
+        # check cycle result
+        yield
+        # source = dut.dchar_decoder.source
+        # source = dut.stream_pipe.frame_extractor.sink
+        source = dut.sink
+        # print(
+        #     f"\nCYCLE#{i} : source char = {yield source.data:#X} k = {yield source.k:#X} stb = {yield source.stb} ack = {yield source.ack} eop = {yield source.eop}"
+        # )
+
+    # extra clk cycles
+    cyc = i + 1
+    img = []
+    line = -1
+    total_pixel = 1000
+    for i in range(cyc, cyc + total_pixel):
+        yield sink.data.eq(0)
+        yield sink.k.eq(0)
+        yield sink.stb.eq(0)
+        yield sink.eop.eq(0)
+        yield
+        # print(
+        #     f"\nCYCLE#{i} : source char = {yield source.data:#X} k = {yield source.k:#X} stb = {yield source.stb} ack = {yield source.ack} eop = {yield source.eop}"
+        # )
+
+        frame_extractoer = dut.stream_pipe.frame_extractor
+        new_line = yield frame_extractoer.new_line
+        if new_line:
+            img.append([])
+            line += 1
+            
+        stb = yield frame_extractoer.source.stb 
+        data = yield frame_extractoer.source.data
+        if stb:
+            # CXP use MSB
+            img[line].append(np.uint16(data & 0xFFFF))
+            img[line].append(np.uint16(data >> 16))
+
+        # metadata = dut.stream_pipe.frame_extractor.metadata
+        # img_header_layout = [
+        #     "stream_id",
+        #     "source_tag",
+        #     "x_size",
+        #     "x_offset",
+        #     "y_size",
+        #     "y_offset",
+        #     "l_size",  # number of data words per image line
+        #     "pixel_format",
+        #     "tap_geo",
+        #     "flag",
+        # ]
+        # for name in img_header_layout:
+        #     print(f"{name} = {yield getattr(metadata, name):#04X} ", end="")
+        # print()
+    Image.fromarray(np.array(img, dtype=np.uint8)).show()
+    assert True
+
+
+def testbench():
+    stream_id = 0x69
+    packet_tag = 0
+    frame_packet = get_frame_packet(stream_id)
+    packet = [
+        {"data": Replicate(C(stream_id, char_width), 4), "k": Replicate(0, 4)},
+        {"data": Replicate(C(packet_tag, char_width), 4), "k": Replicate(0, 4)},
+        {
+            "data": Replicate(C(len(frame_packet), 2*char_width)[8:], 4),
+            "k": Replicate(0, 4),
+        },
+        {
+            "data": Replicate(C(len(frame_packet), 2*char_width)[:8], 4),
+            "k": Replicate(0, 4),
+        },
+    ]
+    packet += frame_packet
+    # NOTE: for crc inserter!!!!
+    packet[-1]["eop"] = 0
+
+    yield from check_case(packet)
+
+
+run_simulation(dut, testbench(), vcd_name="sim-cxp.vcd")

sim_frame_gen.py

@@ -0,0 +1,148 @@
+from migen import *
+from misoc.interconnect import stream
+
+from src.gateware.cxp_pipeline import *
+from src.gateware.cxp_frame_pipeline import *
+
+from PIL import Image
+import numpy as np
+
+
+def get_image_header(
+    stream_id, source_tag, xsize, xoffset, ysize, yoffset, dsize, pixelF, tag_geo, flag
+):
+    stream_id = C(stream_id, char_width)
+    source_tag = C(source_tag, 2 * char_width)
+    xsize = C(xsize, 3 * char_width)
+    xoffset = C(xoffset, 3 * char_width)
+    ysize = C(ysize, 3 * char_width)
+    yoffset = C(yoffset, 3 * char_width)
+    dsize = C(dsize, 3 * char_width)
+    pixelF = C(pixelF, 2 * char_width)
+    tag_geo = C(tag_geo, 2 * char_width)
+    flag = C(flag, char_width)
+
+    assert len(stream_id) == len(flag) == char_width
+    assert len(source_tag) == len(pixelF) == len(tag_geo) == 2 * char_width
+    assert len(xsize) == len(xoffset) == len(ysize) == len(yoffset) == 3 * char_width
+    return [
+        {"data": Replicate(KCode["stream_marker"], 4), "k": Replicate(1, 4)},
+        {"data": Replicate(C(0x01, char_width), 4), "k": Replicate(0, 4)},
+        {"data": Replicate(stream_id, 4), "k": Replicate(0, 4)},
+        {"data": Replicate(source_tag[8:], 4), "k": Replicate(0, 4)},
+        {"data": Replicate(source_tag[:8], 4), "k": Replicate(0, 4)},
+        {"data": Replicate(xsize[16:], 4), "k": Replicate(0, 4)},
+        {"data": Replicate(xsize[8:16], 4), "k": Replicate(0, 4)},
+        {"data": Replicate(xsize[:8], 4), "k": Replicate(0, 4)},
+        {"data": Replicate(xoffset[16:], 4), "k": Replicate(0, 4)},
+        {"data": Replicate(xoffset[8:16], 4), "k": Replicate(0, 4)},
+        {"data": Replicate(xoffset[:8], 4), "k": Replicate(0, 4)},
+        {"data": Replicate(ysize[16:], 4), "k": Replicate(0, 4)},
+        {"data": Replicate(ysize[8:16], 4), "k": Replicate(0, 4)},
+        {"data": Replicate(ysize[:8], 4), "k": Replicate(0, 4)},
+        {"data": Replicate(yoffset[16:], 4), "k": Replicate(0, 4)},
+        {"data": Replicate(yoffset[8:16], 4), "k": Replicate(0, 4)},
+        {"data": Replicate(yoffset[:8], 4), "k": Replicate(0, 4)},
+        {"data": Replicate(dsize[16:], 4), "k": Replicate(0, 4)},
+        {"data": Replicate(dsize[8:16], 4), "k": Replicate(0, 4)},
+        {"data": Replicate(dsize[:8], 4), "k": Replicate(0, 4)},
+        {"data": Replicate(pixelF[8:], 4), "k": Replicate(0, 4)},
+        {"data": Replicate(pixelF[:8], 4), "k": Replicate(0, 4)},
+        {"data": Replicate(tag_geo[8:], 4), "k": Replicate(0, 4)},
+        {"data": Replicate(tag_geo[:8], 4), "k": Replicate(0, 4)},
+        {"data": Replicate(flag, 4), "k": Replicate(0, 4)},
+    ]
+
+
+def get_line_marker():
+    return [
+        {"data": Replicate(KCode["stream_marker"], 4), "k": Replicate(1, 4)},
+        {"data": Replicate(C(0x02, char_width), 4), "k": Replicate(0, 4)},
+    ]
+
+
+def get_frame_packet(stream_id, pixel_format="mono16"):
+    assert pixel_format in ["mono16"]
+
+    arr = [
+        [204, 200, 203, 205, 190, 187, 189, 205, 214, 197, 188, 185, 181, 178, 193, 209, 211, 207, 211, 192, 168, 168, 171, 199, 210, 212, 203, 196],
+        [218, 205, 199, 190, 192, 197, 196, 195, 184, 178, 182, 173, 166, 132, 122, 114, 154, 184, 187, 188, 171, 168, 170, 180, 192, 196, 202, 198],
+        [223, 222, 222, 224, 216, 199, 199, 207, 205, 189, 183, 182, 144, 66,  61,  66, 80, 148, 181, 175, 169, 170, 174, 177, 196, 206, 223, 218],
+        [221, 226, 225, 222, 211, 200, 202, 208, 215, 201, 187, 180, 133, 116, 113, 118, 96, 111, 206, 193, 170, 169, 186, 211, 218, 224, 231, 223],
+        [219, 216, 206, 197, 210, 201, 206, 203, 191, 190, 185, 145, 134, 140, 159, 170, 150, 116, 180, 173, 179, 170, 172, 185, 201, 218, 227, 227],
+        [203, 198, 194, 208, 227, 201, 201, 201, 215, 221, 209, 170, 136, 113, 141, 139, 141, 145, 188, 170, 180, 169, 184, 173, 174, 192, 215, 230],
+        [206, 224, 213, 213, 233, 207, 204, 226, 233, 227, 214, 166, 145, 123, 145, 155, 147, 186, 213, 187, 171, 169, 193, 193, 171, 178, 186, 207],
+        [212, 228, 216, 205, 214, 205, 204, 230, 235, 225, 219, 187, 143, 122, 146, 163, 158, 195, 209, 203, 174, 168, 190, 185, 187, 202, 180, 174],
+        [197, 206, 201, 223, 213, 201, 203, 231, 234, 225, 218, 206, 147, 125, 149, 155, 190, 208, 206, 203, 175, 168, 171, 179, 184, 206, 189, 176],
+        [213, 202, 209, 235, 223, 200, 202, 202, 227, 227, 202, 176, 138, 122, 144, 153, 190, 209, 207, 191, 172, 167, 179, 204, 190, 191, 180, 193],
+        [225, 225, 207, 231, 219, 197, 215, 200, 194, 199, 181, 172, 131, 129, 147, 159, 113, 175, 196, 179, 184, 169, 181, 210, 202, 204, 200, 177],
+        [208, 222, 204, 223, 210, 191, 195, 198, 203, 167, 171, 168, 135, 129, 149, 175,  66,  57,  90, 121, 147, 165, 181, 205, 195, 217, 209, 173],
+        [188, 216, 201, 206, 199, 180, 185, 180, 129,  75, 139, 166, 124, 146, 189, 135,  51,  41,  38,  40,  45,  63, 131, 201, 189, 215, 193, 170],
+        [188, 194, 195, 192, 182, 180, 134,  68,  45,  41,  96, 130, 116, 156, 163,  64,  46,  41,  43,  41,  42,  42,  74, 181, 177, 198, 175, 193],
+        [179, 179, 209, 224, 198, 182,  99,  42,  44,  41,  44, 100, 116, 125, 100,  46,  45,  42,  42,  37,  44,  43,  49, 150, 183, 170, 172, 198],
+        [175, 177, 208, 223, 197, 180,  94,  40,  42,  40,  41,  99, 134, 117,  80,  43,  46,  43,  37,  37,  44,  42,  35, 129, 195, 170, 170, 180],
+        [179, 181, 187, 217, 193, 175,  91,  38,  41,  41,  42, 106, 151, 107,  62,  43,  45,  41,  33,  38,  42,  34,  33,  77, 188, 175, 173, 208],
+        [190, 191, 180, 213, 194, 175,  78,  38,  40,  40,  40,  98, 134, 97,  51,  44,  59,  50,  37,  40,  36,  26,  36,  44, 100, 178, 192, 206],
+        [199, 191, 184, 204, 196, 176,  78,  33,  38,  38,  39,  80, 102, 83,  43,  44, 112, 130, 122,  63,  33,  24,  29,  34,  33,  74, 162, 195],
+        [191, 170, 196, 193, 186, 177,  88,  27,  34,  37,  36,  74, 101, 70,  36,  37,  81, 127, 137, 113,  40,  28,  30,  32,  36,  29, 69, 173],
+        [164, 189, 190, 180, 176, 172,  83,  26,  28,  33,  32,  68,  97, 62,  32,  30,  44,  97, 123, 136,  58,  42,  44,  43,  43,  40, 58, 162],
+        [177, 202, 205, 181, 174, 163,  78,  38,  35,  47,  54,  67,  92, 51,  28,  29,  26,  21,  39,  85,  47,  46,  52,  47,  46,  45, 48, 141],
+        [181, 193, 199, 192, 171, 163,  91,  67, 121, 123,  91,  63,  89, 45,  25,  25,  23,  20,  15,  13,  20,  48,  54,  35,  34,  34, 68, 146],
+        [175, 192, 195, 179, 165, 163, 100,  64,  99,  94,  82,  58,  83, 37,  23,  22,  22,  27,  21,  15,  14,  44,  98,  83,  94, 118, 164, 157],
+        [153, 184, 171, 163, 161, 157, 140,  70,  58,  89,  61,  53,  76, 30,  20,  20,  20,  31,  24,  19,  16,  47, 159, 163, 160, 171, 160, 142],
+        [142, 150, 161, 168, 154, 154, 164, 138,  76,  55,  26,  37,  62, 24,  19,  19,  20,  21,  23,  27,  31,  46, 142, 156, 151, 153, 147, 145],
+        [153, 147, 174, 171, 151, 150, 169, 158, 142,  92,  28,  60,  59, 20,  20,  18,  20,  26,  27,  29,  33,  38, 125, 153, 150, 147, 147, 148],
+        [138, 141, 166, 164, 146, 144, 164, 149, 132,  72,  34,  88,  72, 24,  19,  18,  18,  23,  25,  28,  31,  30,  98, 150, 146, 144, 146, 144]
+    ]
+    source_tag = 0
+    xsize, ysize = len(arr[0]), len(arr)
+
+    xoffset, yoffset = 0, 0
+    if pixel_format == "mono16":
+        dsize = xsize // 2
+        pixelF = 0x0105
+    tag_geo = 0
+    flag = 0
+
+    packet = []
+    # Image header
+    packet += get_image_header(
+        stream_id,
+        source_tag,
+        xsize,
+        xoffset,
+        ysize,
+        yoffset,
+        dsize,
+        pixelF,
+        tag_geo,
+        flag,
+    )
+
+    for line in arr:
+        packet += get_line_marker()
+        if pixel_format == "mono16":
+            for i in range(len(line)):
+                if (i % 2) == 0:
+                    if i == len(line) - 1:
+                        # print(C(line[i]))
+                        packet += [
+                            {
+                                "data": C(line[i], 4 * char_width),
+                                "k": Replicate(0, 4),
+                            },
+                        ]
+                    else:
+                        # print(C(line[i], 2 * char_width), C(line[i + 1]))
+                        # CXP use MSB
+                        packet += [
+                            {
+                                "data": Cat(
+                                    C(line[i], 2 * char_width),
+                                    C(line[i + 1], 2 * char_width),
+                                ),
+                                "k": Replicate(0, 4),
+                            },
+                        ]
+
+    return packet

sim_generator.py

@@ -0,0 +1,120 @@
+from migen import *
+from misoc.interconnect.csr import *
+from misoc.interconnect import stream
+
+from src.gateware.cxp_frame_pipeline import CXPCRC32
+from src.gateware.cxp_pipeline import *
+
+class CXPCRC32Inserter(Module):
+    def __init__(self):
+        self.sink = stream.Endpoint(word_layout)
+        self.source = stream.Endpoint(word_layout)
+
+        # # #
+
+        self.submodules.crc = crc = CXPCRC32(word_dw)
+        self.submodules.fsm = fsm = FSM(reset_state="IDLE")
+
+        fsm.act(
+            "IDLE",
+            crc.reset.eq(1),
+            self.sink.ack.eq(1),
+            If(
+                self.sink.stb,
+                self.sink.ack.eq(0),
+                NextState("COPY"),
+            ),
+        )
+        fsm.act(
+            "COPY",
+            crc.ce.eq(self.sink.stb & self.source.ack),
+            crc.data.eq(self.sink.data),
+            self.sink.connect(self.source),
+            self.source.eop.eq(0),
+            If(
+                self.sink.stb & self.sink.eop & self.source.ack,
+                NextState("INSERT"),
+            ),
+        )
+        fsm.act(
+            "INSERT",
+            self.source.stb.eq(1),
+            self.source.eop.eq(1),
+            self.source.data.eq(crc.value),
+            If(self.source.ack, NextState("IDLE")),
+        )
+
+
+class StreamPacket_Wrapper(Module):
+    def __init__(self):
+        self.sink = stream.Endpoint(word_layout)
+        self.source = stream.Endpoint(word_layout)
+
+        # # #
+
+        self.submodules.fsm = fsm = FSM(reset_state="IDLE")
+
+        fsm.act(
+            "IDLE",
+            self.sink.ack.eq(1),
+            If(
+                self.sink.stb,
+                self.sink.ack.eq(0),
+                NextState("INSERT_HEADER_0"),
+            ),
+        )
+
+        fsm.act(
+            "INSERT_HEADER_0",
+            self.sink.ack.eq(0),
+            self.source.stb.eq(1),
+            self.source.data.eq(Replicate(KCode["pak_start"], 4)),
+            self.source.k.eq(Replicate(1, 4)),
+            If(self.source.ack, NextState("INSERT_HEADER_1")),
+        )
+
+        fsm.act(
+            "INSERT_HEADER_1",
+            self.sink.ack.eq(0),
+            self.source.stb.eq(1),
+            self.source.data.eq(Replicate(C(0x01, char_width), 4)),
+            self.source.k.eq(Replicate(0, 4)),
+            If(self.source.ack, NextState("COPY")),
+        )
+
+        fsm.act(
+            "COPY",
+            self.sink.connect(self.source),
+            self.source.eop.eq(0),
+            If(
+                self.sink.stb & self.sink.eop & self.source.ack,
+                NextState("INSERT_FOOTER"),
+            ),
+        )
+
+        fsm.act(
+            "INSERT_FOOTER",
+            self.sink.ack.eq(0),
+            self.source.stb.eq(1),
+            self.source.data.eq(Replicate(KCode["pak_end"], 4)),
+            self.source.k.eq(Replicate(1, 4)),
+            # Simulate RX don't have eop tagged
+            # self.source.eop.eq(1),
+            If(self.source.ack, NextState("IDLE")),
+        )
+
+
+# With KCode & 0x01*4
+class StreamData_Generator(Module):
+    def __init__(self):
+        # should be big enough for all test
+        self.submodules.buffer = buffer = stream.SyncFIFO(word_layout, 32)
+        self.submodules.crc_inserter = crc_inserter = CXPCRC32Inserter()
+        self.submodules.wrapper = wrapper = StreamPacket_Wrapper()
+
+        # # #
+        pipeline = [buffer, crc_inserter, wrapper]
+        for s, d in zip(pipeline, pipeline[1:]):
+            self.comb += s.source.connect(d.sink)
+        self.sink = pipeline[0].sink
+        self.source = pipeline[-1].source

sim_stream.py

@@ -0,0 +1,154 @@
+from migen import *
+from misoc.interconnect import stream
+
+from sim_pipeline import *
+from sim_generator import StreamData_Generator
+
+from src.gateware.cxp_pipeline import *
+
+class CXP_Links(Module):
+    def __init__(self):
+        # TODO: select the correct buffer to read from
+        # NOTE: although there are double buffer in each connect, the reading must be faster than writing to avoid data loss
+
+        self.downconn_sources = []
+        self.stream_sinks = []
+        for i in range(2):
+            downconn = Pipeline()
+            setattr(self.submodules, "cxp_conn"+str(i), downconn)
+            self.downconn_sources.append(downconn)
+
+            stream_pipeline = Stream_Pipeline()
+            setattr(self.submodules, "stream_pipeline"+str(i), stream_pipeline)
+            self.stream_sinks.append(stream_pipeline)
+
+        self.submodules.crossbar = Streams_Crossbar(self.downconn_sources, self.stream_sinks)
+        
+class Pipeline(Module):
+    def __init__(self):
+        self.submodules.generator = generator = StreamData_Generator()
+        self.submodules.dchar_decoder = dchar_decoder = Duplicated_Char_Decoder()
+        self.submodules.data_decoder = data_decoder = RX_Bootstrap()
+        self.submodules.eop_marker = eop_marker = EOP_Marker()
+
+        # # #
+
+        pipeline = [generator, dchar_decoder, data_decoder, eop_marker]
+        for s, d in zip(pipeline, pipeline[1:]):
+            self.comb += s.source.connect(d.sink)
+        self.sink = pipeline[0].sink
+        self.source = pipeline[-1].source
+
+        # self.comb += self.source.ack.eq(1)
+
+
+dut = CXP_Links()
+
+def check_case(packet=[]):
+    print("=================TEST========================")
+
+    downconns = dut.downconn_sources
+    stream_buffers = dut.stream_sinks
+    ch = 0
+    
+    for i, p in enumerate(packet):
+        for x in range(len(downconns)):
+            if x == ch:
+                yield downconns[x].sink.data.eq(p["data"])
+                yield downconns[x].sink.k.eq(p["k"])
+                yield downconns[x].sink.stb.eq(1)
+            else:
+                yield downconns[x].sink.data.eq(0)
+                yield downconns[x].sink.k.eq(0)
+                yield downconns[x].sink.stb.eq(0)
+                yield downconns[x].sink.eop.eq(0)
+        if "eop" in p:
+            yield downconns[ch].sink.eop.eq(1)
+            # compensate for delay
+            # yield
+            # yield downconns[ch].sink.data.eq(0)
+            # yield downconns[ch].sink.k.eq(0)
+            # yield downconns[ch].sink.stb.eq(0)
+            # yield downconns[ch].sink.eop.eq(0)
+            # yield
+            # yield
+            # yield
+            ch = (ch + 1) % len(downconns)
+        else:
+            yield downconns[ch].sink.eop.eq(0)
+
+        # check cycle result
+        yield
+        # source = dut.stream_pipeline_sinks[0].source
+        source = dut.stream_sinks[0].double_buffer.source
+        print(
+            f"\nCYCLE#{i} : source char = {yield source.data:#X} k = {yield source.k:#X} stb = {yield source.stb} ack = {yield source.ack} eop = {yield source.eop}"
+            # f" source dchar = {yield source.dchar:#X} dchar_k = {yield source.dchar_k:#X}"
+            f"\nCYCLE#{i} : read mask = {yield dut.crossbar.mux.sel}"
+            # f"\nCYCLE#{i} : stream id = {yield decoder.stream_id:#X} pak_tag = {yield decoder.pak_tag:#X}"
+            # f" stream_pak_size = {yield decoder.stream_pak_size:#X}"
+        )
+        # crc = downconns[1].generator.crc_inserter.crc
+        # crc = dut.double_buffer.crc
+        # print(
+        #     f"CYCLE#{i} : crc error = {yield crc.error:#X} crc value = {yield crc.value:#X}"
+        #     f" crc data = {yield crc.data:#X} engine next = {yield crc.engine.next:#X} ce = {yield crc.ce}"
+        # )
+
+            
+    # extra clk cycles
+    cyc = i + 1
+    for i in range(cyc, cyc + 30):
+        for x in range(len(downconns)):
+            # yield won't reset every cycle
+            yield downconns[x].sink.data.eq(0)
+            yield downconns[x].sink.k.eq(0)
+            yield downconns[x].sink.stb.eq(0)
+            yield downconns[x].sink.eop.eq(0)
+        yield
+        print(
+            f"\nCYCLE#{i} : source char = {yield source.data:#X} k = {yield source.k:#X} stb = {yield source.stb} ack = {yield source.ack} eop = {yield source.eop}"
+            # f" source dchar = {yield source.dchar:#X} dchar_k = {yield source.dchar_k:#X}"
+            f"\nCYCLE#{i} : read mask = {yield dut.crossbar .mux.sel}"
+            # f"\nCYCLE#{i} : stream id = {yield decoder.stream_id:#X} pak_tag = {yield decoder.pak_tag:#X}"
+            # f" stream_pak_size = {yield decoder.stream_pak_size:#X}"
+        )
+    assert True
+
+
+def testbench():
+    # stream_id = 0x01
+    streams = [
+        [
+            {"data": 0x11111111, "k": Replicate(0, 4)},
+            {"data": 0xB105F00D, "k": Replicate(0, 4)},
+        ],
+        [
+            {"data": 0x22222222, "k": Replicate(0, 4)},
+            {"data": 0xC001BEA0, "k": Replicate(0, 4)},
+        ],
+        [
+            {"data": 0x33333333, "k": Replicate(0, 4)},
+            {"data": 0xC0A79AE5, "k": Replicate(0, 4)},
+        ],
+    ]
+
+    packet = []
+    for i, s in enumerate(streams):
+        s[-1]["eop"] = 0
+        packet += [
+            {"data": Replicate(C(i % 2, char_width), 4), "k": Replicate(0, 4)},
+            {"data": Replicate(C(i, char_width), 4), "k": Replicate(0, 4)},
+            {
+                "data": Replicate(C(len(s) >> 8 & 0xFF, char_width), 4),
+                "k": Replicate(0, 4),
+            },
+            {"data": Replicate(C(len(s) & 0xFF, char_width), 4), "k": Replicate(0, 4)},
+            *s,
+        ]
+
+
+    yield from check_case(packet)
+
+
+run_simulation(dut, testbench(), vcd_name="sim-cxp.vcd")

src/Cargo.lock

@@ -2,6 +2,15 @@
 # It is not intended for manual editing.
 version = 3
 
+[[package]]
+name = "approx"
+version = "0.5.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "cab112f0a86d568ea0e627cc1d6be74a1e9cd55214684db5561995f6dad897c6"
+dependencies = [
+ "num-traits",
+]
+
 [[package]]
 name = "arrayvec"
 version = "0.7.4"
@@ -246,6 +255,7 @@ dependencies = [
  "libsupport_zynq",
  "log",
  "log_buffer",
+ "nalgebra",
  "nb 0.1.3",
  "unwind",
  "vcell",
@@ -268,6 +278,7 @@ name = "libboard_artiq"
 version = "0.0.0"
 dependencies = [
  "build_zynq",
+ "byteorder",
  "core_io",
  "crc",
  "embedded-hal",
@@ -382,6 +393,19 @@ version = "0.7.2"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "c75de51135344a4f8ed3cfe2720dc27736f7711989703a0b43aadf3753c55577"
 
+[[package]]
+name = "nalgebra"
+version = "0.32.6"
+source = "git+https://git.m-labs.hk/M-Labs/nalgebra.git?rev=dd00f9b#dd00f9b46046e0b931d1b470166db02fd29591be"
+dependencies = [
+ "approx",
+ "num-complex",
+ "num-rational",
+ "num-traits",
+ "simba",
+ "typenum",
+]
+
 [[package]]
 name = "nb"
 version = "0.1.3"
@@ -397,6 +421,15 @@ version = "1.0.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "546c37ac5d9e56f55e73b677106873d9d9f5190605e41a856503623648488cae"
 
+[[package]]
+name = "num-complex"
+version = "0.4.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "26873667bbbb7c5182d4a37c1add32cdf09f841af72da53318fdb81543c15085"
+dependencies = [
+ "num-traits",
+]
+
 [[package]]
 name = "num-derive"
 version = "0.3.3"
@@ -408,6 +441,26 @@ dependencies = [
  "syn",
 ]
 
+[[package]]
+name = "num-integer"
+version = "0.1.46"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "7969661fd2958a5cb096e56c8e1ad0444ac2bbcd0061bd28660485a44879858f"
+dependencies = [
+ "num-traits",
+]
+
+[[package]]
+name = "num-rational"
+version = "0.4.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "d41702bd167c2df5520b384281bc111a4b5efcf7fbc4c9c222c815b07e0a6a6a"
+dependencies = [
+ "autocfg",
+ "num-integer",
+ "num-traits",
+]
+
 [[package]]
 name = "num-traits"
 version = "0.2.15"
@@ -415,8 +468,15 @@ source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "578ede34cf02f8924ab9447f50c28075b4d3e5b269972345e7e0372b38c6cdcd"
 dependencies = [
  "autocfg",
+ "libm",
 ]
 
+[[package]]
+name = "paste"
+version = "1.0.15"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "57c0d7b74b563b49d38dae00a0c37d4d6de9b432382b2892f0574ddcae73fd0a"
+
 [[package]]
 name = "pin-project-lite"
 version = "0.2.9"
@@ -523,6 +583,18 @@ version = "0.1.20"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "d4f410fedcf71af0345d7607d246e7ad15faaadd49d240ee3b24e5dc21a820ac"
 
+[[package]]
+name = "simba"
+version = "0.8.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "50582927ed6f77e4ac020c057f37a268fc6aebc29225050365aacbb9deeeddc4"
+dependencies = [
+ "approx",
+ "num-complex",
+ "num-traits",
+ "paste",
+]
+
 [[package]]
 name = "smoltcp"
 version = "0.7.5"
@@ -555,6 +627,12 @@ dependencies = [
  "log",
 ]
 
+[[package]]
+name = "typenum"
+version = "1.17.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "42ff0bf0c66b8238c6f3b578df37d0b7848e55df8577b3f74f92a69acceeb825"
+
 [[package]]
 name = "unicode-ident"
 version = "1.0.5"

src/gateware/cxp.py

@@ -0,0 +1,381 @@
+from migen import *
+from migen.genlib.cdc import MultiReg, PulseSynchronizer
+from misoc.interconnect.csr import *
+
+from artiq.gateware.rtio import rtlink
+
+from cxp_downconn import CXP_DownConn_PHYS
+from cxp_upconn import CXP_UpConn_PHYS
+from cxp_pipeline import *
+
+
+class CXP_PHYS(Module, AutoCSR):
+    def __init__(self, refclk, upconn_pads, downconn_pads, sys_clk_freq, debug_sma, pmod_pads):
+        assert len(upconn_pads) == len(downconn_pads)
+
+        self.submodules.upconn = CXP_UpConn_PHYS(upconn_pads, sys_clk_freq, debug_sma, pmod_pads)
+        self.submodules.downconn = CXP_DownConn_PHYS(refclk, downconn_pads, sys_clk_freq, debug_sma, pmod_pads)
+
+@FullMemoryWE()
+class CXP_Interface(Module, AutoCSR):
+    def __init__(self, upconn_phy, downconn_phy, debug_sma, pmod_pads):
+        self.submodules.upconn = UpConn_Interface(upconn_phy, debug_sma, pmod_pads)
+        self.submodules.downconn = DownConn_Interface(downconn_phy, debug_sma, pmod_pads)
+
+    def get_tx_port(self):
+        return self.upconn.bootstrap.mem.get_port(write_capable=True)
+
+    def get_tx_mem_size(self):
+        # FIXME: if tx mem size is same as rx, for some reason when rx mem is writen, tx mem cannot be access anymore
+        # and each time tx mem is read, CPU will return rx mem instead
+        return self.upconn.bootstrap.mem.depth*self.upconn.bootstrap.mem.width // 8
+        # return self.downconn.bootstrap.mem.depth*self.downconn.bootstrap.mem.width // 8
+
+    def get_rx_port(self):
+        return self.downconn.bootstrap.mem.get_port(write_capable=False)
+
+    def get_rx_mem_size(self):
+        return self.downconn.bootstrap.mem.depth*self.downconn.bootstrap.mem.width // 8
+
+    def get_loopback_tx_port(self):
+        return self.downconn.bootstrap_loopback.mem.get_port(write_capable=True)
+    
+    def get_loopback_tx_mem_size(self):
+        return self.downconn.bootstrap_loopback.mem.depth*self.downconn.bootstrap_loopback.mem.width // 8
+
+class CXP_Master(CXP_Interface):
+    def __init__(self, upconn_phy, downconn_phy, debug_sma, pmod_pads):
+        CXP_Interface.__init__(self, upconn_phy, downconn_phy, debug_sma, pmod_pads)
+        nbit_trigdelay = 8
+        nbit_linktrig = 1
+
+        self.rtlink = rtlink.Interface(
+            rtlink.OInterface(nbit_trigdelay + nbit_linktrig),
+            rtlink.IInterface(word_dw, timestamped=False)
+        )
+
+        self.sync.rio += [
+            If(self.rtlink.o.stb,
+                self.upconn.trig.delay.eq(self.rtlink.o.data[nbit_linktrig:]),
+                self.upconn.trig.linktrig_mode.eq(self.rtlink.o.data[:nbit_linktrig]),
+            ),
+            self.upconn.trig.stb.eq(self.rtlink.o.stb),
+        ]
+
+        # DEBUG: out
+        self.specials += Instance("OBUF", i_I=self.rtlink.o.stb, o_O=debug_sma.p_tx),
+        # self.specials += Instance("OBUF", i_I=self.rtlink.o.stb, o_O=debug_sma.n_rx),
+
+class CXP_Extension(CXP_Interface):
+    def __init__(self, upconn_phy, downconn_phy, debug_sma, pmod_pads):
+        CXP_Interface.__init__(self, upconn_phy, downconn_phy, debug_sma, pmod_pads)
+
+
+class DownConn_Interface(Module, AutoCSR):
+    def __init__(self, phy, debug_sma, pmod_pads):
+        self.rx_start_init = CSRStorage()
+        self.rx_restart = CSR()
+        self.rx_ready = CSRStatus()
+
+        # # #
+
+        gtx = phy.gtx
+
+        # GTX Control
+        self.sync += [
+            gtx.rx_restart.eq(self.rx_restart.re),
+            gtx.rx_init.clk_path_ready.eq(self.rx_start_init.storage),
+            self.rx_ready.status.eq(gtx.rx_ready),
+        ]
+
+
+        # DEBUG: tx control
+        self.tx_start_init = CSRStorage()
+        self.tx_restart = CSR()
+        self.txenable = CSRStorage()
+        self.sync += [
+            gtx.txenable.eq(self.txenable.storage),
+            gtx.tx_restart.eq(self.tx_restart.re),
+            gtx.tx_init.clk_path_ready.eq(self.tx_start_init.storage),
+        ]
+
+        # DEBUG: loopback control
+        self.loopback_mode = CSRStorage(3)
+        self.comb += gtx.loopback_mode.eq(self.loopback_mode.storage) 
+
+        
+        # DEBUG: init status
+        self.txinit_phaligndone = CSRStatus()
+        self.rxinit_phaligndone = CSRStatus()
+        self.comb += [
+            self.txinit_phaligndone.status.eq(gtx.tx_init.Xxphaligndone),
+            self.rxinit_phaligndone.status.eq(gtx.rx_init.Xxphaligndone),
+        ]
+
+        # Connect all GTX connections' DRP
+        self.gtx_daddr = CSRStorage(9)
+        self.gtx_dread = CSR()
+        self.gtx_din_stb = CSR()
+        self.gtx_din = CSRStorage(16)
+
+        self.gtx_dout = CSRStatus(16)
+        self.gtx_dready = CSR()
+
+        self.comb += gtx.dclk.eq(ClockSignal("sys"))
+        self.sync += [
+            gtx.daddr.eq(self.gtx_daddr.storage),
+            gtx.den.eq(self.gtx_dread.re | self.gtx_din_stb.re),
+            gtx.dwen.eq(self.gtx_din_stb.re),
+            gtx.din.eq(self.gtx_din.storage),
+            If(gtx.dready,
+                self.gtx_dready.w.eq(1),
+                self.gtx_dout.status.eq(gtx.dout),
+            ).Elif(self.gtx_dready.re,
+                self.gtx_dready.w.eq(0),
+            ),
+        ]
+
+
+        # DEBUG: txusrclk PLL DRP
+        
+        self.txpll_reset = CSRStorage()
+        self.pll_daddr = CSRStorage(7)
+        self.pll_dclk = CSRStorage()
+        self.pll_den = CSRStorage()
+        self.pll_din = CSRStorage(16)
+        self.pll_dwen = CSRStorage()
+
+        self.txpll_locked = CSRStatus()
+        self.pll_dout = CSRStatus(16)
+        self.pll_dready = CSRStatus()
+
+        self.comb += [
+            gtx.txpll_reset.eq(self.txpll_reset.storage),
+            gtx.pll_daddr.eq(self.pll_daddr.storage),
+            gtx.pll_dclk.eq(self.pll_dclk.storage),
+            gtx.pll_den.eq(self.pll_den.storage),
+            gtx.pll_din.eq(self.pll_din.storage),
+            gtx.pll_dwen.eq(self.pll_dwen.storage),
+
+            self.txinit_phaligndone.status.eq(gtx.tx_init.Xxphaligndone),
+            self.rxinit_phaligndone.status.eq(gtx.rx_init.Xxphaligndone),
+            self.txpll_locked.status.eq(gtx.txpll_locked),
+            self.pll_dout.status.eq(gtx.pll_dout),
+            self.pll_dready.status.eq(gtx.pll_dready),
+        ]
+
+
+        # DEBUG: Transmission Pipeline
+        # 
+        #  rtio pak  ----+
+        #   from gw      |   32                                  32
+        #               mux---/---> packet -----> trigger ack ---/---> PHY
+        #                |          wrapper       inserter
+        #  data/test ----+
+        #  pak from fw
+        #
+        
+
+        # DEBUG: TX pipeline
+        self.submodules.bootstrap_loopback = bootstrap_loopback = TX_Bootstrap()
+        self.submodules.pak_wrp = pak_wrp = Packet_Wrapper()
+        self.submodules.trig_ack = trig_ack = Trigger_ACK_Inserter()
+
+        self.ack = CSR()
+
+        self.sync += trig_ack.stb.eq(self.ack.re),
+
+        tx_pipeline = [bootstrap_loopback, pak_wrp, trig_ack, phy]
+        for s, d in zip(tx_pipeline, tx_pipeline[1:]):
+            self.comb += s.source.connect(d.sink)
+
+
+
+
+        # Receiver Pipeline WIP
+        # 
+        #        32             32+8(dchar)
+        # PHY ---/---> dchar   -----/-----> trigger ack ------>  packet  ------> CDC FIFO ------> debug buffer
+        #              decoder              checker              decoder
+        #
+        cdr = ClockDomainsRenamer("cxp_gtx_rx")
+
+        # decode all incoming data as duplicate char and inject the result into the bus for downstream modules
+        self.submodules.dchar_decoder = dchar_decoder = cdr(Duplicated_Char_Decoder())
+
+        # Priority level 1 packet - Trigger ack packet
+        self.submodules.trig_ack_checker = trig_ack_checker = cdr(Trigger_Ack_Checker())
+        
+        self.submodules.trig_ack_ps = trig_ack_ps = PulseSynchronizer("cxp_gtx_rx", "sys")
+        self.sync.cxp_gtx_rx += trig_ack_ps.i.eq(trig_ack_checker.ack)
+
+        self.trig_ack = Signal()
+        self.trig_clr = Signal()
+        # Error are latched
+        self.sync += [
+            If(trig_ack_ps.o,
+                self.trig_ack.eq(1),
+            ).Elif(self.trig_clr,
+                self.trig_ack.eq(0),
+            ),
+        ]
+
+        # Priority level 2 packet - data, test packet
+        self.submodules.bootstrap = bootstrap = cdr(RX_Bootstrap())
+
+        self.bootstrap_decoder_err = CSR()
+        self.bootstrap_test_err = CSR()
+        self.boostrap_buffer_err = CSR()
+
+        decode_err_ps = PulseSynchronizer("cxp_gtx_rx", "sys")
+        test_err_ps = PulseSynchronizer("cxp_gtx_rx", "sys")
+        buffer_err_ps = PulseSynchronizer("cxp_gtx_rx", "sys")
+        self.submodules += decode_err_ps, test_err_ps, buffer_err_ps
+        self.sync.cxp_gtx_rx += [
+            decode_err_ps.i.eq(bootstrap.decode_err),
+            test_err_ps.i.eq(bootstrap.test_err),
+            buffer_err_ps.i.eq(bootstrap.buffer_err),
+        ]
+        self.sync += [
+            If(decode_err_ps.o,
+                self.bootstrap_decoder_err.w.eq(1),
+            ).Elif(self.bootstrap_decoder_err.re,
+                self.bootstrap_decoder_err.w.eq(0),
+            ),
+            If(test_err_ps.o,
+                self.bootstrap_test_err.w.eq(1),
+            ).Elif(self.bootstrap_test_err.re,
+                self.bootstrap_test_err.w.eq(0),
+            ),
+            If(buffer_err_ps.o,
+                self.boostrap_buffer_err.w.eq(1),
+            ).Elif(self.bootstrap_test_err.re,
+                self.boostrap_buffer_err.w.eq(0),
+            ),
+        ]
+
+
+        # Cicular buffer interface
+        self.packet_type = CSRStatus(8)
+        self.pending_packet = CSR()
+        self.read_ptr = CSRStatus(log2_int(buffer_count))
+
+        self.specials += [
+            MultiReg(bootstrap.packet_type, self.packet_type.status),
+            MultiReg(self.read_ptr.status, bootstrap.read_ptr_rx, odomain="cxp_gtx_rx"),
+        ]
+        self.sync += [
+            self.pending_packet.w.eq(self.read_ptr.status != bootstrap.write_ptr_sys),
+            If(~gtx.rx_ready,
+                self.read_ptr.status.eq(0),
+            ).Elif(self.pending_packet.re & self.pending_packet.w, 
+                self.read_ptr.status.eq(self.read_ptr.status + 1),
+            )
+        ]
+        
+
+        cdc_fifo = stream.AsyncFIFO(word_layout_dchar, 512)
+        self.submodules += ClockDomainsRenamer({"write": "cxp_gtx_rx", "read": "sys"})(cdc_fifo)
+        self.submodules.debug_out = debug_out = RX_Debug_Buffer()
+
+        rx_pipeline = [phy, dchar_decoder, trig_ack_checker, bootstrap, cdc_fifo, debug_out]
+        for s, d in zip(rx_pipeline, rx_pipeline[1:]):
+            self.comb += s.source.connect(d.sink)
+        
+
+        # DEBUG: CSR
+        self.trigger_ack = CSR()
+        self.sync += [
+            self.trig_clr.eq(self.trigger_ack.re),
+            self.trigger_ack.w.eq(self.trig_ack),
+        ]
+
+        pak_start = Signal()
+        self.sync += [
+            pak_start.eq(bootstrap.sink.data == 0xFBFBFBFB),
+        ]
+
+        self.specials += [
+            # Instance("OBUF", i_I=phy.gtx.cd_cxp_gtx_rx.clk, o_O=debug_sma.p_tx),
+            # Instance("OBUF", i_I=, o_O=debug_sma.p_rx),
+            # # pmod 0-7 pin
+            # Instance("OBUF", i_I=bootstrap.test_err, o_O=pmod_pads[0]),
+            # Instance("OBUF", i_I=pak_start, o_O=pmod_pads[1]),
+            # Instance("OBUF", i_I=fifo_in.source.ack, o_O=pmod_pads[2]),
+            # Instance("OBUF", i_I=gtx.comma_checker.aligner_en, o_O=pmod_pads[3]),
+            # Instance("OBUF", i_I=gtx.comma_checker.check_reset, o_O=pmod_pads[4]),
+            # Instance("OBUF", i_I=gtx.comma_checker.has_comma, o_O=pmod_pads[5]),
+            # Instance("OBUF", i_I=gtx.comma_checker.has_error, o_O=pmod_pads[6]),
+            # Instance("OBUF", i_I=gtx.comma_checker.ready_sys, o_O=pmod_pads[7]),
+        ]
+
+        
+class UpConn_Interface(Module, AutoCSR):
+    def __init__(self, phy, debug_sma, pmod_pads):
+        # Transmission Pipeline
+        #
+        #              32                                                  32           8
+        # ctrl/test ---/---> packet -----> idle word -----> trigger ack ---/--> conv ---/---> trigger -----> PHY
+        # packet             wrapper       inserter         inserter                          inserter
+        #
+        # Equivalent transmission priority:
+        # trigger > trigger ack > idle > test/data packet
+        # To maintain the trigger performance, idle word should not be inserted into trigger or trigger ack.
+        # 
+        # In low speed CoaXpress, the higher priority packet can be inserted in two types of boundary
+        # Insertion @ char boundary: Trigger packets
+        # Insertion @ word boundary: Trigger ack & IDLE packets
+        # The 32 bit part of the pipeline handles the word boundary insertion while the 8 bit part handles the char boundary insertion
+        
+
+
+        # Packet FIFOs with transmission priority
+        # 0: Trigger packet
+        self.submodules.trig = trig = TX_Trigger()
+        
+        # # DEBUG: INPUT
+        self.trig_stb = CSR()
+        self.trig_delay = CSRStorage(8) 
+        self.linktrigger = CSRStorage()
+
+        # self.sync += [
+        #     trig.stb.eq(self.trig_stb.re),
+        #     trig.delay.eq(self.trig_delay.storage),
+        #     trig.linktrig_mode.eq(self.linktrigger.storage),
+        # ]
+
+        
+        # 1: IO acknowledgment for trigger packet
+        self.submodules.trig_ack = trig_ack = Trigger_ACK_Inserter()
+
+        # DEBUG: INPUT
+        self.ack = CSR()
+        self.sync += trig_ack.stb.eq(self.ack.re),
+
+
+        # 2: All other packets (data & test packet)
+        # Control is not timing dependent, all the data packets are handled in firmware
+        self.submodules.bootstrap = bootstrap = TX_Bootstrap()
+
+        self.submodules.pak_wrp = pak_wrp = Packet_Wrapper()
+        self.submodules.idle = idle = Idle_Word_Inserter()
+
+        # Section 9.2.5.1 (CXP-001-2021)
+        # IDLE should be transmitter every 10000 words
+        cnt = Signal(max=10000)
+
+        self.sync += [
+            idle.stb.eq(0),
+            If((~idle.sink.stb) | (cnt == 9999),
+               idle.stb.eq(1),
+               cnt.eq(cnt.reset),
+            ).Else(
+               cnt.eq(cnt + 1),
+            ),
+        ]
+        
+        self.submodules.converter = converter = stream.StrideConverter(word_layout, char_layout)
+
+        tx_pipeline = [bootstrap, pak_wrp, idle, trig_ack, converter, trig, phy]
+        for s, d in zip(tx_pipeline, tx_pipeline[1:]):
+            self.comb += s.source.connect(d.sink)

src/gateware/cxp_4r_fmc.py

@@ -0,0 +1,87 @@
+from migen.build.generic_platform import *
+
+fmc_adapter_io = [
+
+    # CoaXPress high speed link
+    ("CXP_HS", 0,
+        Subsignal("txp", Pins("HPC:DP0_C2M_P")),
+        Subsignal("txn", Pins("HPC:DP0_C2M_N")),
+        Subsignal("rxp", Pins("HPC:DP0_M2C_P")),
+        Subsignal("rxn", Pins("HPC:DP0_M2C_N")),
+    ),
+    ("CXP_HS", 1,
+        Subsignal("txp", Pins("HPC:DP1_C2M_P")),
+        Subsignal("txn", Pins("HPC:DP1_C2M_N")),
+        Subsignal("rxp", Pins("HPC:DP1_M2C_P")),
+        Subsignal("rxn", Pins("HPC:DP1_M2C_N")),
+    ),
+    ("CXP_HS", 2,
+        Subsignal("txp", Pins("HPC:DP2_C2M_P")),
+        Subsignal("txn", Pins("HPC:DP2_C2M_N")),
+        Subsignal("rxp", Pins("HPC:DP2_M2C_P")),
+        Subsignal("rxn", Pins("HPC:DP2_M2C_N")),
+    ),
+    ("CXP_HS", 3,
+        Subsignal("txp", Pins("HPC:DP3_C2M_P")),
+        Subsignal("txn", Pins("HPC:DP3_C2M_N")),
+        Subsignal("rxp", Pins("HPC:DP3_M2C_P")),
+        Subsignal("rxn", Pins("HPC:DP3_M2C_N")),
+    ),
+
+    # CoaXPress low speed link
+    ("CXP_LS", 0, Pins("HPC:LA00_CC_P"), IOStandard("LVCMOS33")),
+    ("CXP_LS", 1, Pins("HPC:LA01_CC_N"), IOStandard("LVCMOS33")),
+    ("CXP_LS", 2, Pins("HPC:LA01_CC_P"), IOStandard("LVCMOS33")),
+    ("CXP_LS", 3, Pins("HPC:LA02_N"), IOStandard("LVCMOS33")),
+
+    # CoaXPress green and red LED
+    ("CXP_LED", 0,
+        Subsignal("green", Pins("HPC:LA11_P"), IOStandard("LVCMOS33")),
+        Subsignal("red", Pins("HPC:LA11_N"), IOStandard("LVCMOS33")),
+    ),
+    ("CXP_LED", 1,
+        Subsignal("green", Pins("HPC:LA12_P"), IOStandard("LVCMOS33")),
+        Subsignal("red", Pins("HPC:LA12_N"), IOStandard("LVCMOS33")),
+    ),
+    ("CXP_LED", 2,
+        Subsignal("green", Pins("HPC:LA13_P"), IOStandard("LVCMOS33")),
+        Subsignal("red", Pins("HPC:LA13_N"), IOStandard("LVCMOS33")),
+    ),
+    ("CXP_LED", 3,
+        Subsignal("green", Pins("HPC:LA14_P"), IOStandard("LVCMOS33")),
+        Subsignal("red", Pins("HPC:LA14_N"), IOStandard("LVCMOS33")),
+    ),
+
+    # Power over CoaXPress 
+    ("PoCXP", 0,
+        Subsignal("enable", Pins("HPC:LA21_N"), IOStandard("LVCMOS33")),
+        Subsignal("alert", Pins("HPC:LA18_CC_P"), IOStandard("LVCMOS33")),
+    ),
+    ("PoCXP", 1,
+        Subsignal("enable", Pins("HPC:LA21_P"), IOStandard("LVCMOS33")),
+        Subsignal("alert", Pins("HPC:LA19_N"), IOStandard("LVCMOS33")),
+    ),
+    ("PoCXP", 2,
+        Subsignal("enable", Pins("HPC:LA22_N"), IOStandard("LVCMOS33")),
+        Subsignal("alert", Pins("HPC:LA19_P"), IOStandard("LVCMOS33")),
+    ),
+    ("PoCXP", 3,
+        Subsignal("enable", Pins("HPC:LA22_P"), IOStandard("LVCMOS33")),
+        Subsignal("alert", Pins("HPC:LA20_N"), IOStandard("LVCMOS33")),
+    ),
+
+    ("i2c_fmc", 0,
+        Subsignal("scl", Pins("HPC:IIC_SCL")),
+        Subsignal("sda", Pins("HPC:IIC_SDA")),
+        IOStandard("LVCMOS33")
+    ),
+
+    ("3V3", 0, Pins("HPC:PG_M2C")),
+    ("GND", 0, Pins("HPC:PRSNT_M2C_L HPC:CLK0_M2C_P")),
+    ("VADJ", 0, Pins("HPC:GBTCLK1_M2C_N CLK0_M2C_N")),
+
+    ("clk125_fmc", 0,
+        Subsignal("p", Pins("HPC:GBTCLK0_M2C_P")),
+        Subsignal("n", Pins("HPC:GBTCLK0_M2C_n")),
+    ),
+]

src/gateware/cxp_downconn.py

@@ -0,0 +1,742 @@
+from migen import *
+from migen.genlib.cdc import MultiReg
+from migen.genlib.resetsync import AsyncResetSynchronizer
+
+from misoc.cores.code_8b10b import Encoder, Decoder
+from misoc.interconnect.csr import *
+from misoc.interconnect import stream
+
+from artiq.gateware.drtio.transceiver.gtx_7series_init import *
+from cxp_pipeline import word_layout
+
+from functools import reduce
+from operator import add
+
+class CXP_DownConn_PHYS(Module, AutoCSR):
+    def __init__(self, refclk, pads, sys_clk_freq, debug_sma, pmod_pads):
+        self.qpll_reset = CSR()
+        self.qpll_locked = CSRStatus()
+
+        self.rx_phys = []
+        # # #
+
+        # For speed higher than 6.6Gbps, QPLL need to be used instead of CPLL
+        self.submodules.qpll = qpll = QPLL(refclk, sys_clk_freq)
+        self.sync += [
+            qpll.reset.eq(self.qpll_reset.re),
+            self.qpll_locked.status.eq(qpll.lock),
+        ]
+
+
+        for i, pad in enumerate(pads):
+            rx = Receiver(qpll, pad, sys_clk_freq, "single", "single", debug_sma, pmod_pads)
+            self.rx_phys.append(rx)
+            setattr(self.submodules, "rx"+str(i), rx)
+
+            # TODO: add extension gtx connections
+            # TODO: add connection interface
+
+        # TODO: Connect slave cxp_gtx_rx clock tgt
+        # checkout channel interfaces & drtio_gtx
+        # GTPTXPhaseAlignement for inspiration
+
+        # Connect slave i's `cxp_gtx_rx` clock to `cxp_gtx_rxi` clock
+        for rx in self.rx_phys:
+            name = "cd_cxp_gtx_rx" + str(i)
+            setattr(self.clock_domains, name, ClockDomain(name=name))
+            self.comb += [
+                getattr(self, name).clk.eq(rx.gtx.cd_cxp_gtx_rx.clk),
+                getattr(self, name).rst.eq(rx.gtx.cd_cxp_gtx_rx.rst)
+            ]
+
+
+class Receiver(Module):
+    def __init__(self, qpll, pad, sys_clk_freq, tx_mode, rx_mode, debug_sma, pmod_pads):
+        self.submodules.gtx = gtx = GTX(qpll, pad, sys_clk_freq, tx_mode="single", rx_mode="single")
+       
+        self.source = stream.Endpoint(word_layout)
+
+        data_valid = Signal()
+        self.sync.cxp_gtx_rx += [
+            data_valid.eq(gtx.comma_aligner.rxfsm.ongoing("READY")),
+
+            self.source.stb.eq(0),
+            If(data_valid & self.source.ack & ~((gtx.decoders[0].d == 0xBC) & (gtx.decoders[0].k == 1)),
+                self.source.stb.eq(1),
+                self.source.data.eq(Cat(gtx.decoders[i].d for i in range(4))),
+                self.source.k.eq(Cat(gtx.decoders[i].k for i in range(4))),
+            )
+        ]
+
+        # DEBUG: tx fifos for loopback
+        # fw -> -> cdc fifo -> buffered fifo -> gtx tx
+        
+        cdc_fifo = stream.AsyncFIFO(word_layout, 512)
+        self.submodules += ClockDomainsRenamer({"write": "sys", "read": "cxp_gtx_tx"})(cdc_fifo)
+        self.sink = cdc_fifo.sink
+
+        # fix timing violation
+        cdr = ClockDomainsRenamer("cxp_gtx_tx")
+        self.submodules.buf = tx_fifo = cdr(stream.SyncFIFO(word_layout, 2, buffered=True))
+
+        self.comb += [
+            cdc_fifo.source.connect(tx_fifo.sink),
+        ]
+    
+        idle_period = 50 # express in word
+        word_count = Signal(max=idle_period)
+
+        # JANK: fix the every 98th word got eaten
+        # cnt      97    98   99       0
+        # out fifo[97] IDLE IDLE fifo[99]
+        # ack       1     0    0       1
+        self.sync.cxp_gtx_tx += [
+            tx_fifo.source.ack.eq(0),
+
+            If(word_count == idle_period-1,
+                word_count.eq(word_count.reset),
+            ).Else(
+                If(tx_fifo.source.stb,
+                    If(word_count != idle_period-2, tx_fifo.source.ack.eq(1)),
+                    word_count.eq(word_count + 1),
+                )
+            )
+        ]
+
+        # NOTE: prevent the first word send twice due to stream stb delay 
+        self.comb += [
+            If((tx_fifo.source.stb & tx_fifo.source.ack & (word_count != idle_period-1)),
+                gtx.encoder.d[0].eq(tx_fifo.source.data[:8]),
+                gtx.encoder.d[1].eq(tx_fifo.source.data[8:16]),
+                gtx.encoder.d[2].eq(tx_fifo.source.data[16:24]),
+                gtx.encoder.d[3].eq(tx_fifo.source.data[24:]),
+                gtx.encoder.k[0].eq(tx_fifo.source.k[0]),
+                gtx.encoder.k[1].eq(tx_fifo.source.k[1]),
+                gtx.encoder.k[2].eq(tx_fifo.source.k[2]),
+                gtx.encoder.k[3].eq(tx_fifo.source.k[3]),
+            ).Else(
+                # NOTE: IDLE WORD
+                gtx.encoder.d[0].eq(0xBC),
+                gtx.encoder.k[0].eq(1),
+                gtx.encoder.d[1].eq(0x3C),
+                gtx.encoder.k[1].eq(1),
+                gtx.encoder.d[2].eq(0x3C),
+                gtx.encoder.k[2].eq(1),
+                gtx.encoder.d[3].eq(0xB5),
+                gtx.encoder.k[3].eq(0),
+            )
+        ]
+
+
+class QPLL(Module, AutoCSR):
+    def __init__(self, refclk, sys_clk_freq):
+        self.clk = Signal()
+        self.refclk = Signal()
+        self.lock = Signal()
+        self.reset = Signal()
+
+        self.daddr = CSRStorage(8)
+        self.dread = CSR()
+        self.din_stb = CSR()
+        self.din = CSRStorage(16)
+
+        self.dout = CSRStatus(16)
+        self.dready = CSR()
+
+        # # #
+
+        # VCO @ 10GHz, linerate = 1.25Gbps
+        # feedback divider = 80
+        qpll_fbdiv = 0b0100100000
+        qpll_fbdiv_ratio = 1
+        refclk_div = 1
+        self.Xxout_div = 8
+
+        # DEBUG: txuserclk
+        fbdiv_real = 80
+        self.tx_usrclk_freq = (sys_clk_freq*fbdiv_real/self.Xxout_div)/40
+        
+        dready = Signal()
+        self.specials += [
+            Instance("GTXE2_COMMON",
+                i_QPLLREFCLKSEL=0b001,
+                i_GTREFCLK0=refclk,         
+
+                i_QPLLPD=0,
+                i_QPLLRESET=self.reset,
+                i_QPLLLOCKEN=1,
+                o_QPLLLOCK=self.lock,
+                o_QPLLOUTCLK=self.clk,
+                o_QPLLOUTREFCLK=self.refclk,
+
+                # See UG476 (v1.12.1) Table 2-16
+                p_QPLL_FBDIV=qpll_fbdiv,
+                p_QPLL_FBDIV_RATIO=qpll_fbdiv_ratio,
+                p_QPLL_REFCLK_DIV=refclk_div,
+
+                # From 7 Series FPGAs Transceivers Wizard
+                p_BIAS_CFG=0x0000040000001000,
+                p_COMMON_CFG=0x00000000,
+                p_QPLL_CFG=0x0680181,
+                p_QPLL_CLKOUT_CFG=0b0000,
+                p_QPLL_COARSE_FREQ_OVRD=0b010000,
+                p_QPLL_COARSE_FREQ_OVRD_EN=0b0,
+                p_QPLL_CP=0b0000011111,
+                p_QPLL_CP_MONITOR_EN=0b0,
+                p_QPLL_DMONITOR_SEL=0b0,
+                p_QPLL_FBDIV_MONITOR_EN= 0b0,
+                p_QPLL_INIT_CFG=0x000006,
+                p_QPLL_LOCK_CFG=0x21E8,
+                p_QPLL_LPF=0b1111,
+             
+                # Reserved, values cannot be modified
+                i_BGBYPASSB=0b1,
+                i_BGMONITORENB=0b1,
+                i_BGPDB=0b1,
+                i_BGRCALOVRD=0b11111,
+                i_RCALENB=0b1,
+                i_QPLLRSVD1=0b0,
+                i_QPLLRSVD2=0b11111,
+
+                # Dynamic Reconfiguration Ports
+                i_DRPADDR=self.daddr.storage,
+                i_DRPCLK=ClockSignal("sys"),
+                i_DRPEN=(self.dread.re | self.din_stb.re),
+                i_DRPWE=self.din_stb.re,
+                i_DRPDI=self.din.storage,
+                o_DRPDO=self.dout.status,
+                o_DRPRDY=dready,
+            )
+        ]
+
+        self.sync += [
+            If(dready,
+               self.dready.w.eq(1),
+            ),
+            If(self.dready.re,
+               self.dready.w.eq(0),
+            ),
+        ]
+
+
+class RX_Resetter(Module):
+    def __init__(self, reset_period=10_000_000):
+        self.rx_ready = Signal()
+        self.rx_reset = Signal()
+
+        # # #
+
+        # periodically reset rx until rx is connected and receiving valid data
+        # as after connecting RXP/RXN, the whole RX need to be reset 
+        
+        reset_counter = Signal(reset=reset_period-1, max=reset_period)
+        self.sync += [
+            self.rx_reset.eq(0),
+            If(~self.rx_ready,
+                If(reset_counter == 0,
+                    reset_counter.eq(reset_counter.reset),
+                    self.rx_reset.eq(1),
+                ).Else(
+                    reset_counter.eq(reset_counter - 1),
+                )
+            )
+        ]
+
+# Warning: Xilinx transceivers are LSB first, and comma needs to be flipped
+# compared to the usual 8b10b binary representation.
+class Comma_Aligner(Module):
+    def __init__(self, comma, reset_period=10_000_000):
+        self.data = Signal(20)
+        self.comma_aligned = Signal()
+        self.comma_realigned = Signal()
+        self.comma_det = Signal()
+
+        self.aligner_en = Signal()
+        self.ready_sys = Signal()
+
+        # # #
+
+        # Data and comma checker
+        # From UG476 (v1.12.1) p.228
+        # The built-in RXBYTEISALIGNED can be falsely asserted at linerate higher than 5Gbps
+        # The validity of data and comma needed to be checked externally
+
+        comma_n = ~comma & 0b1111111111
+
+        # DEBUG: remove after use
+        self.has_comma = Signal()
+        self.has_error = Signal()
+
+        comma_seen = Signal()
+        error_seen = Signal()
+        one_counts = Signal(max=11)
+
+        # From CXP-001-2021 section 9.2.5.1
+        # For high speed connection an IDLE word shall be transmitted at least once every 100 words
+        counter_period = 200
+
+        counter = Signal(reset=counter_period-1, max=counter_period)
+        check_reset = Signal()
+        check = Signal()
+
+        self.sync.cxp_gtx_rx += [
+            If(check_reset,
+                counter.eq(counter.reset),   
+                check.eq(0),
+            ).Elif(counter == 0,
+                check.eq(1),
+            ).Else(
+                counter.eq(counter - 1),   
+            ),
+
+            If(check_reset,
+                comma_seen.eq(0),
+            ).Elif((self.data[:10] == comma) | (self.data[:10] == comma_n),
+                comma_seen.eq(1)
+            ),
+
+            one_counts.eq(reduce(add, [self.data[i] for i in range(10)])),
+            If(check_reset,
+                error_seen.eq(0),
+            ).Elif((one_counts != 4) & (one_counts != 5) & (one_counts != 6),
+                error_seen.eq(1),
+            ),
+
+            # DEBUG: 
+            self.has_comma.eq(0),
+            If((self.data[:10] == comma) | (self.data[:10] == comma_n),
+               self.has_comma.eq(1),
+            ),
+
+            self.has_error.eq(0),
+            If((one_counts != 4) & (one_counts != 5) & (one_counts != 6),
+                self.has_error.eq(1),
+            ),
+        ]
+
+        # DEBUG: expose signal
+        self.check_reset = Signal()
+        self.comb +=[
+            self.check_reset.eq(check_reset),
+        ]
+
+        self.submodules.rxfsm = rxfsm = ClockDomainsRenamer("cxp_gtx_rx")(FSM(reset_state="WAIT_COMMA"))
+
+        rxfsm.act("WAIT_COMMA",
+            If(self.comma_det,
+                NextState("ALIGNING"),
+            )
+        )
+
+        rxfsm.act("ALIGNING",
+            If(self.comma_aligned & (~self.comma_realigned),
+                NextState("WAIT_ALIGNED_DATA"),               
+            ).Else(
+                self.aligner_en.eq(1),
+            )
+        )
+
+        # wait for the aligned data to arrive at the FPGA RX interface 
+        # as there is a delay before the data is avaiable after RXBYTEISALIGNED is asserted
+        self.submodules.timer = timer = ClockDomainsRenamer("cxp_gtx_rx")(WaitTimer(10_000))
+
+        rxfsm.act("WAIT_ALIGNED_DATA",
+            timer.wait.eq(1),
+            If(timer.done,
+                check_reset.eq(1),
+                NextState("CHECKING"),
+            )
+        )
+
+        rxfsm.act("CHECKING",
+            If(check,
+                check_reset.eq(1),
+                If(comma_seen & (~error_seen),
+                    NextState("READY"),
+                ).Else(
+                    NextState("WAIT_COMMA")
+                )
+            )
+        )
+
+        ready = Signal()
+        self.specials += MultiReg(ready, self.ready_sys)
+        rxfsm.act("READY",
+            ready.eq(1),
+            If(check,
+                check_reset.eq(1),
+                If(~(comma_seen & (~error_seen)),
+                    NextState("WAIT_COMMA"),
+                )
+            )
+        )
+
+
+class GTX(Module):
+    # Settings:
+    # * GTX reference clock @ 125MHz
+    # * GTX data width = 20
+    # * GTX PLL frequency @ 3.125GHz
+    # * GTX line rate (TX & RX) @ 3.125Gb/s
+    # * GTX TX/RX USRCLK @ PLL/datawidth = 156MHz
+    def __init__(self, qpll, pads, sys_clk_freq, tx_mode="single", rx_mode="single"):
+        assert tx_mode in ["single", "master", "slave"]
+        assert rx_mode in ["single", "master", "slave"]
+
+        # linerate = USRCLK * datawidth
+        pll_fbout_mult = 8
+        txusr_pll_div = pll_fbout_mult*sys_clk_freq/qpll.tx_usrclk_freq
+
+        self.tx_restart = Signal()
+        self.rx_restart = Signal()
+        self.loopback_mode = Signal(3)
+
+        self.txenable = Signal()
+        self.rx_ready = Signal()
+
+        # Dynamic Reconfiguration Ports
+        self.daddr = Signal(9)
+        self.dclk = Signal()
+        self.den = Signal()
+        self.dwen = Signal()
+        self.din = Signal(16)
+        self.dout = Signal(16)
+        self.dready = Signal()
+
+        self.submodules.encoder = ClockDomainsRenamer("cxp_gtx_tx")(Encoder(4, True))
+        self.submodules.decoders = [ClockDomainsRenamer("cxp_gtx_rx")(
+            (Decoder(True))) for _ in range(4)]
+
+
+        # transceiver direct clock outputs
+        # useful to specify clock constraints in a way palatable to Vivado
+        self.txoutclk = Signal()
+        self.rxoutclk = Signal()
+
+        # # #
+
+        # TX generates cxp_tx clock, init must be in system domain
+        # FIXME: 500e6 is used to fix Xx reset by holding gtxXxreset for a couple cycle more
+        self.submodules.tx_init = tx_init = GTXInit(500e6, False, mode=tx_mode)
+        self.submodules.rx_init = rx_init = GTXInit(sys_clk_freq, True, mode=rx_mode)
+
+        # RX receives restart commands from txusrclk domain
+        # self.submodules.rx_init = rx_init = ClockDomainsRenamer("cxp_gtx_tx")(GTXInit(500e6, True, mode=rx_mode))
+
+        self.comb += [
+            tx_init.cplllock.eq(qpll.lock),
+            rx_init.cplllock.eq(qpll.lock)
+        ]
+
+        txdata = Signal(40)
+        rxdata = Signal(40)
+
+        comma_aligned = Signal()
+        comma_realigned = Signal()
+        comma_det = Signal()
+        comma_aligner_en = Signal()
+        # Note: the following parameters were set after consulting AR45360
+        self.specials += \
+            Instance("GTXE2_CHANNEL",
+                # PMA Attributes
+                p_PMA_RSV=0x001E7080,
+                p_PMA_RSV2=0x2050,              # PMA_RSV2[5] = 0: Eye scan feature disabled
+                p_PMA_RSV3=0,
+                p_PMA_RSV4=1,                   # PMA_RSV[4],RX_CM_TRIM[2:0] = 0b1010: Common mode 800mV
+                p_RX_BIAS_CFG=0b000000000100,
+                p_RX_OS_CFG=0b0000010000000,
+                p_RX_CLK25_DIV=5,
+                p_TX_CLK25_DIV=5,
+
+                # Power-Down Attributes
+                p_PD_TRANS_TIME_FROM_P2=0x3c,
+                p_PD_TRANS_TIME_NONE_P2=0x3c,
+                p_PD_TRANS_TIME_TO_P2=0x64,
+                i_CPLLPD=1,
+
+                # QPLL
+                i_QPLLCLK=qpll.clk,
+                i_QPLLREFCLK=qpll.refclk,
+                p_RXOUT_DIV=qpll.Xxout_div,
+                p_TXOUT_DIV=qpll.Xxout_div,
+                i_RXSYSCLKSEL=0b11, # use QPLL & QPLL's REFCLK
+                i_TXSYSCLKSEL=0b11, # use QPLL & CPLL's REFCLK
+
+                # TX clock
+                p_TXBUF_EN="FALSE",
+                p_TX_XCLK_SEL="TXUSR",
+                o_TXOUTCLK=self.txoutclk,
+                # i_TXSYSCLKSEL=0b00,
+                i_TXOUTCLKSEL=0b11,
+
+                # TX Startup/Reset
+                i_TXPHDLYRESET=0,
+                i_TXDLYBYPASS=0,
+                i_TXPHALIGNEN=1 if tx_mode != "single" else 0,
+                i_GTTXRESET=tx_init.gtXxreset,
+                o_TXRESETDONE=tx_init.Xxresetdone,
+                i_TXDLYSRESET=tx_init.Xxdlysreset,
+                o_TXDLYSRESETDONE=tx_init.Xxdlysresetdone,
+                i_TXPHINIT=tx_init.txphinit if tx_mode != "single" else 0,
+                o_TXPHINITDONE=tx_init.txphinitdone if tx_mode != "single" else Signal(),
+                i_TXPHALIGN=tx_init.Xxphalign if tx_mode != "single" else 0,
+                i_TXDLYEN=tx_init.Xxdlyen if tx_mode != "single" else 0,
+                o_TXPHALIGNDONE=tx_init.Xxphaligndone,
+                i_TXUSERRDY=tx_init.Xxuserrdy,
+                p_TXPMARESET_TIME=1,
+                p_TXPCSRESET_TIME=1,
+                i_TXINHIBIT=~self.txenable,
+
+                # TX data
+                p_TX_DATA_WIDTH=40,
+                p_TX_INT_DATAWIDTH=1, # 1 if a line rate is greater than 6.6 Gbps
+                i_TXCHARDISPMODE=Cat(txdata[9], txdata[19], txdata[29], txdata[39]),
+                i_TXCHARDISPVAL=Cat(txdata[8], txdata[18], txdata[28], txdata[38]),
+                i_TXDATA=Cat(txdata[:8], txdata[10:18], txdata[20:28], txdata[30:38]),
+                i_TXUSRCLK=ClockSignal("cxp_gtx_tx"),
+                i_TXUSRCLK2=ClockSignal("cxp_gtx_tx"),
+
+                # TX electrical
+                i_TXBUFDIFFCTRL=0b100,
+                i_TXDIFFCTRL=0b1000,
+
+                # RX Startup/Reset
+                i_RXPHDLYRESET=0,
+                i_RXDLYBYPASS=0,
+                i_RXPHALIGNEN=1 if rx_mode != "single" else 0,
+                i_GTRXRESET=rx_init.gtXxreset,
+                o_RXRESETDONE=rx_init.Xxresetdone,
+                i_RXDLYSRESET=rx_init.Xxdlysreset,
+                o_RXDLYSRESETDONE=rx_init.Xxdlysresetdone,
+                i_RXPHALIGN=rx_init.Xxphalign if rx_mode != "single" else 0,
+                i_RXDLYEN=rx_init.Xxdlyen if rx_mode != "single" else 0,
+                o_RXPHALIGNDONE=rx_init.Xxphaligndone,
+                i_RXUSERRDY=rx_init.Xxuserrdy,
+                p_RXPMARESET_TIME=1,
+                p_RXPCSRESET_TIME=1,
+
+                # RX AFE
+                p_RX_DFE_XYD_CFG=0,
+                p_RX_CM_SEL=0b11,               # RX_CM_SEL = 0b11: Common mode is programmable
+                p_RX_CM_TRIM=0b010,             # PMA_RSV[4],RX_CM_TRIM[2:0] = 0b1010: Common mode 800mV
+                i_RXDFEXYDEN=1,
+                i_RXDFEXYDHOLD=0,
+                i_RXDFEXYDOVRDEN=0,
+                i_RXLPMEN=1,                    # RXLPMEN = 1: LPM mode is enable for non scramble 8b10b data
+                p_RXLPM_HF_CFG=0b00000011110000,
+                p_RXLPM_LF_CFG=0b00000011110000,
+
+                p_RX_DFE_GAIN_CFG=0x0207EA,
+                p_RX_DFE_VP_CFG=0b00011111100000011,
+                p_RX_DFE_UT_CFG=0b10001000000000000,
+                p_RX_DFE_KL_CFG=0b0000011111110,
+                p_RX_DFE_KL_CFG2=0x3788140A,
+                p_RX_DFE_H2_CFG=0b000110000000,
+                p_RX_DFE_H3_CFG=0b000110000000,
+                p_RX_DFE_H4_CFG=0b00011100000,
+                p_RX_DFE_H5_CFG=0b00011100000,
+                p_RX_DFE_LPM_CFG=0x0904,        # RX_DFE_LPM_CFG = 0x0904: linerate <= 6.6Gb/s
+                                                #                = 0x0104: linerate > 6.6Gb/s
+
+                # RX clock
+                i_RXDDIEN=1,
+                # i_RXSYSCLKSEL=0b00,
+                i_RXOUTCLKSEL=0b010,
+                o_RXOUTCLK=self.rxoutclk,
+                i_RXUSRCLK=ClockSignal("cxp_gtx_rx"),
+                i_RXUSRCLK2=ClockSignal("cxp_gtx_rx"),
+
+                # RX Clock Correction Attributes
+                p_CLK_CORRECT_USE="FALSE",
+                p_CLK_COR_SEQ_1_1=0b0100000000,
+                p_CLK_COR_SEQ_2_1=0b0100000000,
+                p_CLK_COR_SEQ_1_ENABLE=0b1111,
+                p_CLK_COR_SEQ_2_ENABLE=0b1111,
+
+                # RX data
+                p_RX_DATA_WIDTH=40,
+                p_RX_INT_DATAWIDTH=1,   # 1 if a line rate is greater than 6.6 Gbps
+                o_RXDISPERR=Cat(rxdata[9], rxdata[19], rxdata[29], rxdata[39]),
+                o_RXCHARISK=Cat(rxdata[8], rxdata[18], rxdata[28], rxdata[38]),
+                o_RXDATA=Cat(rxdata[:8], rxdata[10:18], rxdata[20:28], rxdata[30:38]),
+
+                # RX Byte and Word Alignment Attributes
+                p_ALIGN_COMMA_DOUBLE="FALSE",
+                p_ALIGN_COMMA_ENABLE=0b1111111111,
+                p_ALIGN_COMMA_WORD=4, # align comma to rxdata[:10] only
+                p_ALIGN_MCOMMA_DET="TRUE",
+                p_ALIGN_MCOMMA_VALUE=0b1010000011,
+                p_ALIGN_PCOMMA_DET="TRUE",
+                p_ALIGN_PCOMMA_VALUE=0b0101111100,
+                p_SHOW_REALIGN_COMMA="FALSE",
+                p_RXSLIDE_AUTO_WAIT=7,
+                p_RXSLIDE_MODE="OFF",
+                p_RX_SIG_VALID_DLY=10,
+                i_RXPCOMMAALIGNEN=comma_aligner_en,
+                i_RXMCOMMAALIGNEN=comma_aligner_en,
+                i_RXCOMMADETEN=1,
+                i_RXSLIDE=0,
+                o_RXBYTEISALIGNED=comma_aligned,
+                o_RXBYTEREALIGN=comma_realigned,
+                o_RXCOMMADET=comma_det,
+
+                # RX 8B/10B Decoder Attributes
+                p_RX_DISPERR_SEQ_MATCH="FALSE",
+                p_DEC_MCOMMA_DETECT="TRUE",
+                p_DEC_PCOMMA_DETECT="TRUE",
+                p_DEC_VALID_COMMA_ONLY="FALSE",
+
+                # RX Buffer Attributes
+                p_RXBUF_ADDR_MODE="FAST",
+                p_RXBUF_EIDLE_HI_CNT=0b1000,
+                p_RXBUF_EIDLE_LO_CNT=0b0000,
+                p_RXBUF_EN="FALSE",
+                p_RX_BUFFER_CFG=0b000000,
+                p_RXBUF_RESET_ON_CB_CHANGE="TRUE",
+                p_RXBUF_RESET_ON_COMMAALIGN="FALSE",
+                p_RXBUF_RESET_ON_EIDLE="FALSE",     # RXBUF_RESET_ON_EIDLE = FALSE: OOB is disabled
+                p_RXBUF_RESET_ON_RATE_CHANGE="TRUE",
+                p_RXBUFRESET_TIME=0b00001,
+                p_RXBUF_THRESH_OVFLW=61,
+                p_RXBUF_THRESH_OVRD="FALSE",
+                p_RXBUF_THRESH_UNDFLW=4,
+                p_RXDLY_CFG=0x001F,
+                p_RXDLY_LCFG=0x030,
+                p_RXDLY_TAP_CFG=0x0000,
+                p_RXPH_CFG=0xC00002,
+                p_RXPHDLY_CFG=0x084020,
+                p_RXPH_MONITOR_SEL=0b00000,
+                p_RX_XCLK_SEL="RXUSR",
+                p_RX_DDI_SEL=0b000000,
+                p_RX_DEFER_RESET_BUF_EN="TRUE",
+
+                # CDR Attributes
+                p_RXCDR_CFG=0x03_0000_23FF_1008_0020,   # LPM @ 0.5G-1.5625G , 8B/10B encoded data, CDR setting < +/- 200ppm
+                                                        # (See UG476 (v1.12.1), p.206)
+                p_RXCDR_FR_RESET_ON_EIDLE=0b0,
+                p_RXCDR_HOLD_DURING_EIDLE=0b0,
+                p_RXCDR_PH_RESET_ON_EIDLE=0b0,
+                p_RXCDR_LOCK_CFG=0b010101,
+
+                # Pads
+                i_GTXRXP=pads.rxp,
+                i_GTXRXN=pads.rxn,
+                o_GTXTXP=pads.txp,
+                o_GTXTXN=pads.txn,
+
+                # Dynamic Reconfiguration Ports
+                p_IS_DRPCLK_INVERTED=0b0,
+                i_DRPADDR=self.daddr,
+                i_DRPCLK=self.dclk,
+                i_DRPEN=self.den,
+                i_DRPWE=self.dwen,
+                i_DRPDI=self.din,
+                o_DRPDO=self.dout,
+                o_DRPRDY=self.dready,
+
+                # ! loopback for debugging
+                i_LOOPBACK = self.loopback_mode,
+                p_TX_LOOPBACK_DRIVE_HIZ = "FALSE",
+                p_RXPRBS_ERR_LOOPBACK = 0b0,
+
+                # Other parameters
+                p_PCS_RSVD_ATTR=(
+                    (tx_mode != "single") << 1 |    # PCS_RSVD_ATTR[1] = 0: TX Single Lane Auto Mode
+                                                    #                  = 1: TX Manual Mode
+                    (rx_mode != "single") << 2 |    #              [2] = 0: RX Single Lane Auto Mode
+                                                    #                  = 1: RX Manual Mode
+                    0 << 8                          #              [8] = 0: OOB is disabled
+                ),
+                i_RXELECIDLEMODE=0b11,              # RXELECIDLEMODE = 0b11: OOB is disabled
+                p_RX_DFE_LPM_HOLD_DURING_EIDLE=0b0,
+                p_ES_EYE_SCAN_EN="TRUE",            # Must be TRUE for GTX
+            )
+
+
+        # TX clocking
+        # A PLL is used to generate the correct frequency for TXUSRCLK (UG476 Equation 3-1)
+        self.clock_domains.cd_cxp_gtx_tx = ClockDomain()
+        txpll_fb_clk = Signal()
+        txoutclk_buf = Signal()
+        txpll_clkout = Signal()
+
+        self.txpll_reset = Signal()
+        self.pll_daddr = Signal(7)
+        self.pll_dclk = Signal()
+        self.pll_den = Signal()
+        self.pll_din = Signal(16)
+        self.pll_dwen = Signal()
+
+        self.txpll_locked = Signal()
+        self.pll_dout = Signal(16)
+        self.pll_dready = Signal()
+        self.specials += [
+            Instance("PLLE2_ADV",
+                p_BANDWIDTH="HIGH",
+                o_LOCKED=self.txpll_locked,
+                i_RST=self.txpll_reset,
+                
+                p_CLKIN1_PERIOD=1e9/sys_clk_freq, # ns
+                i_CLKIN1=txoutclk_buf,
+
+                # VCO @ 1.25GHz 
+                p_CLKFBOUT_MULT=pll_fbout_mult, p_DIVCLK_DIVIDE=1,
+                i_CLKFBIN=txpll_fb_clk, o_CLKFBOUT=txpll_fb_clk, 
+
+                # frequency = linerate/40
+                p_CLKOUT0_DIVIDE=txusr_pll_div, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=txpll_clkout,
+
+                # Dynamic Reconfiguration Ports
+                i_DADDR = self.pll_daddr,
+                i_DCLK = self.pll_dclk,
+                i_DEN = self.pll_den,
+                i_DI = self.pll_din,
+                i_DWE = self.pll_dwen,
+                o_DO = self.pll_dout,
+                o_DRDY = self.pll_dready,
+            ),
+            Instance("BUFG", i_I=self.txoutclk, o_O=txoutclk_buf),
+            Instance("BUFG", i_I=txpll_clkout, o_O=self.cd_cxp_gtx_tx.clk),
+            AsyncResetSynchronizer(self.cd_cxp_gtx_tx, ~self.txpll_locked & ~tx_init.done)
+        ]
+        self.comb += tx_init.restart.eq(self.tx_restart)
+
+        # RX clocking
+        # the CDR matches the required frequency for RXUSRCLK, no need for PLL 
+
+        # Slave Rx will use cxp_gtx_rx instead
+        if rx_mode == "single" or rx_mode == "master":
+            self.clock_domains.cd_cxp_gtx_rx = ClockDomain()
+            self.specials += [
+                Instance("BUFG", i_I=self.rxoutclk, o_O=self.cd_cxp_gtx_rx.clk),
+                AsyncResetSynchronizer(self.cd_cxp_gtx_rx, ~rx_init.done)
+            ]
+            self.submodules.rx_resetter = rx_resetter = RX_Resetter()
+            self.comb += [
+                rx_resetter.rx_ready.eq(self.rx_ready),
+                rx_init.restart.eq(self.rx_restart | rx_resetter.rx_reset),
+            ]
+        else:
+            self.comb += rx_init.restart.eq(self.rx_restart),
+
+
+
+        # 8b10b Encoder/Decoder
+
+        self.comb += [
+            txdata.eq(Cat(self.encoder.output[0], self.encoder.output[1], self.encoder.output[2], self.encoder.output[3])),
+            self.decoders[0].input.eq(rxdata[:10]),
+            self.decoders[1].input.eq(rxdata[10:20]),
+            self.decoders[2].input.eq(rxdata[20:30]),
+            self.decoders[3].input.eq(rxdata[30:]),
+        ]
+
+        self.submodules.comma_aligner = comma_aligner = Comma_Aligner(0b0101111100)
+        self.comb += [
+            comma_aligner.data.eq(rxdata),
+            comma_aligner.comma_aligned.eq(comma_aligned),
+            comma_aligner.comma_realigned.eq(comma_realigned),
+            comma_aligner.comma_det.eq(comma_det),
+            comma_aligner_en.eq(comma_aligner.aligner_en),
+            self.rx_ready.eq(comma_aligner.ready_sys),
+        ]

src/gateware/cxp_frame_pipeline.py

@@ -0,0 +1,409 @@
+from migen import *
+from misoc.interconnect.csr import *
+from misoc.interconnect import stream
+from misoc.cores.liteeth_mini.mac.crc import LiteEthMACCRCEngine
+
+from cxp_pipeline import *
+# from src.gateware.cxp_pipeline import * # for sim only
+
+from types import SimpleNamespace
+
+class EOP_Marker(Module):
+    def __init__(self):
+        self.sink = stream.Endpoint(word_layout_dchar)
+        self.source = stream.Endpoint(word_layout_dchar)
+
+        # # #
+
+        last_stb = Signal()
+        self.sync += [
+            If((~self.source.stb | self.source.ack),
+                self.source.stb.eq(self.sink.stb),
+                self.source.payload.eq(self.sink.payload),
+            ),
+            last_stb.eq(self.sink.stb),
+        ]
+        self.comb += [
+            self.sink.ack.eq(~self.source.stb | self.source.ack),
+            self.source.eop.eq(~self.sink.stb & last_stb),
+        ]
+
+class Streams_Crossbar(Module):
+    def __init__(self, downconn_sources, stream_sinks):
+        n_downconn = len(downconn_sources)
+        self.active_conn= C(n_downconn) 
+        # TODO: change self.active_conns to signal and link it to rx_ready of GTX lanes
+
+        # # #
+
+        self.submodules.mux = mux = stream.Multiplexer(word_layout_dchar, n_downconn)
+
+        for i, downconn in enumerate(downconn_sources):
+            self.comb += downconn.source.connect(getattr(mux, "sink"+str(i)))
+
+        self.submodules.fsm = fsm = FSM(reset_state="WAIT_HEADER")
+
+        self.stream_id = Signal(char_width)
+        case = dict((i, mux.source.connect(b.sink)) for i, b in enumerate(stream_sinks))
+        fsm.act(
+            "WAIT_HEADER",
+            NextValue(self.stream_id, mux.source.dchar),
+            If(mux.source.stb,
+                NextState("COPY"),
+            ),
+        )
+
+        fsm.act(
+            "COPY",
+            Case(self.stream_id, case),
+            If(mux.source.eop,
+                NextState("SWITCH_CONN"),
+            ),
+        )
+
+        # Section 9.5.5 (CXP-001-2021)
+        # When Multiple connections are active, stream packets are transmitted in
+        # ascending order of Connection ID. And one connection shall be transmitting data at a time.
+        read_mask = Signal(max=n_downconn)
+        self.comb += mux.sel.eq(read_mask)
+        fsm.act(
+            "SWITCH_CONN",
+            # assuming downconn_sources have ascending Connection ID 
+            If(read_mask == self.active_conn - 1,
+                NextValue(read_mask, read_mask.reset),
+            ).Else(
+                NextValue(read_mask, read_mask + 1),
+            ),
+            NextState("WAIT_HEADER"),
+        )
+
+
+def reverse_bytes(s):
+    assert len(s) % 8 == 0
+    char = [s[i*8:(i+1)*8] for i in range(len(s)//8)]
+    return Cat(char[::-1])
+
+@ResetInserter()
+@CEInserter()
+class CXPCRC32(Module):
+    # Section 9.2.2.2 (CXP-001-2021)
+    width = 32
+    polynom = 0x04C11DB7
+    seed = 2**width - 1
+    check = 0x00000000
+
+    def __init__(self, data_width):
+        self.data = Signal(data_width)
+        self.value = Signal(self.width)
+        self.error = Signal()
+
+        # # #
+
+        self.submodules.engine = LiteEthMACCRCEngine(
+            data_width, self.width, self.polynom
+        )
+        reg = Signal(self.width, reset=self.seed)
+        self.sync += reg.eq(self.engine.next)
+        self.comb += [
+            # the CRC Engine use Big Endian, need to reverse the bytes
+            self.engine.data.eq(reverse_bytes(self.data)),
+            self.engine.last.eq(reg),
+            self.value.eq(reverse_bytes(reg[::-1])),
+            self.error.eq(reg != self.check),
+        ]
+
+# For verifying crc in stream data packet
+class Double_Stream_Buffer(Module):
+    def __init__(self, size):
+        self.sink = stream.Endpoint(word_layout_dchar)
+
+        self.submodules.crc = crc = CXPCRC32(word_dw)
+        self.comb += crc.data.eq(self.sink.data)
+
+        self.submodules.fsm = fsm = FSM(reset_state="RESET")
+
+        write_mask = Signal()
+        self.submodules.line_buffer0 = line_buffer0 = ResetInserter()(stream.SyncFIFO(word_layout_dchar, 2**bits_for(size//word_dw)))
+        self.submodules.line_buffer1 = line_buffer1 = ResetInserter()(stream.SyncFIFO(word_layout_dchar, 2**bits_for(size//word_dw)))
+        fsm.act("RESET",
+            Case(write_mask,
+                {
+                     0: line_buffer0.reset.eq(1),
+                     1: line_buffer1.reset.eq(1),
+                }
+            ),
+            crc.reset.eq(1),
+            NextState("CHECKING"),
+        )
+
+        fsm.act("CHECKING",
+            self.sink.ack.eq(1),
+            If(self.sink.stb,
+                crc.ce.eq(1),
+                If(self.sink.eop,
+                    # discard the crc at the end
+                    NextState("SWITCH_BUFFER")
+                ).Else(
+                    If(write_mask == 0,
+                        self.sink.connect(line_buffer0.sink),
+                    ).Else(
+                        self.sink.connect(line_buffer1.sink),
+                    ),
+                )
+            )
+        )
+
+        # only valid data will be passed to downstream
+        fsm.act("SWITCH_BUFFER",
+            If(~crc.error,
+                NextValue(write_mask, ~write_mask),
+            ),
+            NextState("RESET"),
+        )
+
+        self.submodules.mux = mux = stream.Multiplexer(word_layout_dchar, 2)
+        self.comb += [
+            line_buffer0.source.connect(mux.sink0),
+            line_buffer1.source.connect(mux.sink1),
+            mux.sel.eq(~write_mask),
+        ]
+        self.source = mux.source
+
+        # DEBUG:
+        self.write = Signal()
+        self.error = Signal()
+        self.comb += [
+            self.write.eq(write_mask),
+            self.error.eq(crc.error),
+        ]
+
+        # # to add eop in the same cycle
+        # # the tricks relies on the fact source lags sink one cycle
+        # # but fsm .connect by default use combinational logic which the same cycle rising/falling edge check immpossible
+        # fsm.act("CHECKING",
+        #     NextValue(self.source.payload.raw_bits(), 0),
+        #     NextValue(self.source.stb, 0),
+        #     If(self.sink.stb,
+        #         crc.ce.eq(1),
+        #         If(self.sink.eop,
+        #             NextState("RESET")
+        #         ).Else(
+        #             NextValue(self.source.payload.raw_bits(), self.sink.payload.raw_bits()),
+        #             NextValue(self.source.stb, 1),
+        #         )
+        #     )
+        # )
+        
+        # last_eop = Signal()
+        # self.comb += self.source.eop.eq(~last_eop & self.sink.eop)
+
+
+class Stream_Parser(Module):
+    def __init__(self):
+        self.sink = stream.Endpoint(word_layout_dchar)
+        self.source = stream.Endpoint(word_layout_dchar)
+
+        # # #
+
+        self.stream_id = Signal(char_width)
+        self.pak_tag = Signal(char_width)
+        self.stream_pak_size = Signal(char_width * 2)
+
+        self.submodules.fsm = fsm = FSM(reset_state="WAIT_HEADER")
+
+        fsm.act(
+            "WAIT_HEADER",
+            NextValue(self.stream_id, self.stream_id.reset),
+            NextValue(self.pak_tag, self.pak_tag.reset),
+            NextValue(self.stream_pak_size, self.stream_pak_size.reset),
+            self.sink.ack.eq(1),
+            If(
+                self.sink.stb,
+                NextValue(self.stream_id, self.sink.dchar),
+                NextState("GET_PAK_TAG"),
+            ),
+        )
+
+        fsm.act(
+            "GET_PAK_TAG",
+            self.sink.ack.eq(1),
+            If(
+                self.sink.stb,
+                NextValue(self.pak_tag, self.sink.dchar),
+                NextState("GET_PAK_SIZE_0"),
+            ),
+        )
+
+        fsm.act(
+            "GET_PAK_SIZE_0",
+            self.sink.ack.eq(1),
+            If(
+                self.sink.stb,
+                NextValue(self.stream_pak_size[8:], self.sink.dchar),
+                NextState("GET_PAK_SIZE_1"),
+            ),
+        )
+
+        fsm.act(
+            "GET_PAK_SIZE_1",
+            self.sink.ack.eq(1),
+            If(
+                self.sink.stb,
+                NextValue(self.stream_pak_size[:8], self.sink.dchar),
+                NextState("STORE_BUFFER"),
+            ),
+        )
+
+        fsm.act(
+            "STORE_BUFFER",
+            self.sink.connect(self.source),
+            # both serve the same function but using the pak size I can remove eop injecter and save 1 cycle
+            If(self.sink.stb,
+                NextValue(self.stream_pak_size, self.stream_pak_size - 1),
+                If(self.stream_pak_size == 1,
+                    NextState("WAIT_HEADER"),
+                )
+            ),
+        )
+
+class Frame_Extractor(Module):
+    def __init__(self, pixel_format="mono16"):
+        assert pixel_format in ["mono16"]
+        pixel_format = {
+            "mono16": C(0x0105, 2*char_width)
+        }
+        self.format_error = Signal()
+        self.decode_err = Signal()
+
+        self.new_frame = Signal()
+        self.new_line = Signal()
+
+        n_metadata_chars = 23
+        img_header_layout = [
+            ("stream_id", char_width),
+            ("source_tag", 2*char_width), 
+            ("x_size", 3*char_width), 
+            ("x_offset", 3*char_width), 
+            ("y_size", 3*char_width), 
+            ("y_offset", 3*char_width), 
+            ("l_size", 3*char_width), # number of data words per image line 
+            ("pixel_format", 2*char_width), 
+            ("tap_geo", 2*char_width), 
+            ("flag", char_width), 
+        ]
+        assert layout_len(img_header_layout) == n_metadata_chars*char_width  
+
+
+        # # #
+
+        # TODO: decode Image header, line break
+        self.sink = stream.Endpoint(word_layout_dchar)
+        self.source = stream.Endpoint(word_layout_dchar)
+
+        self.submodules.fsm = fsm = FSM(reset_state="IDLE")
+
+        # DEBUG: remove this
+        self.fsm_state = Signal()
+        self.comb += self.fsm_state.eq(fsm.ongoing("IDLE"))
+
+        fsm.act("IDLE",
+            self.sink.ack.eq(1),
+            If((self.sink.stb & (self.sink.dchar == KCode["stream_marker"]) & (self.sink.dchar_k == 1)),
+                NextState("DECODE"),
+            )
+        )
+
+        fsm.act("COPY",
+            # until for new line or new frame
+            If((self.sink.stb & (self.sink.dchar == KCode["stream_marker"]) & (self.sink.dchar_k == 1)),
+                self.sink.ack.eq(1),
+                NextState("DECODE"),
+            ).Else(
+                self.sink.connect(self.source),
+            )
+        )
+
+        type = {
+            "new_frame": 0x01,
+            "line_break": 0x02,
+        }
+
+        cnt = Signal(max=n_metadata_chars)
+        fsm.act("DECODE",
+            self.sink.ack.eq(1),
+            If(self.sink.stb,
+                Case(self.sink.dchar, {
+                    type["new_frame"]: [
+                        self.new_frame.eq(1),
+                        NextValue(cnt, cnt.reset),
+                        NextState("GET_FRAME_DATA"),
+                    ],
+                    type["line_break"]: [
+                        self.new_line.eq(1),
+                        NextState("COPY"),
+                    ],
+                    "default": [
+                         self.decode_err.eq(1),
+                         # discard all data until valid frame
+                         NextState("IDLE"),
+                    ],
+                }),
+            )
+        )
+
+        packet_buffer = Signal(layout_len(img_header_layout))
+        case = dict(
+            (i, NextValue(packet_buffer[8*i:8*(i+1)], self.sink.dchar))
+            for i in range(n_metadata_chars)
+        )
+        fsm.act("GET_FRAME_DATA",
+            self.sink.ack.eq(1),
+            If(self.sink.stb,
+                Case(cnt, case),
+                If(cnt == n_metadata_chars - 1,
+                    NextState("COPY"),
+                    NextValue(cnt, cnt.reset),
+                ).Else(
+                    NextValue(cnt, cnt + 1),
+                ),
+            ),
+        )
+
+        # dissect packet 
+        self.metadata = SimpleNamespace()
+        idx = 0
+        for name, size in img_header_layout:
+            # CXP use MSB even when sending duplicate chars
+            setattr(self.metadata, name, reverse_bytes(packet_buffer[idx:idx+size]))
+            idx += size
+
+
+class Pixel_Decoder(Module):
+    def __init__(self, pixel_format="mono16"):
+        assert pixel_format == "mono16"
+
+        self.sink = stream.Endpoint(word_layout_dchar)
+        self.source = stream.Endpoint(word_layout_dchar)
+
+        # # #
+
+        # TODO: support mono16 for now?
+        # TODO: or support it in driver instead?
+
+class Stream_Pipeline(Module):
+    # optimal stream packet size is 2 kBtyes - Section 9.5.2 (CXP-001-2021)
+    def __init__(self, size=16000):
+
+        # double buffer need eop to function correctly
+        self.submodules.double_buffer = double_buffer = Double_Stream_Buffer(size)
+        self.submodules.parser = parser = Stream_Parser()
+        self.submodules.frame_extractor = frame_extractor = Frame_Extractor()
+
+        pipeline = [double_buffer, parser, frame_extractor]
+        for s, d in zip(pipeline, pipeline[1:]):
+            self.comb += s.source.connect(d.sink)
+        self.sink = pipeline[0].sink
+        self.source = pipeline[-1].source
+        
+        # no backpressure for sim purposes
+        self.sync += self.source.ack.eq(1)

src/gateware/cxp_pipeline.py

@@ -0,0 +1,527 @@
+from migen import *
+from migen.genlib.cdc import MultiReg 
+from misoc.interconnect.csr import *
+from misoc.interconnect import stream
+
+from functools import reduce
+from itertools import combinations
+from operator import or_, and_
+
+char_width = 8
+char_layout = [("data", char_width), ("k", char_width//8)]
+
+word_dw = 32
+word_layout = [("data", word_dw), ("k", word_dw//8)]
+
+word_layout_dchar = [
+    ("data", word_dw),
+    ("k", word_dw//8), 
+    ("dchar", char_width), 
+    ("dchar_k", char_width//8)
+]
+
+buffer_count = 4
+buffer_depth = 512
+
+def K(x, y):
+    return ((y << 5) | x)
+
+KCode = {
+    "pak_start" : C(K(27, 7), char_width),
+    "io_ack" : C(K(28, 6), char_width), 
+    "trig_indic_28_2" : C(K(28, 2), char_width),
+    "stream_marker" : C(K(28, 3), char_width),
+    "trig_indic_28_4" : C(K(28, 4), char_width),
+    "pak_end" : C(K(29, 7), char_width),
+    "idle_comma" : C(K(28, 5), char_width),
+    "idle_alignment" : C(K(28, 1), char_width),
+}
+
+class Packet_Wrapper(Module):
+    def __init__(self):
+        self.sink = stream.Endpoint(word_layout)
+        self.source = stream.Endpoint(word_layout)
+
+        # # #
+
+        self.submodules.fsm = fsm = FSM(reset_state="IDLE")
+        
+        fsm.act("IDLE",
+            self.sink.ack.eq(1),
+            If(self.sink.stb,
+                self.sink.ack.eq(0),
+                NextState("INSERT_HEADER"),
+            )
+        )
+
+        fsm.act("INSERT_HEADER",
+            self.sink.ack.eq(0),
+            self.source.stb.eq(1),
+            self.source.data.eq(Replicate(KCode["pak_start"], 4)),
+            self.source.k.eq(Replicate(1, 4)),
+            If(self.source.ack, NextState("COPY")),
+        )
+
+        fsm.act("COPY",
+            self.sink.connect(self.source),
+            self.source.eop.eq(0),
+            If(self.sink.stb & self.sink.eop & self.source.ack,
+                NextState("INSERT_FOOTER"),
+            ),
+        )
+
+        fsm.act("INSERT_FOOTER",
+            self.sink.ack.eq(0),
+            self.source.stb.eq(1),
+            self.source.data.eq(Replicate(KCode["pak_end"], 4)),
+            self.source.k.eq(Replicate(1, 4)),
+            self.source.eop.eq(1),
+            If(self.source.ack, NextState("IDLE")),
+        )
+        
+class TX_Trigger(Module):
+    def __init__(self):
+        self.stb = Signal()
+        self.delay = Signal(char_width) 
+        self.linktrig_mode = Signal()
+
+        # # #
+
+        self.sink = stream.Endpoint(char_layout)
+        self.source = stream.Endpoint(char_layout)
+
+        # Table 15 & 16 (CXP-001-2021)
+        # Send [K28.2, K28.4, K28.4] or [K28.4, K28.2, K28.2] and 3x delay as trigger packet 
+
+        trig_packet = [Signal(char_width), Signal(char_width), Signal(char_width), self.delay, self.delay, self.delay]
+        trig_packet_k = [1, 1, 1, 0, 0, 0]
+        self.comb += [
+            If(self.linktrig_mode,
+                trig_packet[0].eq(KCode["trig_indic_28_4"]),
+                trig_packet[1].eq(KCode["trig_indic_28_2"]),
+                trig_packet[2].eq(KCode["trig_indic_28_2"]),
+            ).Else(
+                trig_packet[0].eq(KCode["trig_indic_28_2"]),
+                trig_packet[1].eq(KCode["trig_indic_28_4"]),
+                trig_packet[2].eq(KCode["trig_indic_28_4"]),
+            ),
+        ]
+        
+        self.submodules.fsm = fsm = FSM(reset_state="COPY")
+        
+        cnt = Signal(max=6)
+        fsm.act("COPY",
+            NextValue(cnt, cnt.reset),
+            self.sink.connect(self.source),
+            If(self.stb, NextState("WRITE_TRIG"))
+        )
+
+        fsm.act("WRITE_TRIG",
+            self.sink.ack.eq(0),
+            self.source.stb.eq(1),
+            self.source.data.eq(Array(trig_packet)[cnt]),
+            self.source.k.eq(Array(trig_packet_k)[cnt]),
+            If(self.source.ack,
+                If(cnt == 5,
+                    NextState("COPY"),
+                ).Else(
+                    NextValue(cnt, cnt + 1),
+                )
+            )
+        )
+
+class Idle_Word_Inserter(Module):
+    def __init__(self):
+        self.stb = Signal()
+
+        # # #
+
+        # Section 9.2.5 (CXP-001-2021)
+        # Send K28.5, K28.1, K28.1, D21.5  as idle word
+        self.submodules.fsm = fsm = FSM(reset_state="COPY")
+        
+        self.sink = stream.Endpoint(word_layout)
+        self.source = stream.Endpoint(word_layout)
+        fsm.act("COPY",
+            self.sink.connect(self.source),
+            If(self.stb, NextState("WRITE_IDLE"))
+        )
+
+        fsm.act("WRITE_IDLE",
+            self.sink.ack.eq(0),
+            self.source.stb.eq(1),
+            self.source.data.eq(Cat(KCode["idle_comma"], KCode["idle_alignment"], KCode["idle_alignment"], C(0xB5, char_width))),
+            self.source.k.eq(Cat(1, 1, 1, 0)),
+            If(self.source.ack, NextState("COPY")),
+        )
+
+
+class Trigger_ACK_Inserter(Module):
+    def __init__(self):
+        self.stb = Signal()
+
+        # # #
+
+        # Section 9.3.2 (CXP-001-2021)
+        # Send 4x K28.6 and 4x 0x01 as trigger packet ack
+        self.submodules.fsm = fsm = FSM(reset_state="COPY")
+        
+        self.sink = stream.Endpoint(word_layout)
+        self.source = stream.Endpoint(word_layout)
+        fsm.act("COPY",
+            self.sink.connect(self.source),
+            If(self.stb, NextState("WRITE_ACK0"))
+        )
+
+        fsm.act("WRITE_ACK0",
+            self.sink.ack.eq(0),
+            self.source.stb.eq(1),
+            self.source.data.eq(Replicate(KCode["io_ack"], 4)),
+            self.source.k.eq(Replicate(1, 4)),
+            If(self.source.ack, NextState("WRITE_ACK1")),
+        )
+
+        fsm.act("WRITE_ACK1",
+            self.sink.ack.eq(0),
+            self.source.stb.eq(1),
+            self.source.data.eq(Replicate(C(0x01, char_width), 4)),
+            self.source.k.eq(Replicate(0, 4)),
+            If(self.source.ack, NextState("COPY")),
+        )
+
+
+@FullMemoryWE()
+class TX_Bootstrap(Module, AutoCSR):
+    def __init__(self):
+        self.tx_word_len = CSRStorage(log2_int(buffer_depth))
+        self.tx = CSR()
+        self.tx_testseq = CSR()
+
+        self.tx_busy = CSRStatus()
+
+        # # #
+        
+        self.specials.mem = mem = Memory(word_dw, buffer_depth)
+        self.specials.mem_port = mem_port = mem.get_port()
+        self.source = stream.Endpoint(word_layout)
+
+        # increment addr in the same cycle the moment addr_inc is high
+        # as memory takes one cycle to shift to the correct addr
+        addr_next = Signal(log2_int(buffer_depth))
+        addr = Signal.like(addr_next)
+        addr_rst = Signal()
+        addr_inc = Signal()
+        self.sync += addr.eq(addr_next),
+
+        self.comb += [
+            addr_next.eq(addr),
+            If(addr_rst,
+                addr_next.eq(addr_next.reset),
+            ).Elif(addr_inc,
+                addr_next.eq(addr + 1),
+            ),
+            mem_port.adr.eq(addr_next),
+            self.source.data.eq(mem_port.dat_r)
+        ]
+
+        self.submodules.fsm = fsm = FSM(reset_state="IDLE")
+        self.sync += self.tx_busy.status.eq(~fsm.ongoing("IDLE"))
+
+        cnt = Signal(max=0xFFF)
+        fsm.act("IDLE",
+            addr_rst.eq(1),
+            If(self.tx.re, NextState("TRANSMIT")),
+            If(self.tx_testseq.re, 
+                NextValue(cnt, cnt.reset),
+                NextState("WRITE_TEST_PACKET_TYPE"),
+            )
+        )
+
+        fsm.act("TRANSMIT",
+            self.source.stb.eq(1),
+            If(self.source.ack,
+                addr_inc.eq(1),
+            ),
+            If(addr_next == self.tx_word_len.storage,
+                self.source.eop.eq(1),
+                NextState("IDLE")
+            )
+        )
+
+        fsm.act("WRITE_TEST_PACKET_TYPE",
+            self.source.stb.eq(1),
+            self.source.data.eq(Replicate(C(0x04, char_width), 4)),
+            self.source.k.eq(Replicate(0, 4)),
+            If(self.source.ack,NextState("WRITE_TEST_COUNTER"))
+        )
+
+        fsm.act("WRITE_TEST_COUNTER",
+            self.source.stb.eq(1),
+            self.source.data.eq(Cat(cnt[:8], cnt[:8]+1, cnt[:8]+2, cnt[:8]+3)),
+            self.source.k.eq(Cat(0, 0, 0, 0)),
+            If(self.source.ack,
+                If(cnt == 0xFFF-3,
+                    self.source.eop.eq(1),
+                    NextState("IDLE")
+                ).Else(
+                    NextValue(cnt, cnt + 4),
+                )
+               
+            )
+        )
+
+class RX_Debug_Buffer(Module,AutoCSR):
+    def __init__(self):
+        self.submodules.buf_out = buf_out = stream.SyncFIFO(word_layout_dchar, 128)
+        self.sink = buf_out.sink
+
+        self.inc = CSR()
+        self.dout_pak = CSRStatus(word_dw)
+        self.kout_pak = CSRStatus(word_dw//8)
+        self.dout_valid = CSRStatus()
+
+        self.sync += [
+            # output
+            buf_out.source.ack.eq(self.inc.re),
+            self.dout_pak.status.eq(buf_out.source.data),
+            self.kout_pak.status.eq(buf_out.source.k),
+            self.dout_valid.status.eq(buf_out.source.stb),
+        ]
+
+class Duplicated_Char_Decoder(Module):
+    def __init__(self):
+        self.sink = stream.Endpoint(word_layout)
+        self.source = stream.Endpoint(word_layout_dchar)
+
+        # # #
+
+
+        # For duplicated characters, an error correction method (e.g. majority voting) is required to meet the CXP spec:
+        # RX decoder should immune to single bit errors when handling duplicated characters - Section 9.2.2.1 (CXP-001-2021)
+        # 
+        #
+        #                                 32
+        #             +--->  buffer  -----/-----+
+        #         32  |                         |            32+8(dchar)
+        # sink ---/---+                         ---> source -----/-----> downstream
+        #             |                8(dchar) |                        decoders
+        #             +---> majority -----/-----+
+        #                   voting
+        # 
+        #
+        # Due to the tight setup/hold time requiremnt for 12.5Gbps CXP, the voting logic cannot be implemented as combinational logic
+        # Hence, a pipeline approach is needed to avoid any s/h violation, where the majority voting result are pre-calculate and injected into the bus immediate after the PHY.
+        # And any downstream modules can access the voting result without implementing the voting logic inside the decoder
+
+        # cycle 1 - buffer data & calculate intermediate result  
+        buffer = stream.Endpoint(word_layout)
+        self.sync += [
+            If((~buffer.stb | buffer.ack),
+                buffer.stb.eq(self.sink.stb),
+                buffer.payload.eq(self.sink.payload),
+            )
+        ]
+        self.comb += self.sink.ack.eq(~buffer.stb | buffer.ack)
+        
+        # calculate ABC, ABD, ACD, BCD  
+        char = [[self.sink.data[i*8:(i+1)*8], self.sink.k[i]] for i in range(4)]
+        voters = [Record([("data", 8), ("k", 1)]) for _ in range(4)]
+
+        for i, comb in enumerate(combinations(char, 3)):
+            self.sync += [
+                If((~buffer.stb | buffer.ack),
+                    voters[i].data.eq(reduce(and_, [code[0] for code in comb])),
+                    voters[i].k.eq(reduce(and_, [code[1] for code in comb])),
+                )
+            ]
+
+
+        # cycle 2 - inject the voting result 
+        self.sync += [
+            If((~self.source.stb | self.source.ack),
+                self.source.stb.eq(buffer.stb),
+                self.source.data.eq(buffer.data),
+                self.source.k.eq(buffer.k),
+                self.source.dchar.eq(Replicate(reduce(or_, [v.data for v in voters]), 4)),
+                self.source.dchar_k.eq(Replicate(reduce(or_, [v.k for v in voters]), 4)),
+            )
+        ]
+        self.comb += buffer.ack.eq(~self.source.stb | self.source.ack)
+
+
+@FullMemoryWE()
+class RX_Bootstrap(Module):
+    def __init__(self):
+        self.packet_type = Signal(8)
+
+        self.decode_err = Signal()
+        self.test_err = Signal()
+        self.buffer_err = Signal()
+        # # #
+
+        # TODO: heartbeat
+        type = {
+            "data_stream": 0x01,
+            "control_ack_no_tag": 0x03,
+            "test_packet": 0x04,
+            "control_ack_with_tag": 0x06,
+            "event": 0x07,
+            "heartbeat": 0x09,
+        }
+
+        self.sink = stream.Endpoint(word_layout_dchar)
+        self.source = stream.Endpoint(word_layout_dchar)
+
+        self.submodules.fsm = fsm = FSM(reset_state="IDLE")
+
+        fsm.act("IDLE",
+            self.sink.ack.eq(1),
+            If((self.sink.stb & (self.sink.dchar == KCode["pak_start"]) & (self.sink.dchar_k == 1)),
+                NextState("DECODE"),
+            )
+        )
+
+        cnt = Signal(max=0x100)
+        addr_nbits = log2_int(buffer_depth)
+        addr = Signal(addr_nbits)
+        fsm.act("DECODE",
+            self.sink.ack.eq(1),
+            If(self.sink.stb,
+                Case(self.sink.dchar, {
+                    type["data_stream"]: NextState("STREAMING"),
+                    type["test_packet"]: [
+                        NextValue(cnt, cnt.reset),
+                        NextState("VERIFY_TEST_PATTERN"),
+                    ],
+                    type["control_ack_no_tag"]:[
+                        NextValue(self.packet_type, self.sink.dchar),
+                        NextValue(addr, addr.reset),
+                        NextState("LOAD_BUFFER"),
+                    ],
+                    type["control_ack_with_tag"]:[
+                        NextValue(self.packet_type, self.sink.dchar),
+                        NextValue(addr, addr.reset),
+                        NextState("LOAD_BUFFER"),
+                    ],
+                    type["event"]: [
+                        NextValue(self.packet_type, self.sink.dchar),
+                        NextValue(addr, addr.reset),
+                        NextState("LOAD_BUFFER"),
+                    ],
+                    "default": [
+                         self.decode_err.eq(1),
+                         # wait till next valid packet
+                         NextState("IDLE"),
+                    ],
+                }),
+            )
+        )
+        # For stream data packet
+        fsm.act("STREAMING",
+            If((self.sink.stb & (self.sink.dchar == KCode["pak_end"]) & (self.sink.dchar_k == 1)),
+                # discard K29,7
+                self.sink.ack.eq(1),
+                NextState("IDLE")
+            ).Else(
+                self.sink.connect(self.source),
+            )      
+        )
+
+        # Section 9.9.1 (CXP-001-2021)
+        # the received test data packet (0x00, 0x01 ... 0xFF) 
+        # need to be compared against the local test sequence generator
+        fsm.act("VERIFY_TEST_PATTERN",
+            self.sink.ack.eq(1),
+            If(self.sink.stb,
+                If(((self.sink.dchar == KCode["pak_end"]) & (self.sink.dchar_k == 1)),
+                    NextState("IDLE"),
+                ).Else(
+                    If(((self.sink.data != Cat(cnt, cnt+1, cnt+2, cnt+3))),  
+                        self.test_err.eq(1),
+                    ),
+                    If(cnt == 0xFC,
+                        NextValue(cnt, cnt.reset),
+                    ).Else(
+                        NextValue(cnt, cnt + 4)
+                    )
+                )
+            )
+                
+        )
+
+        # A circular buffer for firmware to read packet from
+        self.specials.mem = mem = Memory(word_dw, buffer_count*buffer_depth)
+        self.specials.mem_port = mem_port = mem.get_port(write_capable=True)
+
+        write_ptr = Signal(log2_int(buffer_count))
+        self.write_ptr_sys = Signal.like(write_ptr)
+        self.specials += MultiReg(write_ptr, self.write_ptr_sys),
+
+        self.comb += [
+            mem_port.adr[:addr_nbits].eq(addr),
+            mem_port.adr[addr_nbits:].eq(write_ptr),
+        ]
+
+        # For control ack, event packet
+        fsm.act("LOAD_BUFFER",
+            mem_port.we.eq(0),
+            self.sink.ack.eq(1),
+            If(self.sink.stb,
+                If(((self.sink.dchar == KCode["pak_end"]) & (self.sink.dchar_k == 1)),
+                    NextState("MOVE_BUFFER_PTR"),
+                ).Else(
+                    mem_port.we.eq(1),
+                    mem_port.dat_w.eq(self.sink.data),
+                    NextValue(addr, addr + 1),
+                    If(addr == buffer_depth - 1,
+                        # discard the packet
+                        self.buffer_err.eq(1),
+                        NextState("IDLE"),
+                    )
+                )
+            )
+        )
+
+        self.read_ptr_rx = Signal.like(write_ptr)
+        fsm.act("MOVE_BUFFER_PTR",
+            self.sink.ack.eq(0),
+            If(write_ptr + 1 == self.read_ptr_rx,
+                # if next one hasn't been read, overwrite the current buffer when new packet comes in
+                self.buffer_err.eq(1),
+            ).Else(
+                NextValue(write_ptr, write_ptr + 1),
+            ),
+            NextState("IDLE"),
+        )
+
+class Trigger_Ack_Checker(Module, AutoCSR):
+    def __init__(self):
+        self.sink = stream.Endpoint(word_layout_dchar)
+        self.source = stream.Endpoint(word_layout_dchar)
+
+        self.ack = Signal()
+
+        # # #
+
+        self.submodules.fsm = fsm = FSM(reset_state="COPY")
+
+        fsm.act("COPY",
+            If((self.sink.stb & (self.sink.dchar == KCode["io_ack"]) & (self.sink.dchar_k == 1)),
+                # discard K28,6
+                self.sink.ack.eq(1),
+                NextState("CHECK_ACK")
+            ).Else(
+                self.sink.connect(self.source),
+            )
+        )
+
+        fsm.act("CHECK_ACK",
+            If(self.sink.stb,
+                NextState("COPY"),
+                # discard the word after K28,6
+                self.sink.ack.eq(1),
+                If((self.sink.dchar == 0x01) & (self.sink.dchar_k == 0),
+                    self.ack.eq(1),
+                )
+            )
+        )

src/gateware/cxp_upconn.py

@@ -0,0 +1,224 @@
+from math import ceil
+
+from migen import *
+
+from misoc.cores.code_8b10b import SingleEncoder
+from misoc.interconnect import stream
+from misoc.interconnect.csr import *
+
+from cxp_pipeline import char_layout
+
+@ResetInserter()
+class UpConn_ClockGen(Module):
+    def __init__(self, sys_clk_freq):
+        self.clk = Signal()
+        self.clk_10x = Signal() # 20.83MHz 48ns or 41.66MHz 24ns
+
+        self.freq2x_enable = Signal()
+        # # #
+
+        period = 1e9/sys_clk_freq
+        max_count = ceil(48/period)
+        counter = Signal(max=max_count, reset=max_count-1)
+
+        clk_div = Signal(max=10, reset=9)
+
+        self.sync += [
+            self.clk.eq(0),
+            self.clk_10x.eq(0),
+
+            If(counter == 0,
+                self.clk_10x.eq(1),
+                If(self.freq2x_enable,
+                    counter.eq(int(max_count/2)-1),
+                ).Else(
+                    counter.eq(counter.reset),
+                ),
+            ).Else(
+                counter.eq(counter-1),
+            ),
+
+            If(counter == 0,
+                If(clk_div == 0,
+                    self.clk.eq(1),
+                    clk_div.eq(clk_div.reset),
+                ).Else(
+                    clk_div.eq(clk_div-1),
+                )
+            )
+
+        ]
+
+@ResetInserter()
+@CEInserter()
+class SERDES_10bits(Module):
+    def __init__(self, pad):
+        self.oe = Signal()
+        self.d = Signal(10)
+
+        # # #
+
+        o = Signal()
+        tx_bitcount = Signal(max=10)
+        tx_reg = Signal(10)
+
+        # DEBUG:
+        self.o = Signal()
+        self.comb += self.o.eq(o)
+
+        self.specials += Instance("OBUF", i_I=o, o_O=pad),
+        
+        self.sync += [
+            If(self.oe,
+                # send LSB first
+                o.eq(tx_reg[0]),
+                tx_reg.eq(Cat(tx_reg[1:], 0)),
+                tx_bitcount.eq(tx_bitcount + 1),   
+
+                If(tx_bitcount == 9,
+                    tx_bitcount.eq(0),
+                    tx_reg.eq(self.d),
+                ),
+            ).Else(
+                o.eq(0),
+                tx_bitcount.eq(0),
+            )
+        ]
+
+class Debug_buffer(Module,AutoCSR):
+    def __init__(self, layout):
+        self.sink_stb = Signal()
+        self.sink_ack = Signal()
+        self.sink_data = Signal(8)
+        self.sink_k = Signal()
+
+        # # #
+
+        self.submodules.buf_out = buf_out = stream.SyncFIFO(layout, 512)
+
+        self.sync += [
+            buf_out.sink.stb.eq(self.sink_stb),
+            self.sink_ack.eq(buf_out.sink.ack),
+            buf_out.sink.data.eq(self.sink_data),
+            buf_out.sink.k.eq(self.sink_k),
+        ]
+
+        self.inc = CSR()
+        self.dout_pak = CSRStatus(8)
+        self.kout_pak = CSRStatus()
+        self.dout_valid = CSRStatus()
+
+        self.sync += [
+            # output
+            buf_out.source.ack.eq(self.inc.re),
+            self.dout_pak.status.eq(buf_out.source.data),
+            self.kout_pak.status.eq(buf_out.source.k),
+            self.dout_valid.status.eq(buf_out.source.stb),
+        ]
+
+
+class Transmitter(Module, AutoCSR):
+    def __init__(self, pad, sys_clk_freq, debug_sma, pmod_pads):
+        self.bitrate2x_enable = Signal()
+        self.clk_reset = Signal()
+        self.tx_enable = Signal()
+
+        # # #
+
+        self.sink = stream.Endpoint(char_layout)
+
+        self.submodules.cg = cg = UpConn_ClockGen(sys_clk_freq)
+        self.submodules.encoder = encoder = SingleEncoder(True)
+        self.submodules.debug_buf = debug_buf = Debug_buffer(char_layout)
+
+        oe = Signal()
+        self.sync += [
+            If(self.tx_enable,
+                self.sink.ack.eq(0),
+
+                # DEBUG:
+                debug_buf.sink_stb.eq(0),
+
+                If(cg.clk,
+                    oe.eq(1),
+                    encoder.disp_in.eq(encoder.disp_out),
+                    self.sink.ack.eq(1),
+                    encoder.d.eq(self.sink.data),
+                    encoder.k.eq(self.sink.k),
+
+                    # DEBUG:
+                    If(debug_buf.sink_ack,
+                        debug_buf.sink_stb.eq(1),
+                        debug_buf.sink_data.eq(self.sink.data),
+                        debug_buf.sink_k.eq(self.sink.k),
+                    )
+                )
+            ).Else(
+                # DEBUG:
+                debug_buf.sink_stb.eq(0),
+
+                # no backpressure
+                self.sink.ack.eq(1),
+                oe.eq(0),
+            )
+        ]
+
+        self.submodules.serdes = serdes = SERDES_10bits(pad)
+
+        self.comb += [
+            cg.reset.eq(self.clk_reset),
+            cg.freq2x_enable.eq(self.bitrate2x_enable),
+
+            serdes.reset.eq(self.clk_reset),
+            serdes.ce.eq(cg.clk_10x),
+            serdes.d.eq(encoder.output),
+            serdes.oe.eq(oe),
+        ]
+
+        # DEBUG: remove pads
+       
+        self.specials += [
+            # # debug sma
+            # Instance("OBUF", i_I=serdes.o, o_O=debug_sma.p_tx),
+            Instance("OBUF", i_I=serdes.o, o_O=debug_sma.n_rx),
+
+
+
+            # # pmod 0-7 pin
+            # Instance("OBUF", i_I=serdes.o, o_O=pmod_pads[0]),
+            # Instance("OBUF", i_I=cg.clk_10x, o_O=pmod_pads[1]),
+            # Instance("OBUF", i_I=~tx_fifos.pe.n, o_O=pmod_pads[2]),
+            # Instance("OBUF", i_I=prioity_0, o_O=pmod_pads[3]),
+            # Instance("OBUF", i_I=word_bound, o_O=pmod_pads[4]),
+            # Instance("OBUF", i_I=debug_buf.buf_out.sink.stb, o_O=pmod_pads[4]),
+            # Instance("OBUF", i_I=debug_buf.buf_out.sink.ack, o_O=pmod_pads[5]),
+            # Instance("OBUF", i_I=debug_buf.buf_out.source.stb, o_O=pmod_pads[6]),
+            # Instance("OBUF", i_I=debug_buf.buf_out.source.ack, o_O=pmod_pads[7]),
+
+            # Instance("OBUF", i_I=scheduler.idling, o_O=pmod_pads[5]),
+            # # Instance("OBUF", i_I=tx_fifos.source_ack[0], o_O=pmod[6]),
+            # # Instance("OBUF", i_I=tx_fifos.source_ack[2], o_O=pmod[6]),
+            # # Instance("OBUF", i_I=tx_fifos.source_ack[1], o_O=pmod[7]),
+            # Instance("OBUF", i_I=p0, o_O=pmod_pads[6]),
+            # Instance("OBUF", i_I=p3, o_O=pmod_pads[7]),
+        ]
+
+class CXP_UpConn_PHYS(Module, AutoCSR):
+    def __init__(self, pads, sys_clk_freq, debug_sma, pmod_pads):
+        self.clk_reset = CSR()
+        self.bitrate2x_enable = CSRStorage()
+        self.tx_enable = CSRStorage()
+
+        # # #
+
+
+        self.tx_phys = []
+        for i, pad in enumerate(pads):
+            tx = Transmitter(pad, sys_clk_freq, debug_sma, pmod_pads)
+            self.tx_phys.append(tx)
+            setattr(self.submodules, "tx"+str(i), tx)
+            self.sync += [
+                tx.clk_reset.eq(self.clk_reset.re),
+                tx.bitrate2x_enable.eq(self.bitrate2x_enable.storage),
+                tx.tx_enable.eq(self.tx_enable.storage),
+            ]

src/gateware/kasli_soc.py

@@ -560,7 +560,10 @@ class GenericSatellite(SoCCore):
         self.submodules.local_io = SyncRTIO(
             self.rtio_tsc, self.rtio_channels, lane_count=description["sed_lanes"]
         )
-        self.comb += self.drtiosat.async_errors.eq(self.local_io.async_errors)
+        self.comb += [
+            self.drtiosat.async_errors.eq(self.local_io.async_errors),
+            self.local_io.sed_spread_enable.eq(self.drtiosat.sed_spread_enable.storage)
+        ]
 
         self.submodules.cri_con = rtio.CRIInterconnectShared(
             [self.drtiosat.cri, self.rtio_dma.cri, self.rtio.cri],

src/gateware/zc706.py

@@ -25,6 +25,8 @@ import analyzer
 import acpki
 import drtio_aux_controller
 import zynq_clocking
+import cxp_4r_fmc
+import cxp
 from config import write_csr_file, write_mem_file, write_rustc_cfg_file
 
 class SMAClkinForward(Module):
@@ -138,7 +140,7 @@ class ZC706(SoCCore):
         platform.add_extension(si5324_fmc33)
         self.comb += platform.request("si5324_33").rst_n.eq(1)
 
-        cdr_clk = Signal()
+        self.cdr_clk = Signal()
         cdr_clk_buf = Signal()
         si5324_out = platform.request("si5324_clkout")
         platform.add_period_constraint(si5324_out.p, 8.0)
@@ -146,11 +148,11 @@ class ZC706(SoCCore):
             Instance("IBUFDS_GTE2",
                 i_CEB=0,
                 i_I=si5324_out.p, i_IB=si5324_out.n,
-                o_O=cdr_clk,
+                o_O=self.cdr_clk,
                 p_CLKCM_CFG="TRUE",
                 p_CLKRCV_TRST="TRUE",
                 p_CLKSWING_CFG=3),
-            Instance("BUFG", i_I=cdr_clk, o_O=cdr_clk_buf)
+            Instance("BUFG", i_I=self.cdr_clk, o_O=cdr_clk_buf)
         ]
         self.config["HAS_SI5324"] = None
         self.config["SI5324_AS_SYNTHESIZER"] = None
@@ -487,6 +489,10 @@ class _SatelliteBase(SoCCore):
         self.csr_devices.append("rtio_dma")
 
         self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels)
+        self.comb += [
+            self.drtiosat.async_errors.eq(self.local_io.async_errors),
+            self.local_io.sed_spread_enable.eq(self.drtiosat.sed_spread_enable.storage)
+        ]
         self.submodules.cri_con = rtio.CRIInterconnectShared(
             [self.drtiosat.cri, self.rtio_dma.cri, self.rtio.cri],
             [self.local_io.cri] + self.drtio_cri,
@@ -648,6 +654,129 @@ class _NIST_QC2_RTIO:
         self.add_rtio(rtio_channels)
 
 
+class CXP_FMC():
+    """
+    CoaXpress FMC with 4 CXP channel and 1 SMA trigger
+    """
+    def __init__(self):
+        platform = self.platform
+        platform.add_extension(cxp_4r_fmc.fmc_adapter_io)
+        platform.add_extension(leds_fmc33)
+
+        debug_sma = [
+            ("user_sma_clock_33", 0,
+                Subsignal("p_tx", Pins("AD18"), IOStandard("LVCMOS33")),
+                Subsignal("n_rx", Pins("AD19"), IOStandard("LVCMOS33")),
+            ),
+        ]
+
+        pmod1_33 = [
+            ("pmod1_33", 0, Pins("AJ21"), IOStandard("LVCMOS33")),
+            ("pmod1_33", 1, Pins("AK21"), IOStandard("LVCMOS33")),
+            ("pmod1_33", 2, Pins("AB21"), IOStandard("LVCMOS33")),
+            ("pmod1_33", 3, Pins("AB16"), IOStandard("LVCMOS33")),
+            ("pmod1_33", 4, Pins("Y20"), IOStandard("LVCMOS33")),
+            ("pmod1_33", 5, Pins("AA20"), IOStandard("LVCMOS33")),
+            ("pmod1_33", 6, Pins("AC18"), IOStandard("LVCMOS33")),
+            ("pmod1_33", 7, Pins("AC19"), IOStandard("LVCMOS33")),
+        ]
+
+        platform.add_extension(debug_sma)
+        platform.add_extension(pmod1_33)
+        debug_sma_pad = platform.request("user_sma_clock_33") 
+        pmod_pads = [platform.request("pmod1_33", i) for i in range(8)]
+
+        clk_freq = 125e6
+
+        links = 1
+        cxp_downconn_pads = [platform.request("CXP_HS", i) for i in range(links)]
+        cxp_upconn_pads = [platform.request("CXP_LS", i) for i in range(links)]
+
+
+        self.submodules.cxp_phys = cxp_phys = cxp.CXP_PHYS(
+            refclk=self.cdr_clk,
+            upconn_pads=cxp_upconn_pads,
+            downconn_pads=cxp_downconn_pads,
+            sys_clk_freq=clk_freq,
+            debug_sma=debug_sma_pad,
+            pmod_pads = pmod_pads
+        )
+        self.csr_devices.append("cxp_phys")
+
+
+        rtio_channels = []
+        cxp_csr_group = []
+        cxp_tx_mem_group = []
+        cxp_rx_mem_group = []
+        cxp_loopback_mem_group = []
+        for i, (tx, rx) in enumerate(zip(cxp_phys.upconn.tx_phys, cxp_phys.downconn.rx_phys)):
+            cxp_name = "cxp" + str(i)
+
+            cdr = ClockDomainsRenamer({"cxp_gtx_rx": "cxp_gtx_rx" + str(i)})
+            
+            if i == 0:
+                cxp_interface = cdr(cxp.CXP_Master(tx, rx, debug_sma_pad, pmod_pads))
+
+                # Add rtlink for Master Connection only
+                print("CoaXPress at RTIO channel 0x{:06x}".format(len(rtio_channels)))
+                rtio_channels.append(rtio.Channel.from_phy(cxp_interface))
+
+            else:
+                cxp_interface = cdr(cxp.CXP_Extension(tx, rx, debug_sma_pad, pmod_pads))
+
+            setattr(self.submodules, cxp_name, cxp_interface)
+            self.csr_devices.append(cxp_name)
+            cxp_csr_group.append(cxp_name)
+
+
+
+            # Add memory group
+            rx_mem_name = "cxp_rx" + str(i) + "_mem"
+            rx_mem_size = cxp_interface.get_rx_mem_size()
+            cxp_rx_mem_group.append(rx_mem_name)
+            memory_address = self.axi2csr.register_port(cxp_interface.get_rx_port(), rx_mem_size)
+            self.add_memory_region(rx_mem_name, self.mem_map["csr"] + memory_address, rx_mem_size)
+
+            tx_mem_name = "cxp_tx" + str(i) + "_mem"
+            tx_mem_size = cxp_interface.get_tx_mem_size()
+            cxp_tx_mem_group.append(tx_mem_name)
+            memory_address = self.axi2csr.register_port(cxp_interface.get_tx_port(), tx_mem_size)
+            self.add_memory_region(tx_mem_name, self.mem_map["csr"] + memory_address, tx_mem_size)
+
+            # DEBUG loopback tx memory
+            loopback_mem_name = "cxp_loopback_tx" + str(i) + "_mem"
+            loopback_mem_size = cxp_interface.get_loopback_tx_mem_size()
+            cxp_loopback_mem_group.append(loopback_mem_name)
+            memory_address = self.axi2csr.register_port(cxp_interface.get_loopback_tx_port(), loopback_mem_size)
+            self.add_memory_region(loopback_mem_name, self.mem_map["csr"] + memory_address, loopback_mem_size)
+
+        self.add_memory_group("cxp_tx_mem", cxp_tx_mem_group)
+        self.add_memory_group("cxp_rx_mem", cxp_rx_mem_group)
+        self.add_memory_group("cxp_loopback_mem", cxp_loopback_mem_group)
+        self.add_csr_group("cxp", cxp_csr_group)
+
+        # max freq of cxp_gtx_rx = linerate/internal_datawidth = 12.5Gbps/40 = 312.5MHz
+        # zc706 use speed grade 2 which only support up to 10.3125Gbps (4ns)
+        # pushing to 12.5Gbps (3.2ns) will result in Pulse width violation but setup/hold times are met
+        for rx in cxp_phys.downconn.rx_phys :
+            platform.add_period_constraint(rx.gtx.cd_cxp_gtx_tx.clk, 3.2)
+            platform.add_period_constraint(rx.gtx.cd_cxp_gtx_rx.clk, 3.2)
+            # constraint the CLK path 
+            platform.add_false_path_constraints(self.sys_crg.cd_sys.clk, rx.gtx.cd_cxp_gtx_tx.clk, rx.gtx.cd_cxp_gtx_rx.clk)
+
+        # FIXME remove this placeholder RTIO channel
+        # There are too few RTIO channels and cannot be compiled (adr width issue of the lane distributor)
+        # see https://github.com/m-labs/artiq/pull/2158 for similar issue
+        print("USER LED at RTIO channel 0x{:06x}".format(len(rtio_channels)))
+        phy = ttl_simple.Output(self.platform.request("user_led_33", 0))
+        self.submodules += phy
+        rtio_channels.append(rtio.Channel.from_phy(phy))
+        self.config["HAS_RTIO_LOG"] = None
+        rtio_channels.append(rtio.LogChannel())
+
+        self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
+        self.add_rtio(rtio_channels)
+
 class NIST_CLOCK(ZC706, _NIST_CLOCK_RTIO):
     def __init__(self, acpki, drtio100mhz):
         ZC706.__init__(self, acpki)
@@ -680,8 +809,13 @@ class NIST_QC2_Satellite(_SatelliteBase, _NIST_QC2_RTIO):
         _SatelliteBase.__init__(self, acpki, drtio100mhz)
         _NIST_QC2_RTIO.__init__(self)
 
+class CXP_Demo(ZC706, CXP_FMC):
+    def __init__(self, acpki, drtio100mhz):
+        ZC706.__init__(self, acpki)
+        CXP_FMC.__init__(self)
+
 VARIANTS = {cls.__name__.lower(): cls for cls in [NIST_CLOCK, NIST_CLOCK_Master, NIST_CLOCK_Satellite,
-                                                  NIST_QC2, NIST_QC2_Master, NIST_QC2_Satellite]}
+                                                  NIST_QC2, NIST_QC2_Master, NIST_QC2_Satellite, CXP_Demo]}
 
 def main():
     parser = argparse.ArgumentParser(

src/libboard_artiq/Cargo.toml.tpl

@@ -23,6 +23,7 @@ core_io = { version = "0.1", features = ["collections"] }
 embedded-hal = "0.2"
 nb = "1.0"
 void = { version = "1", default-features = false }
+byteorder = { version = "1.3", default-features = false }
 
 io = { path = "../libio", features = ["byteorder"] }
 libboard_zynq = { path = "@@ZYNQ_RS@@/libboard_zynq" }

src/libboard_artiq/src/cxp.rs

@@ -0,0 +1,172 @@
+use embedded_hal::blocking::delay::DelayMs;
+use libboard_zynq::timer::GlobalTimer;
+use log::{info, warn};
+
+use crate::{cxp_comms,
+            cxp_comms::Error,
+            cxp_phys,
+            pl::{csr, csr::CXP}};
+
+const STANDARD: u32 = 0x0000;
+const REVISION: u32 = 0x0004;
+const CONNECTION_RESET: u32 = 0x4000;
+const CONTROL_PACKET_SIZE_MAX: u32 = 0x400C;
+const STREAM_PACKET_SIZE_MAX: u32 = 0x4010;
+const CONNECTION_CFG: u32 = 0x4014;
+const CONNECTION_CFG_DEF: u32 = 0x4018;
+const TESTMODE: u32 = 0x401C;
+const CAPABILITY_REGISTER: u32 = 0x403C;
+const VERSION_SUPPORTED: u32 = 0x4044;
+const VERSION_USED: u32 = 0x4048;
+
+const MASTER_CHANNEL: u8 = 0;
+
+pub fn setup(timer: &mut GlobalTimer) {
+    cxp_phys::setup(timer);
+    if let Err(e) = probe_connections(timer) {
+        warn!("CXP init failure {:?} ", e);
+    };
+}
+
+fn connection_reset(channel: u8) -> Result<(), Error> {
+    // ConnectionReset
+    // without this, camera will still blind red @ 1Hz (i.e. no connection)
+    // TODO: rename cxp_comms to cxp_ctrl
+    cxp_comms::write_u32_no_ack(channel, CONNECTION_RESET, 1, false)
+}
+
+fn scan_channels_status() -> Result<(), Error> {
+    let mut result = Err(Error::LinkDown);
+    for ch in 0..cxp_phys::CXP_CHANNELS {
+        if unsafe { (CXP[ch as usize].downconn_rx_ready_read)() } == 1 {
+            info!("CHANNEL #{} discovered", ch);
+            result = Ok(());
+        }
+    }
+    result
+}
+
+fn discover_channels(timer: &mut GlobalTimer) -> Result<(), Error> {
+    // only the simple topology MASTER:ch0, extension:ch1,2,3 is supported right now
+    // TODO: properly support other topology
+
+    // Section 7.6 (CXP-001-2021)
+    // 1.25Gbps (CXP_1) and 3.125Gbps (CXP_3) are the discovery rate
+    // both linerate need to be checked as camera only support ONE of discovery rate
+    for speed in [cxp_phys::CXP_SPEED::CXP_1, cxp_phys::CXP_SPEED::CXP_3].iter() {
+        // Section 12.1.2 (CXP-001-2021)
+        // reset -> wait 200ms -> scan for active channels
+        connection_reset(MASTER_CHANNEL)?;
+
+        cxp_phys::change_linerate(*speed);
+        timer.delay_ms(200);
+        if scan_channels_status().is_ok() {
+            return Ok(());
+        }
+    }
+    Err(Error::LinkDown)
+}
+
+fn negotiate_cxp_version() -> Result<bool, Error> {
+    let rev = cxp_comms::read_u32(MASTER_CHANNEL, REVISION, false)?;
+
+    let mut major_rev: u32 = rev >> 16;
+    let mut minor_rev: u32 = rev & 0xFF;
+    info!("Camera's CXP revision is {}.{}", major_rev, minor_rev);
+
+    // Section 12.1.4 (CXP-001-2021)
+    // For CXP 2.0 and onward, Host need to check the VersionSupported register to determine
+    // the highest common version that supported by both device & host
+    if major_rev >= 2 {
+        let reg = cxp_comms::read_u32(MASTER_CHANNEL, VERSION_SUPPORTED, false)?;
+
+        if ((reg >> 3) & 1) == 1 {
+            major_rev = 2;
+            minor_rev = 1;
+        } else if ((reg >> 2) & 1) == 1 {
+            major_rev = 2;
+            minor_rev = 0;
+        } else {
+            return Err(Error::UnsupportedVersion);
+        }
+
+        cxp_comms::write_u32(MASTER_CHANNEL, VERSION_USED, major_rev << 16 | minor_rev, false)?;
+    }
+    info!(
+        "Camera supports CXP {}.{}, using CXP {}.{} protcol now",
+        major_rev, minor_rev, major_rev, minor_rev
+    );
+
+    let with_tag = major_rev >= 2;
+    Ok(with_tag)
+}
+
+fn negotiate_pak_max_size(with_tag: bool) -> Result<(), Error> {
+    let reg = cxp_comms::read_u32(MASTER_CHANNEL, CONTROL_PACKET_SIZE_MAX, with_tag)?;
+    info!("Max CTRL PAK size = {:#010X}", reg);
+
+    let reg = cxp_comms::read_u32(MASTER_CHANNEL, STREAM_PACKET_SIZE_MAX, with_tag)?;
+    info!("Max STREAM PAK size = {:#010X}", reg);
+    // TODO: set stream packet size
+    Ok(())
+}
+
+fn check_standard() -> Result<(), Error> {
+    let reg = cxp_comms::read_u32(MASTER_CHANNEL, STANDARD, true)?;
+    info!("CoaXPress special WORD = {:#010X} !!!", reg);
+    Ok(())
+}
+
+fn check_optional_features() -> Result<(), Error> {
+    let reg = cxp_comms::read_u32(MASTER_CHANNEL, CAPABILITY_REGISTER, true)?;
+    info!("Camera optional feature = {:#010X}", reg);
+    Ok(())
+}
+
+fn decode_cxp_speed(code: u32) -> Option<cxp_phys::CXP_SPEED> {
+    match code {
+        0x28 => Some(cxp_phys::CXP_SPEED::CXP_1),
+        0x30 => Some(cxp_phys::CXP_SPEED::CXP_2),
+        0x38 => Some(cxp_phys::CXP_SPEED::CXP_3),
+        0x40 => Some(cxp_phys::CXP_SPEED::CXP_5),
+        0x48 => Some(cxp_phys::CXP_SPEED::CXP_6),
+        0x50 => Some(cxp_phys::CXP_SPEED::CXP_10),
+        0x58 => Some(cxp_phys::CXP_SPEED::CXP_12),
+        _ => None,
+    }
+}
+
+fn set_operation_linerate(with_tag: bool, timer: &mut GlobalTimer) -> Result<(), Error> {
+    let reg = cxp_comms::read_u32(MASTER_CHANNEL, CONNECTION_CFG, with_tag)?;
+    info!("Current connection cfg = {:#010X}", reg);
+
+    let cfg = cxp_comms::read_u32(MASTER_CHANNEL, CONNECTION_CFG_DEF, with_tag)?;
+    info!("Best connection cfg = {:#010X}", cfg);
+
+    if let Some(speed) = decode_cxp_speed(cfg & 0xFF) {
+        cxp_comms::write_u32(MASTER_CHANNEL, CONNECTION_CFG, cfg, with_tag)?;
+
+        cxp_phys::change_linerate(speed);
+        timer.delay_ms(500);
+        scan_channels_status()
+    } else {
+        Err(Error::UnsupportedSpeed)
+    }
+}
+
+fn probe_connections(timer: &mut GlobalTimer) -> Result<(), Error> {
+    discover_channels(timer)?;
+    // TODO: Section 12.1.3 (CXP-001-2021)
+    // TODO: add a topology struct and output master channel??
+    // discover_topology(); // get master_channel here
+
+    let with_tag = negotiate_cxp_version()?;
+    // CXP 2.x ONLY, need TAGS
+    // negotiate_pak_max_size(with_tag)?;
+    set_operation_linerate(with_tag, timer)?;
+
+    // DEBUG: print
+    // check_standard()?;
+    // check_optional_features()?;
+    Ok(())
+}

src/libboard_artiq/src/cxp_comms.rs

@@ -0,0 +1,219 @@
+use core::slice;
+
+use byteorder::{ByteOrder, NetworkEndian};
+use embedded_hal::blocking::delay::DelayMs;
+use io::Cursor;
+use libboard_zynq::{println, time::Milliseconds, timer::GlobalTimer};
+use log::info;
+
+use crate::{cxp_proto::{print_packet, DownConnPacket, Error as ProtoError, UpConnPacket, DATA_MAXSIZE},
+            mem::mem::{CXP_RX_MEM, CXP_TX_MEM},
+            pl::{csr, csr::CXP}};
+
+#[derive(Debug)]
+pub enum Error {
+    LinkDown,
+    TimedOut,
+    UnexpectedReply,
+    UnsupportedVersion,
+    UnsupportedSpeed,
+    WrongTag(u8),
+    Protocol(ProtoError),
+}
+impl From<ProtoError> for Error {
+    fn from(value: ProtoError) -> Error {
+        Error::Protocol(value)
+    }
+}
+
+const BUF_LEN: usize = 0x800;
+const TRANSMISSION_TIMEOUT: u64 = 200;
+pub const MASTER_CHANNEL: u8 = 0;
+
+fn packet_pending(channel: u8) -> bool {
+    unsafe { (CXP[channel as usize].downconn_pending_packet_read)() == 1 }
+}
+
+fn receive(channel: u8) -> Result<Option<DownConnPacket>, Error> {
+    if packet_pending(channel) {
+        let channel = channel as usize;
+        unsafe {
+            let read_buffer_ptr = (CXP[channel].downconn_read_ptr_read)() as usize;
+            println!("buffer ptr = {}", read_buffer_ptr);
+            let ptr = (CXP_RX_MEM[channel].base + read_buffer_ptr * BUF_LEN) as *mut u32;
+
+            let mut reader = Cursor::new(slice::from_raw_parts_mut(ptr as *mut u8, BUF_LEN));
+            let packet_type = (CXP[channel].downconn_packet_type_read)();
+
+            let packet = DownConnPacket::read_from(&mut reader, packet_type);
+            println!("{:X?}", packet);
+
+            (CXP[channel].downconn_pending_packet_write)(1);
+            Ok(Some(packet?))
+        }
+    } else {
+        Ok(None)
+    }
+}
+
+fn receive_timeout(channel: u8, timeout_ms: u64) -> Result<DownConnPacket, Error> {
+    let timer = unsafe { GlobalTimer::get() };
+    let limit = timer.get_time() + Milliseconds(timeout_ms);
+    while timer.get_time() < limit {
+        match receive(channel)? {
+            None => (),
+            Some(packet) => return Ok(packet),
+        }
+    }
+    Err(Error::TimedOut)
+}
+
+fn send_data_packet(channel: u8, packet: &UpConnPacket) -> Result<(), Error> {
+    let channel = channel as usize;
+    unsafe {
+        if csr::cxp_phys::upconn_tx_enable_read() == 0 {
+            return Err(Error::LinkDown);
+        }
+
+        while (CXP[channel].upconn_bootstrap_tx_busy_read)() == 1 {}
+        let ptr = CXP_TX_MEM[0].base as *mut u32;
+        let mut writer = Cursor::new(slice::from_raw_parts_mut(ptr as *mut u8, BUF_LEN));
+
+        packet.write_to(&mut writer)?;
+        // DEBUG:
+        // println!("TX MEM after writing");
+        // print_packet(&writer.get_ref()[0..40]);
+
+        (CXP[channel].upconn_bootstrap_tx_word_len_write)(writer.position() as u16 / 4);
+        (CXP[channel].upconn_bootstrap_tx_write)(1);
+    }
+
+    Ok(())
+}
+
+fn send_test_packet(channel: u8) -> Result<(), Error> {
+    let channel = channel as usize;
+    unsafe {
+        if csr::cxp_phys::upconn_tx_enable_read() == 0 {
+            return Err(Error::LinkDown);
+        }
+
+        while (CXP[channel].upconn_bootstrap_tx_busy_read)() == 1 {}
+        (CXP[channel].upconn_bootstrap_tx_testseq_write)(1);
+    }
+    Ok(())
+}
+
+//
+//
+// DEBUG:
+//
+//
+pub fn downconn_debug_mem_print(channel: u8) {
+    unsafe {
+        let ptr = CXP_RX_MEM[channel as usize].base as *mut u32;
+        let arr = slice::from_raw_parts_mut(ptr as *mut u8, BUF_LEN * 4);
+        print_packet(arr);
+    }
+}
+
+//
+//
+// CTRL packet
+//
+//
+
+static mut TAG: u8 = 0;
+
+pub fn reset_tag() {
+    unsafe { TAG = 0 }
+}
+
+pub fn delay_ms(ms: u64) {
+    // assume timer was initialized successfully
+    // CXP comms api calls need to have delay
+    unsafe { GlobalTimer::get() }.delay_ms(ms);
+}
+
+fn check_tag(tag: Option<u8>) -> Result<(), Error> {
+    unsafe {
+        if tag.is_some() && tag != Some(TAG) {
+            Err(Error::WrongTag(tag.unwrap()))
+        } else {
+            Ok(())
+        }
+    }
+}
+
+fn process_ack_packet(channel: u8, timeout: u64) -> Result<(), Error> {
+    match receive_timeout(channel, timeout) {
+        Ok(DownConnPacket::CtrlDelay { tag, time }) => {
+            check_tag(tag)?;
+
+            info!("delaying by {} ms ....", time);
+            process_ack_packet(channel, time as u64)
+        }
+        Ok(DownConnPacket::CtrlAck { .. }) => Ok(()),
+        Ok(_) => Err(Error::UnexpectedReply),
+        Err(e) => Err(e),
+    }
+}
+
+pub fn write_u32_no_ack(channel: u8, addr: u32, val: u32, with_tag: bool) -> Result<(), Error> {
+    let mut data: [u8; DATA_MAXSIZE] = [0; DATA_MAXSIZE];
+    NetworkEndian::write_u32(&mut data[..4], val);
+
+    let tag: Option<u8> = if with_tag { Some(unsafe { TAG }) } else { None };
+    send_data_packet(
+        channel,
+        &UpConnPacket::CtrlWrite {
+            tag,
+            addr,
+            length: 4,
+            data,
+        },
+    )
+}
+
+pub fn write_u32(channel: u8, addr: u32, val: u32, with_tag: bool) -> Result<(), Error> {
+    write_u32_no_ack(channel, addr, val, with_tag)?;
+    process_ack_packet(channel, TRANSMISSION_TIMEOUT)?;
+
+    if with_tag {
+        unsafe { TAG = TAG.wrapping_add(1) };
+    };
+    Ok(())
+}
+
+fn process_reply_packet(channel: u8) -> Result<u32, Error> {
+    // TODO: turn this into macro??
+    match receive_timeout(channel, TRANSMISSION_TIMEOUT) {
+        Ok(DownConnPacket::CtrlReply { tag, length, data }) => {
+            check_tag(tag)?;
+
+            if length != 4 {
+                return Err(Error::UnexpectedReply);
+            }
+
+            // TODO: how to deal with tag?
+            let mut bytes = [0; 4];
+            bytes.clone_from_slice(&data[0..4]);
+
+            Ok(NetworkEndian::read_u32(&bytes))
+        }
+        Ok(_) => Err(Error::UnexpectedReply),
+        Err(e) => Err(e),
+    }
+}
+
+pub fn read_u32(channel: u8, addr: u32, with_tag: bool) -> Result<u32, Error> {
+    let tag: Option<u8> = if with_tag { Some(unsafe { TAG }) } else { None };
+    send_data_packet(channel, &UpConnPacket::CtrlRead { tag, addr, length: 4 })?;
+
+    let val = process_reply_packet(channel)?;
+
+    if with_tag {
+        unsafe { TAG = TAG.wrapping_add(1) };
+    };
+    Ok(val)
+}

src/libboard_artiq/src/cxp_downconn.rs

@@ -0,0 +1,94 @@
+use embedded_hal::prelude::_embedded_hal_blocking_delay_DelayUs;
+use libboard_zynq::{println, timer::GlobalTimer};
+use log::info;
+
+use crate::{cxp_phys, pl::csr::CXP};
+
+pub fn loopback_testing(channel: usize, timer: &mut GlobalTimer, speed: cxp_phys::CXP_SPEED) {
+    println!("==============================================================================");
+    cxp_phys::change_linerate(speed);
+
+    unsafe {
+        info!("waiting for tx&rx setup...");
+        timer.delay_us(50_000);
+        info!(
+            "tx_phaligndone = {} | rx_phaligndone = {}",
+            (CXP[channel].downconn_txinit_phaligndone_read)(),
+            (CXP[channel].downconn_rxinit_phaligndone_read)(),
+        );
+
+        // enable txdata tranmission thought MGTXTXP, required by PMA loopback
+        (CXP[channel].downconn_txenable_write)(1);
+
+        info!("waiting for rx to align...");
+        while (CXP[channel].downconn_rx_ready_read)() != 1 {}
+        info!("rx ready!");
+
+        // cxp_proto::downconn_send_test_packet(channel);
+
+        // FIXME: why test + trig ack doesn't work well for rx??
+        // cxp_proto::downconn_debug_send_trig_ack(channel);
+
+        // const DATA_MAXSIZE: usize = 253;
+        // let data_size = 4; // no. of bytes
+
+        // let data: u32 = 0xDADA as u32;
+        // let mut data_slice: [u8; DATA_MAXSIZE] = [0; DATA_MAXSIZE];
+        // data_slice[..4].clone_from_slice(&data.to_be_bytes());
+        // cxp_proto::downconn_debug_send(
+        //     channel,
+        //     &cxp_proto::UpConnPacket::Event {
+        //         conn_id: 0x1234_5678_u32,
+        //         packet_tag: 0x69_u8,
+        //         length: data_size + 3,
+        //         event_size: data_size,
+        //         namespace: 0x02_u8,
+        //         event_id: 0x00_6969u16,
+        //         timestamp: 0x1234_5678u64,
+        //         data: data_slice,
+        //     },
+        // )
+        // .expect("loopback gtx tx error");
+
+        timer.delay_us(1000); // wait packet has arrive at RX async fifo
+
+        if (CXP[channel].downconn_trigger_ack_read)() == 1 {
+            (CXP[channel].downconn_trigger_ack_write)(1);
+            info!("trig ack and cleared");
+        }
+
+        if (CXP[channel].downconn_bootstrap_decoder_err_read)() == 1 {
+            info!("!!!!!!!DECODER ERROR!!!!!!! and cleared");
+            (CXP[channel].downconn_bootstrap_decoder_err_write)(1);
+        }
+
+        if (CXP[channel].downconn_bootstrap_test_err_read)() == 1 {
+            info!("!!!!!!!TEST ERROR!!!!!!! and cleared");
+            (CXP[channel].downconn_bootstrap_test_err_write)(1);
+        }
+
+        info!("packet type = {:#06X}", (CXP[channel].downconn_packet_type_read)());
+
+        // cxp_proto::receive(channel as u8).expect("loopback gtx rx error");
+        // cxp_proto::downconn_debug_mem_print(channel);
+
+        // DEBUG: print loopback packets
+        const LEN: usize = 20;
+        let mut pak_arr: [u32; LEN] = [0; LEN];
+        let mut k_arr: [u8; LEN] = [0; LEN];
+        let mut i: usize = 0;
+        while (CXP[channel].downconn_debug_out_dout_valid_read)() == 1 {
+            pak_arr[i] = (CXP[channel].downconn_debug_out_dout_pak_read)();
+            k_arr[i] = (CXP[channel].downconn_debug_out_kout_pak_read)();
+            // println!("received {:#04X}", pak_arr[i]);
+            (CXP[channel].downconn_debug_out_inc_write)(1);
+            i += 1;
+            if i == LEN {
+                break;
+            }
+        }
+
+        info!("rx ready = {}", (CXP[channel].downconn_rx_ready_read)());
+        // cxp_proto::print_packetu32(&pak_arr, &k_arr);
+    }
+}

src/libboard_artiq/src/cxp_phys.rs

@@ -0,0 +1,217 @@
+use embedded_hal::prelude::_embedded_hal_blocking_delay_DelayUs;
+use libboard_zynq::{println, timer::GlobalTimer};
+use log::info;
+
+use crate::pl::{csr, csr::CXP};
+
+pub const CXP_CHANNELS: usize = csr::CXP_LEN;
+
+#[derive(Clone, Copy, Debug)]
+#[allow(non_camel_case_types)]
+pub enum CXP_SPEED {
+    CXP_1,
+    CXP_2,
+    CXP_3,
+    CXP_5,
+    CXP_6,
+    CXP_10,
+    CXP_12,
+}
+
+pub fn setup(timer: &mut GlobalTimer) {
+    down_conn::setup(timer);
+    up_conn::setup();
+    change_linerate(CXP_SPEED::CXP_1);
+}
+
+pub fn change_linerate(speed: CXP_SPEED) {
+    info!("Changing all channels datarate to {:?}", speed);
+    down_conn::change_linerate(speed);
+    up_conn::change_linerate(speed);
+}
+
+mod up_conn {
+    use super::*;
+
+    pub fn setup() {
+        unsafe {
+            csr::cxp_phys::upconn_tx_enable_write(1);
+        }
+    }
+
+    pub fn change_linerate(speed: CXP_SPEED) {
+        unsafe {
+            match speed {
+                CXP_SPEED::CXP_1 | CXP_SPEED::CXP_2 | CXP_SPEED::CXP_3 | CXP_SPEED::CXP_5 | CXP_SPEED::CXP_6 => {
+                    csr::cxp_phys::upconn_bitrate2x_enable_write(0);
+                }
+                CXP_SPEED::CXP_10 | CXP_SPEED::CXP_12 => {
+                    csr::cxp_phys::upconn_bitrate2x_enable_write(1);
+                }
+            };
+            csr::cxp_phys::upconn_clk_reset_write(1);
+        }
+    }
+}
+
+mod down_conn {
+    use super::*;
+
+    pub fn setup(timer: &mut GlobalTimer) {
+        unsafe {
+            csr::cxp_phys::downconn_qpll_reset_write(1);
+            info!("waiting for QPLL/CPLL to lock...");
+            while csr::cxp_phys::downconn_qpll_locked_read() != 1 {}
+            info!("QPLL locked");
+
+            for channel in 0..CXP_CHANNELS {
+                (CXP[channel].downconn_rx_start_init_write)(1);
+            }
+
+            // DEBUG: printout
+            info!("waiting for rx setup...");
+            timer.delay_us(50_000);
+            for channel in 0..CXP_CHANNELS {
+                info!("rx_phaligndone = {}", (CXP[channel].downconn_rxinit_phaligndone_read)(),);
+            }
+        }
+    }
+
+    pub fn change_linerate(speed: CXP_SPEED) {
+        change_qpll_fb_divider(speed);
+        change_gtx_divider(speed);
+        change_cdr_cfg(speed);
+
+        unsafe {
+            csr::cxp_phys::downconn_qpll_reset_write(1);
+            info!("waiting for QPLL/CPLL to lock...");
+            while csr::cxp_phys::downconn_qpll_locked_read() != 1 {}
+            info!("QPLL locked");
+
+            for channel in 0..CXP_CHANNELS {
+                (CXP[channel].downconn_rx_restart_write)(1);
+            }
+        }
+    }
+
+    fn change_qpll_fb_divider(speed: CXP_SPEED) {
+        let qpll_div_reg = match speed {
+            CXP_SPEED::CXP_1 | CXP_SPEED::CXP_2 | CXP_SPEED::CXP_5 | CXP_SPEED::CXP_10 => 0x0120, // FB_Divider = 80
+            CXP_SPEED::CXP_3 | CXP_SPEED::CXP_6 | CXP_SPEED::CXP_12 => 0x0170,                    // FB_Divider = 100
+        };
+
+        // DEBUG:
+        println!("QPLL DRP:");
+        println!("0x36 = {:#06x}", qpll_read(0x36));
+        qpll_write(0x36, qpll_div_reg);
+        println!("0x36 = {:#06x}", qpll_read(0x36));
+    }
+
+    fn change_gtx_divider(speed: CXP_SPEED) {
+        let div_reg = match speed {
+            CXP_SPEED::CXP_1 => 0x33,                      // RXOUT_DIV = 8
+            CXP_SPEED::CXP_2 | CXP_SPEED::CXP_3 => 0x22,   // RXOUT_DIV = 4
+            CXP_SPEED::CXP_5 | CXP_SPEED::CXP_6 => 0x11,   // RXOUT_DIV = 2
+            CXP_SPEED::CXP_10 | CXP_SPEED::CXP_12 => 0x00, // RXOUT_DIV = 1
+        };
+
+        // DEBUG:
+        println!("RX GTX DRP:");
+        for channel in 0..CXP_CHANNELS {
+            println!("channel {}, 0x88 = {:#06x}", channel, gtx_read(channel, 0x88));
+            gtx_write(channel, 0x88, div_reg);
+            println!("channel {}, 0x88 = {:#06x}", channel, gtx_read(channel, 0x88));
+        }
+    }
+
+    fn change_cdr_cfg(speed: CXP_SPEED) {
+        struct CdrConfig {
+            pub cfg_reg0: u16, // addr = 0xA8
+            pub cfg_reg1: u16, // addr = 0xA9
+            pub cfg_reg2: u16, // addr = 0xAA
+            pub cfg_reg3: u16, // addr = 0xAB
+            pub cfg_reg4: u16, // addr = 0xAC
+        }
+
+        let cdr_cfg = match speed {
+            // when RXOUT_DIV = 8
+            CXP_SPEED::CXP_1 => CdrConfig {
+                cfg_reg0: 0x0020,
+                cfg_reg1: 0x1008,
+                cfg_reg2: 0x23FF,
+                cfg_reg3: 0x0000,
+                cfg_reg4: 0x0003,
+            },
+            // when RXOUT_DIV = 4
+            CXP_SPEED::CXP_2 | CXP_SPEED::CXP_5 => CdrConfig {
+                cfg_reg0: 0x0020,
+                cfg_reg1: 0x1010,
+                cfg_reg2: 0x23FF,
+                cfg_reg3: 0x0000,
+                cfg_reg4: 0x0003,
+            },
+            // when RXOUT_DIV= 2
+            CXP_SPEED::CXP_3 | CXP_SPEED::CXP_6 => CdrConfig {
+                cfg_reg0: 0x0020,
+                cfg_reg1: 0x1020,
+                cfg_reg2: 0x23FF,
+                cfg_reg3: 0x0000,
+                cfg_reg4: 0x0003,
+            },
+            // when RXOUT_DIV= 1
+            CXP_SPEED::CXP_10 | CXP_SPEED::CXP_12 => CdrConfig {
+                cfg_reg0: 0x0020,
+                cfg_reg1: 0x1040,
+                cfg_reg2: 0x23FF,
+                cfg_reg3: 0x0000,
+                cfg_reg4: 0x000B,
+            },
+        };
+
+        for channel in 0..CXP_CHANNELS {
+            gtx_write(channel, 0x0A8, cdr_cfg.cfg_reg0);
+            gtx_write(channel, 0x0A9, cdr_cfg.cfg_reg1);
+            gtx_write(channel, 0x0AA, cdr_cfg.cfg_reg2);
+            gtx_write(channel, 0x0AB, cdr_cfg.cfg_reg3);
+            gtx_write(channel, 0x0AC, cdr_cfg.cfg_reg4);
+        }
+    }
+
+    #[allow(dead_code)]
+    fn gtx_read(channel: usize, address: u16) -> u16 {
+        unsafe {
+            (CXP[channel].downconn_gtx_daddr_write)(address);
+            (CXP[channel].downconn_gtx_dread_write)(1);
+            while (CXP[channel].downconn_gtx_dready_read)() != 1 {}
+            (CXP[channel].downconn_gtx_dout_read)()
+        }
+    }
+
+    fn gtx_write(channel: usize, address: u16, value: u16) {
+        unsafe {
+            (CXP[channel].downconn_gtx_daddr_write)(address);
+            (CXP[channel].downconn_gtx_din_write)(value);
+            (CXP[channel].downconn_gtx_din_stb_write)(1);
+            while (CXP[channel].downconn_gtx_dready_read)() != 1 {}
+        }
+    }
+
+    #[allow(dead_code)]
+    fn qpll_read(address: u8) -> u16 {
+        unsafe {
+            csr::cxp_phys::downconn_qpll_daddr_write(address);
+            csr::cxp_phys::downconn_qpll_dread_write(1);
+            while csr::cxp_phys::downconn_qpll_dready_read() != 1 {}
+            csr::cxp_phys::downconn_qpll_dout_read()
+        }
+    }
+
+    fn qpll_write(address: u8, value: u16) {
+        unsafe {
+            csr::cxp_phys::downconn_qpll_daddr_write(address);
+            csr::cxp_phys::downconn_qpll_din_write(value);
+            csr::cxp_phys::downconn_qpll_din_stb_write(1);
+            while csr::cxp_phys::downconn_qpll_dready_read() != 1 {}
+        }
+    }
+}

src/libboard_artiq/src/cxp_proto.rs

@@ -0,0 +1,398 @@
+use byteorder::{ByteOrder, NetworkEndian};
+use core_io::{Error as IoError, Read, Write};
+use crc::crc32::checksum_ieee;
+use io::Cursor;
+use libboard_zynq::println;
+
+const EV_MAXSIZE: usize = 253;
+pub const DATA_MAXSIZE: usize = 48;
+
+#[derive(Debug)]
+pub enum Error {
+    BufferError,
+    CorruptedPacket,
+    CtrlAckError(u8),
+    Io(IoError),
+    UnknownPacket(u8),
+}
+
+impl From<IoError> for Error {
+    fn from(value: IoError) -> Error {
+        Error::Io(value)
+    }
+}
+
+fn get_cxp_crc(bytes: &[u8]) -> u32 {
+    // Section 9.2.2.2 (CXP-001-2021)
+    // Only Control packet need CRC32 appended in the end of the packet
+    // CoaXpress use the polynomial of IEEE-802.3 (Ethernet) CRC but the checksum calculation is different
+    (!checksum_ieee(bytes)).swap_bytes()
+}
+
+trait CxpRead {
+    fn read_u8(&mut self) -> Result<u8, Error>;
+
+    fn read_u16(&mut self) -> Result<u16, Error>;
+
+    fn read_u32(&mut self) -> Result<u32, Error>;
+
+    fn read_u64(&mut self) -> Result<u64, Error>;
+
+    fn read_exact_4x(&mut self, buf: &mut [u8]) -> Result<(), Error>;
+
+    fn read_4x_u8(&mut self) -> Result<u8, Error>;
+
+    fn read_4x_u16(&mut self) -> Result<u16, Error>;
+
+    fn read_4x_u32(&mut self) -> Result<u32, Error>;
+
+    fn read_4x_u64(&mut self) -> Result<u64, Error>;
+}
+impl<Cursor: Read> CxpRead for Cursor {
+    fn read_u8(&mut self) -> Result<u8, Error> {
+        let mut bytes = [0; 1];
+        self.read_exact(&mut bytes)?;
+        Ok(bytes[0])
+    }
+
+    fn read_u16(&mut self) -> Result<u16, Error> {
+        let mut bytes = [0; 2];
+        self.read_exact(&mut bytes)?;
+        Ok(NetworkEndian::read_u16(&bytes))
+    }
+
+    fn read_u32(&mut self) -> Result<u32, Error> {
+        let mut bytes = [0; 4];
+        self.read_exact(&mut bytes)?;
+        Ok(NetworkEndian::read_u32(&bytes))
+    }
+
+    fn read_u64(&mut self) -> Result<u64, Error> {
+        let mut bytes = [0; 8];
+        self.read_exact(&mut bytes)?;
+        Ok(NetworkEndian::read_u64(&bytes))
+    }
+
+    fn read_exact_4x(&mut self, buf: &mut [u8]) -> Result<(), Error> {
+        for byte in buf {
+            // Section 9.2.2.1 (CXP-001-2021)
+            // decoder should immune to single bit errors when handling 4x duplicated characters
+            let a = self.read_u8()?;
+            let b = self.read_u8()?;
+            let c = self.read_u8()?;
+            let d = self.read_u8()?;
+            // vote and return majority
+            *byte = a & b & c | a & b & d | a & c & d | b & c & d;
+        }
+        Ok(())
+    }
+
+    fn read_4x_u8(&mut self) -> Result<u8, Error> {
+        let mut bytes = [0; 1];
+        self.read_exact_4x(&mut bytes)?;
+        Ok(bytes[0])
+    }
+
+    fn read_4x_u16(&mut self) -> Result<u16, Error> {
+        let mut bytes = [0; 2];
+        self.read_exact_4x(&mut bytes)?;
+        Ok(NetworkEndian::read_u16(&bytes))
+    }
+
+    fn read_4x_u32(&mut self) -> Result<u32, Error> {
+        let mut bytes = [0; 4];
+        self.read_exact_4x(&mut bytes)?;
+        Ok(NetworkEndian::read_u32(&bytes))
+    }
+
+    fn read_4x_u64(&mut self) -> Result<u64, Error> {
+        let mut bytes = [0; 6];
+        self.read_exact_4x(&mut bytes)?;
+        Ok(NetworkEndian::read_u64(&bytes))
+    }
+}
+
+#[derive(Debug)]
+pub enum NameSpace {
+    GenICam,
+    DeviceSpecific,
+}
+
+#[derive(Debug)]
+pub enum DownConnPacket {
+    CtrlReply {
+        tag: Option<u8>,
+        length: u32,
+        data: [u8; DATA_MAXSIZE],
+    },
+    CtrlDelay {
+        tag: Option<u8>,
+        time: u16, // max value of time is 10000
+    },
+    CtrlAck {
+        tag: Option<u8>,
+    },
+    Event {
+        conn_id: u32,
+        packet_tag: u8,
+        length: u16,
+        ev_size: u16,
+        namespace: NameSpace,
+        event_id: u16,
+        timestamp: u64,
+        ev: [u8; EV_MAXSIZE],
+    },
+}
+
+impl DownConnPacket {
+    pub fn read_from(reader: &mut Cursor<&mut [u8]>, packet_type: u8) -> Result<Self, Error> {
+        match packet_type {
+            0x03 => DownConnPacket::get_ctrl_packet(reader, false),
+            0x06 => DownConnPacket::get_ctrl_packet(reader, true),
+            0x07 => DownConnPacket::get_event_packet(reader),
+            _ => Err(Error::UnknownPacket(packet_type)),
+        }
+    }
+
+    fn get_ctrl_packet(reader: &mut Cursor<&mut [u8]>, with_tag: bool) -> Result<Self, Error> {
+        let mut tag: Option<u8> = None;
+        if with_tag {
+            tag = Some(reader.read_4x_u8()?);
+        }
+
+        let ackcode = reader.read_4x_u8()?;
+
+        match ackcode {
+            0x00 | 0x04 => {
+                let length = reader.read_u32()?;
+                let mut data: [u8; DATA_MAXSIZE] = [0; DATA_MAXSIZE];
+                reader.read(&mut data[0..length as usize])?;
+
+                let checksum = get_cxp_crc(&reader.get_ref()[0..reader.position()]);
+                if reader.read_u32()? != checksum {
+                    return Err(Error::CorruptedPacket);
+                }
+
+                if ackcode == 0x00 {
+                    return Ok(DownConnPacket::CtrlReply { tag, length, data });
+                } else {
+                    return Ok(DownConnPacket::CtrlDelay {
+                        tag,
+                        time: NetworkEndian::read_u16(&data[..2]),
+                    });
+                }
+            }
+            0x01 => return Ok(DownConnPacket::CtrlAck { tag }),
+            _ => return Err(Error::CtrlAckError(ackcode)),
+        }
+    }
+
+    fn get_event_packet(reader: &mut Cursor<&mut [u8]>) -> Result<Self, Error> {
+        let conn_id = reader.read_4x_u32()?;
+        let packet_tag = reader.read_4x_u8()?;
+        let length = reader.read_4x_u16()?;
+
+        let ev_size = reader.read_u16()?;
+        if ev_size + 3 != length {
+            println!("length mismatch");
+            return Err(Error::CorruptedPacket);
+        }
+
+        let mut bytes = [0; 2];
+        reader.read_exact(&mut bytes)?;
+        let namespace_bits = (bytes[0] & 0xC0) >> 6;
+        let namespace = match namespace_bits {
+            0 => NameSpace::GenICam,
+            2 => NameSpace::DeviceSpecific,
+            _ => {
+                println!("namespace = {} error", namespace_bits);
+                return Err(Error::CorruptedPacket);
+            }
+        };
+
+        let event_id = (bytes[0] & 0xF) as u16 | (bytes[1] as u16);
+
+        let timestamp = reader.read_u64()?;
+
+        let mut ev: [u8; EV_MAXSIZE] = [0; EV_MAXSIZE];
+        reader.read(&mut ev[0..ev_size as usize])?;
+
+        let checksum = get_cxp_crc(&reader.get_ref()[0..reader.position()]);
+        if reader.read_u32()? != checksum {
+            println!("crc error");
+            return Err(Error::CorruptedPacket);
+        }
+
+        Ok(DownConnPacket::Event {
+            conn_id,
+            packet_tag,
+            length,
+            ev_size,
+            namespace,
+            event_id,
+            timestamp,
+            ev,
+        })
+    }
+}
+
+trait CxpWrite {
+    fn write_all_4x(&mut self, buf: &[u8]) -> Result<(), Error>;
+
+    fn write_4x_u8(&mut self, value: u8) -> Result<(), Error>;
+
+    fn write_4x_u16(&mut self, value: u16) -> Result<(), Error>;
+
+    fn write_4x_u32(&mut self, value: u32) -> Result<(), Error>;
+
+    fn write_4x_u64(&mut self, value: u64) -> Result<(), Error>;
+
+    fn write_u32(&mut self, value: u32) -> Result<(), Error>;
+}
+impl<Cursor: Write> CxpWrite for Cursor {
+    fn write_all_4x(&mut self, buf: &[u8]) -> Result<(), Error> {
+        for byte in buf {
+            self.write_all(&[*byte; 4])?;
+        }
+        Ok(())
+    }
+
+    fn write_4x_u8(&mut self, value: u8) -> Result<(), Error> {
+        self.write_all_4x(&[value])
+    }
+
+    fn write_4x_u16(&mut self, value: u16) -> Result<(), Error> {
+        let mut bytes = [0; 2];
+        NetworkEndian::write_u16(&mut bytes, value);
+        self.write_all_4x(&bytes)
+    }
+
+    fn write_4x_u32(&mut self, value: u32) -> Result<(), Error> {
+        let mut bytes = [0; 4];
+        NetworkEndian::write_u32(&mut bytes, value);
+        self.write_all_4x(&bytes)
+    }
+
+    fn write_4x_u64(&mut self, value: u64) -> Result<(), Error> {
+        let mut bytes = [0; 6];
+        NetworkEndian::write_u64(&mut bytes, value);
+        self.write_all_4x(&bytes)
+    }
+
+    fn write_u32(&mut self, value: u32) -> Result<(), Error> {
+        let mut bytes = [0; 4];
+        NetworkEndian::write_u32(&mut bytes, value);
+        self.write_all(&bytes)?;
+        Ok(())
+    }
+}
+
+#[derive(Debug)]
+pub enum UpConnPacket {
+    CtrlRead {
+        tag: Option<u8>,
+        addr: u32,
+        length: u8,
+    },
+    CtrlWrite {
+        tag: Option<u8>,
+        addr: u32,
+        length: u8,
+        data: [u8; DATA_MAXSIZE],
+    }, // max register size is 8 bytes
+    EventAck {
+        packet_tag: u8,
+    },
+}
+
+impl UpConnPacket {
+    pub fn write_to(&self, writer: &mut Cursor<&mut [u8]>) -> Result<(), Error> {
+        match *self {
+            UpConnPacket::CtrlRead { tag, addr, length } => {
+                match tag {
+                    Some(t) => {
+                        writer.write_4x_u8(0x05)?;
+                        writer.write_4x_u8(t)?;
+                    }
+                    None => {
+                        writer.write_4x_u8(0x02)?;
+                    }
+                }
+                writer.write_all(&[0x00, 0x00, 0x00, length])?;
+                writer.write_u32(addr)?;
+
+                // Section 9.6.2 (CXP-001-2021)
+                // only bytes after the first 4 are used in calculating the checksum
+                let checksum = get_cxp_crc(&writer.get_ref()[4..writer.position()]);
+                writer.write_u32(checksum)?;
+            }
+            UpConnPacket::CtrlWrite {
+                tag,
+                addr,
+                length,
+                data,
+            } => {
+                match tag {
+                    Some(t) => {
+                        writer.write_4x_u8(0x05)?;
+                        writer.write_4x_u8(t)?;
+                    }
+                    None => {
+                        writer.write_4x_u8(0x02)?;
+                    }
+                }
+                writer.write_all(&[0x01, 0x00, 0x00, length])?;
+                writer.write_u32(addr)?;
+                writer.write_all(&data[0..length as usize])?;
+
+                // Section 9.6.2 (CXP-001-2021)
+                // only bytes after the first 4 are used in calculating the checksum
+                let checksum = get_cxp_crc(&writer.get_ref()[4..writer.position()]);
+                writer.write_u32(checksum)?;
+            }
+            UpConnPacket::EventAck { packet_tag } => {
+                writer.write_4x_u8(0x08)?;
+                writer.write_4x_u8(packet_tag)?;
+            }
+        }
+        Ok(())
+    }
+}
+
+// DEBUG: use only
+//
+//
+//
+pub fn print_packet(pak: &[u8]) {
+    println!("pak = [");
+    for i in 0..(pak.len() / 4) {
+        println!(
+            "{:#03}     {:#04X} {:#04X} {:#04X} {:#04X},",
+            i + 1,
+            pak[i * 4],
+            pak[i * 4 + 1],
+            pak[i * 4 + 2],
+            pak[i * 4 + 3]
+        )
+    }
+    println!("]");
+    println!("============================================");
+}
+
+pub fn print_packetu32(pak: &[u32], k: &[u8]) {
+    println!("pak = [");
+    for i in 0..(pak.len()) {
+        let data: [u8; 4] = pak[i].to_le_bytes();
+        println!(
+            "{:#03}     {:#04X} {:#04X} {:#04X} {:#04X} | K {:04b},",
+            i + 1,
+            data[0],
+            data[1],
+            data[2],
+            data[3],
+            k[i],
+        )
+    }
+    println!("]");
+    println!("============================================");
+}

src/libboard_artiq/src/cxp_upconn.rs

@@ -0,0 +1,42 @@
+use embedded_hal::prelude::_embedded_hal_blocking_delay_DelayUs;
+use libboard_zynq::timer::GlobalTimer;
+
+pub use crate::cxp_proto;
+use crate::pl::{csr, csr::CXP};
+
+pub fn tx_test(channel: usize, timer: &mut GlobalTimer) {
+    const LEN: usize = 4 * 30;
+    let mut pak_arr: [u8; LEN] = [0; LEN];
+
+    unsafe {
+        // cxp_proto::read_u32(channel, 0x00).expect("Cannot Write CoaXpress Register");
+        // cxp_proto::write_u64(channel, 0x00, 0x01);
+        // cxp_proto::send(channel, &cxp_proto::Packet::EventAck { packet_tag: 0x04 }).expect("Cannot send CoaXpress packet");
+        // cxp_proto::send(channel, &cxp_proto::Packet::TestPacket).expect("Cannot send CoaXpress packet");
+
+        timer.delay_us(2); // send one word
+        // DEBUG: Trigger packet
+        (CXP[channel].upconn_trig_delay_write)(0x86);
+        (CXP[channel].upconn_linktrigger_write)(0x00);
+        (CXP[channel].upconn_trig_stb_write)(1); // send trig
+
+        // DEBUG: Trigger ACK packet
+        // CXP[channel].upconn_ack_write(1);
+
+        timer.delay_us(20);
+        csr::cxp_phys::upconn_tx_enable_write(0);
+
+        // Collect data
+        let mut i: usize = 0;
+        while csr::cxp_phys::upconn_tx0_debug_buf_dout_valid_read() == 1 {
+            pak_arr[i] = csr::cxp_phys::upconn_tx0_debug_buf_dout_pak_read();
+            csr::cxp_phys::upconn_tx0_debug_buf_inc_write(1);
+            i += 1;
+            if i == LEN {
+                break;
+            }
+        }
+
+        cxp_proto::print_packet(&pak_arr);
+    }
+}

src/libboard_artiq/src/drtioaux_proto.rs

@@ -267,12 +267,14 @@ pub enum Packet {
         exception_src: u8,
     },
     SubkernelExceptionRequest {
+        source: u8,
         destination: u8,
     },
     SubkernelException {
+        destination: u8,
         last: bool,
         length: u16,
-        data: [u8; SAT_PAYLOAD_MAX_SIZE],
+        data: [u8; MASTER_PAYLOAD_MAX_SIZE],
     },
     SubkernelMessage {
         source: u8,
@@ -524,14 +526,17 @@ impl Packet {
                 exception_src: reader.read_u8()?,
             },
             0xc9 => Packet::SubkernelExceptionRequest {
+                source: reader.read_u8()?,
                 destination: reader.read_u8()?,
             },
             0xca => {
+                let destination = reader.read_u8()?;
                 let last = reader.read_bool()?;
                 let length = reader.read_u16()?;
-                let mut data: [u8; SAT_PAYLOAD_MAX_SIZE] = [0; SAT_PAYLOAD_MAX_SIZE];
+                let mut data: [u8; MASTER_PAYLOAD_MAX_SIZE] = [0; MASTER_PAYLOAD_MAX_SIZE];
                 reader.read_exact(&mut data[0..length as usize])?;
                 Packet::SubkernelException {
+                    destination: destination,
                     last: last,
                     length: length,
                     data: data,
@@ -896,12 +901,19 @@ impl Packet {
                 writer.write_bool(with_exception)?;
                 writer.write_u8(exception_src)?;
             }
-            Packet::SubkernelExceptionRequest { destination } => {
+            Packet::SubkernelExceptionRequest { source, destination } => {
                 writer.write_u8(0xc9)?;
+                writer.write_u8(source)?;
                 writer.write_u8(destination)?;
             }
-            Packet::SubkernelException { last, length, data } => {
+            Packet::SubkernelException {
+                destination,
+                last,
+                length,
+                data,
+            } => {
                 writer.write_u8(0xca)?;
+                writer.write_u8(destination)?;
                 writer.write_bool(last)?;
                 writer.write_u16(length)?;
                 writer.write_all(&data[0..length as usize])?;
@@ -943,6 +955,8 @@ impl Packet {
             Packet::SubkernelLoadRunReply { destination, .. } => Some(*destination),
             Packet::SubkernelMessage { destination, .. } => Some(*destination),
             Packet::SubkernelMessageAck { destination } => Some(*destination),
+            Packet::SubkernelExceptionRequest { destination, .. } => Some(*destination),
+            Packet::SubkernelException { destination, .. } => Some(*destination),
             Packet::DmaPlaybackStatus { destination, .. } => Some(*destination),
             Packet::SubkernelFinished { destination, .. } => Some(*destination),
             _ => None,

src/libboard_artiq/src/lib.rs

@@ -3,6 +3,7 @@
 #![feature(naked_functions)]
 #![feature(asm)]
 
+extern crate byteorder;
 extern crate core_io;
 extern crate crc;
 extern crate embedded_hal;
@@ -25,7 +26,7 @@ pub mod fiq;
 #[cfg(feature = "target_kasli_soc")]
 pub mod io_expander;
 pub mod logger;
-#[cfg(has_drtio)]
+#[cfg(any(has_drtio, has_cxp_phys))]
 #[rustfmt::skip]
 #[path = "../../../build/mem.rs"]
 pub mod mem;
@@ -42,6 +43,19 @@ pub mod si5324;
 pub mod si549;
 use core::{cmp, str};
 
+#[cfg(has_cxp_phys)]
+pub mod cxp_downconn;
+#[cfg(has_cxp_phys)]
+pub mod cxp_upconn;
+
+pub mod cxp_proto;
+
+pub mod cxp_phys;
+
+pub mod cxp;
+
+pub mod cxp_comms;
+
 pub fn identifier_read(buf: &mut [u8]) -> &str {
     unsafe {
         pl::csr::identifier::address_write(0);

src/libksupport/Cargo.toml.tpl

@@ -32,3 +32,9 @@ unwind = { path = "../libunwind" }
 libc = { path = "../libc" }
 io = { path = "../libio" }
 libboard_artiq = { path = "../libboard_artiq" }
+
+[dependencies.nalgebra]
+git = "https://git.m-labs.hk/M-Labs/nalgebra.git"
+rev = "dd00f9b"
+default-features = false
+features = ["libm", "alloc"]

src/libksupport/src/cxp.rs

@@ -0,0 +1,11 @@
+// use libboard_artiq::cxp_comms;
+
+// pub extern "C" fn cxp_readu32(channel: i32, addr: i32) {
+//     // TODO: use artiq_raise like i2c?
+//     cxp_comms::read_u32(channel as u8, addr as u32).expect("CXP transmission failed");
+// }
+
+// pub extern "C" fn cxp_writeu32(channel: i32, addr: i32, val: i32) {
+//     // TODO: use artiq_raise like i2c?
+//     cxp_comms::write_u32(channel as u8, addr as u32, val as u32).expect("CXP transmission failed");
+// }

src/libksupport/src/eh_artiq.rs

@@ -14,8 +14,10 @@
 
 use core::mem;
 
-use cslice::CSlice;
+use core_io::Error as ReadError;
+use cslice::{AsCSlice, CSlice};
 use dwarf::eh::{self, EHAction, EHContext};
+use io::{Cursor, ProtoRead};
 use libc::{c_int, c_void, uintptr_t};
 use log::{error, trace};
 use unwind as uw;
@@ -220,8 +222,6 @@ pub unsafe fn artiq_personality(
 }
 
 pub unsafe extern "C" fn raise(exception: *const Exception) -> ! {
-    use cslice::AsCSlice;
-
     let count = EXCEPTION_BUFFER.exception_count;
     let stack = &mut EXCEPTION_BUFFER.exception_stack;
     let diff = exception as isize - EXCEPTION_BUFFER.exceptions.as_ptr() as isize;
@@ -295,6 +295,60 @@ pub unsafe extern "C" fn raise(exception: *const Exception) -> ! {
     unreachable!();
 }
 
+fn read_exception_string<'a>(reader: &mut Cursor<&[u8]>) -> Result<CSlice<'a, u8>, ReadError> {
+    let len = reader.read_u32()? as usize;
+    if len == usize::MAX {
+        let data = reader.read_u32()?;
+        Ok(unsafe { CSlice::new(data as *const u8, len) })
+    } else {
+        let pos = reader.position();
+        let slice = unsafe {
+            let ptr = reader.get_ref().as_ptr().offset(pos as isize);
+            CSlice::new(ptr, len)
+        };
+        reader.set_position(pos + len);
+        Ok(slice)
+    }
+}
+
+fn read_exception(raw_exception: &[u8]) -> Result<Exception, ReadError> {
+    let mut reader = Cursor::new(raw_exception);
+
+    let mut byte = reader.read_u8()?;
+    // to sync
+    while byte != 0x5a {
+        byte = reader.read_u8()?;
+    }
+    // skip sync bytes, 0x09 indicates exception
+    while byte != 0x09 {
+        byte = reader.read_u8()?;
+    }
+    let _len = reader.read_u32()?;
+    // ignore the remaining exceptions, stack traces etc. - unwinding from another device would be unwise anyway
+    Ok(Exception {
+        id: reader.read_u32()?,
+        message: read_exception_string(&mut reader)?,
+        param: [
+            reader.read_u64()? as i64,
+            reader.read_u64()? as i64,
+            reader.read_u64()? as i64,
+        ],
+        file: read_exception_string(&mut reader)?,
+        line: reader.read_u32()?,
+        column: reader.read_u32()?,
+        function: read_exception_string(&mut reader)?,
+    })
+}
+
+pub fn raise_raw(raw_exception: &[u8]) -> ! {
+    use crate::artiq_raise;
+    if let Ok(exception) = read_exception(raw_exception) {
+        unsafe { raise(&exception) };
+    } else {
+        artiq_raise!("SubkernelError", "Error passing exception");
+    }
+}
+
 pub unsafe extern "C" fn resume() -> ! {
     trace!("resume");
     assert!(EXCEPTION_BUFFER.exception_count != 0);
@@ -421,20 +475,28 @@ extern "C" fn stop_fn(
     }
 }
 
-// Must be kept in sync with preallocate_runtime_exception_names() in artiq/language/embedding_map.py
-static EXCEPTION_ID_LOOKUP: [(&str, u32); 12] = [
-    ("RuntimeError", 0),
-    ("RTIOUnderflow", 1),
-    ("RTIOOverflow", 2),
-    ("RTIODestinationUnreachable", 3),
-    ("DMAError", 4),
-    ("I2CError", 5),
-    ("CacheError", 6),
-    ("SPIError", 7),
-    ("ZeroDivisionError", 8),
-    ("IndexError", 9),
-    ("UnwrapNoneError", 10),
-    ("SubkernelError", 11),
+// Must be kept in sync with preallocate_runtime_exception_names() in `artiq.compiler.embedding`
+static EXCEPTION_ID_LOOKUP: [(&str, u32); 20] = [
+    ("RTIOUnderflow", 0),
+    ("RTIOOverflow", 1),
+    ("RTIODestinationUnreachable", 2),
+    ("DMAError", 3),
+    ("I2CError", 4),
+    ("CacheError", 5),
+    ("SPIError", 6),
+    ("SubkernelError", 7),
+    ("AssertionError", 8),
+    ("AttributeError", 9),
+    ("IndexError", 10),
+    ("IOError", 11),
+    ("KeyError", 12),
+    ("NotImplementedError", 13),
+    ("OverflowError", 14),
+    ("RuntimeError", 15),
+    ("TimeoutError", 16),
+    ("TypeError", 17),
+    ("ValueError", 18),
+    ("ZeroDivisionError", 19),
 ];
 
 pub fn get_exception_id(name: &str) -> u32 {
@@ -469,3 +531,29 @@ macro_rules! artiq_raise {
     }};
     ($name:expr, $message:expr) => {{ artiq_raise!($name, $message, 0, 0, 0) }};
 }
+
+/// Takes as input exception id from host
+/// Generates a new exception with:
+///   * `id` set to `exn_id`
+///   * `message` set to corresponding exception name from `EXCEPTION_ID_LOOKUP`
+///
+/// The message is matched on host to ensure correct exception is being referred
+/// This test checks the synchronization of exception ids for runtime errors
+#[no_mangle]
+pub extern "C" fn test_exception_id_sync(exn_id: u32) {
+    let message = EXCEPTION_ID_LOOKUP
+        .iter()
+        .find_map(|&(name, id)| if id == exn_id { Some(name) } else { None })
+        .unwrap_or("unallocated internal exception id");
+
+    let exn = Exception {
+        id: exn_id,
+        file: file!().as_c_slice(),
+        line: 0,
+        column: 0,
+        function: "test_exception_id_sync".as_c_slice(),
+        message: message.as_c_slice(),
+        param: [0, 0, 0],
+    };
+    unsafe { raise(&exn) };
+}

src/libksupport/src/kernel/api.rs

@@ -9,8 +9,10 @@ use log::{info, warn};
 use super::subkernel;
 use super::{cache,
             core1::rtio_get_destination_status,
-            dma,
+            dma, linalg,
             rpc::{rpc_recv, rpc_send, rpc_send_async}};
+// #[cfg(has_cxp_phys)]
+// use crate::cxp;
 use crate::{eh_artiq, i2c, rtio};
 
 extern "C" {
@@ -126,6 +128,12 @@ pub fn resolve(required: &[u8]) -> Option<u32> {
         #[cfg(has_drtio)]
         api!(subkernel_await_message = subkernel::await_message),
 
+        // CoaXPress
+        // #[cfg(has_cxp_phys)]
+        // api!(cxp_readu32 = cxp::cxp_readu32),
+        // #[cfg(has_cxp_phys)]
+        // api!(cxp_writeu32 = cxp::cxp_writeu32),
+
         // Double-precision floating-point arithmetic helper functions
         // RTABI chapter 4.1.2, Table 2
         api!(__aeabi_dadd),
@@ -303,6 +311,7 @@ pub fn resolve(required: &[u8]) -> Option<u32> {
         api_libm_f64f64f64!(nextafter),
         api_libm_f64f64f64!(pow),
         api_libm_f64f64!(round),
+        api_libm_f64f64!(rint),
         api_libm_f64f64!(sin),
         api_libm_f64f64!(sinh),
         api_libm_f64f64!(sqrt),
@@ -318,6 +327,26 @@ pub fn resolve(required: &[u8]) -> Option<u32> {
             }
             api!(yn = yn)
         },
+
+        // linalg
+        api!(np_linalg_cholesky = linalg::np_linalg_cholesky),
+        api!(np_linalg_qr = linalg::np_linalg_qr),
+        api!(np_linalg_svd = linalg::np_linalg_svd),
+        api!(np_linalg_inv = linalg::np_linalg_inv),
+        api!(np_linalg_pinv = linalg::np_linalg_pinv),
+        api!(np_linalg_matrix_power = linalg::np_linalg_matrix_power),
+        api!(np_linalg_det = linalg::np_linalg_det),
+        api!(sp_linalg_lu = linalg::sp_linalg_lu),
+        api!(sp_linalg_schur = linalg::sp_linalg_schur),
+        api!(sp_linalg_hessenberg = linalg::sp_linalg_hessenberg),
+
+        /*
+         * syscall for unit tests
+         * Used in `artiq.tests.coredevice.test_exceptions.ExceptionTest.test_raise_exceptions_kernel`
+         * This syscall checks that the exception IDs used in the Python `EmbeddingMap` (in `artiq.language.embedding`)
+         * match the `EXCEPTION_ID_LOOKUP` defined in the firmware (`libksupport::src::eh_artiq`)
+         */
+        api!(test_exception_id_sync = eh_artiq::test_exception_id_sync)
     ];
     api.iter()
         .find(|&&(exported, _)| exported.as_bytes() == required)

src/libksupport/src/kernel/linalg.rs

@@ -0,0 +1,440 @@
+// Uses `nalgebra` crate to invoke `np_linalg` and `sp_linalg` functions
+// When converting between `nalgebra::Matrix` and `NDArray` following considerations are necessary
+//
+// * Both `nalgebra::Matrix` and `NDArray` require their content to be stored in row-major order
+// * `NDArray` data pointer can be directly read and converted to `nalgebra::Matrix` (row and column number must be known)
+// * `nalgebra::Matrix::as_slice` returns the content of matrix in column-major order and initial data needs to be transposed before storing it in `NDArray` data pointer
+
+use alloc::vec::Vec;
+use core::slice;
+
+use nalgebra::DMatrix;
+
+use crate::artiq_raise;
+
+pub struct InputMatrix {
+    pub ndims: usize,
+    pub dims: *const usize,
+    pub data: *mut f64,
+}
+
+impl InputMatrix {
+    fn get_dims(&mut self) -> Vec<usize> {
+        let dims = unsafe { slice::from_raw_parts(self.dims, self.ndims) };
+        dims.to_vec()
+    }
+}
+
+/// # Safety
+///
+/// `mat1` should point to a valid 2DArray of `f64` floats in row-major order
+#[no_mangle]
+pub unsafe extern "C" fn np_linalg_cholesky(mat1: *mut InputMatrix, out: *mut InputMatrix) {
+    let mat1 = mat1.as_mut().unwrap();
+    let out = out.as_mut().unwrap();
+
+    if mat1.ndims != 2 {
+        artiq_raise!(
+            "ValueError",
+            "expected 2D Vector Input, but received {1}D input)",
+            0,
+            mat1.ndims as i64,
+            0
+        );
+    }
+
+    let dim1 = (*mat1).get_dims();
+    if dim1[0] != dim1[1] {
+        artiq_raise!(
+            "ValueError",
+            "last 2 dimensions of the array must be square: {1} != {2}",
+            0,
+            dim1[0] as i64,
+            dim1[1] as i64
+        );
+    }
+
+    let outdim = out.get_dims();
+    let out_slice = slice::from_raw_parts_mut(out.data, outdim[0] * outdim[1]);
+    let data_slice1 = slice::from_raw_parts_mut(mat1.data, dim1[0] * dim1[1]);
+
+    let matrix1 = DMatrix::from_row_slice(dim1[0], dim1[1], data_slice1);
+    let result = matrix1.cholesky();
+    match result {
+        Some(res) => {
+            out_slice.copy_from_slice(res.unpack().transpose().as_slice());
+        }
+        None => {
+            artiq_raise!("LinAlgError", "Matrix is not positive definite");
+        }
+    };
+}
+
+/// # Safety
+///
+/// `mat1` should point to a valid 2DArray of `f64` floats in row-major order
+#[no_mangle]
+pub unsafe extern "C" fn np_linalg_qr(mat1: *mut InputMatrix, out_q: *mut InputMatrix, out_r: *mut InputMatrix) {
+    let mat1 = mat1.as_mut().unwrap();
+    let out_q = out_q.as_mut().unwrap();
+    let out_r = out_r.as_mut().unwrap();
+
+    if mat1.ndims != 2 {
+        artiq_raise!(
+            "ValueError",
+            "expected 2D Vector Input, but received {1}D input)",
+            0,
+            mat1.ndims as i64,
+            0
+        );
+    }
+
+    let dim1 = (*mat1).get_dims();
+    let outq_dim = (*out_q).get_dims();
+    let outr_dim = (*out_r).get_dims();
+
+    let data_slice1 = slice::from_raw_parts_mut(mat1.data, dim1[0] * dim1[1]);
+    let out_q_slice = slice::from_raw_parts_mut(out_q.data, outq_dim[0] * outq_dim[1]);
+    let out_r_slice = slice::from_raw_parts_mut(out_r.data, outr_dim[0] * outr_dim[1]);
+
+    // Refer to https://github.com/dimforge/nalgebra/issues/735
+    let matrix1 = DMatrix::from_row_slice(dim1[0], dim1[1], data_slice1);
+
+    let res = matrix1.qr();
+    let (q, r) = res.unpack();
+
+    // Uses different algo need to match numpy
+    out_q_slice.copy_from_slice(q.transpose().as_slice());
+    out_r_slice.copy_from_slice(r.transpose().as_slice());
+}
+
+/// # Safety
+///
+/// `mat1` should point to a valid 2DArray of `f64` floats in row-major order
+#[no_mangle]
+pub unsafe extern "C" fn np_linalg_svd(
+    mat1: *mut InputMatrix,
+    outu: *mut InputMatrix,
+    outs: *mut InputMatrix,
+    outvh: *mut InputMatrix,
+) {
+    let mat1 = mat1.as_mut().unwrap();
+    let outu = outu.as_mut().unwrap();
+    let outs = outs.as_mut().unwrap();
+    let outvh = outvh.as_mut().unwrap();
+
+    if mat1.ndims != 2 {
+        artiq_raise!(
+            "ValueError",
+            "expected 2D Vector Input, but received {1}D input)",
+            0,
+            mat1.ndims as i64,
+            0
+        );
+    }
+
+    let dim1 = (*mat1).get_dims();
+    let outu_dim = (*outu).get_dims();
+    let outs_dim = (*outs).get_dims();
+    let outvh_dim = (*outvh).get_dims();
+
+    let data_slice1 = slice::from_raw_parts_mut(mat1.data, dim1[0] * dim1[1]);
+    let out_u_slice = slice::from_raw_parts_mut(outu.data, outu_dim[0] * outu_dim[1]);
+    let out_s_slice = slice::from_raw_parts_mut(outs.data, outs_dim[0]);
+    let out_vh_slice = slice::from_raw_parts_mut(outvh.data, outvh_dim[0] * outvh_dim[1]);
+
+    let matrix = DMatrix::from_row_slice(dim1[0], dim1[1], data_slice1);
+    let result = matrix.svd(true, true);
+    out_u_slice.copy_from_slice(result.u.unwrap().transpose().as_slice());
+    out_s_slice.copy_from_slice(result.singular_values.as_slice());
+    out_vh_slice.copy_from_slice(result.v_t.unwrap().transpose().as_slice());
+}
+
+/// # Safety
+///
+/// `mat1` should point to a valid 2DArray of `f64` floats in row-major order
+#[no_mangle]
+pub unsafe extern "C" fn np_linalg_inv(mat1: *mut InputMatrix, out: *mut InputMatrix) {
+    let mat1 = mat1.as_mut().unwrap();
+    let out = out.as_mut().unwrap();
+
+    if mat1.ndims != 2 {
+        artiq_raise!(
+            "ValueError",
+            "expected 2D Vector Input, but received {1}D input)",
+            0,
+            mat1.ndims as i64,
+            0
+        );
+    }
+    let dim1 = (*mat1).get_dims();
+
+    if dim1[0] != dim1[1] {
+        artiq_raise!(
+            "ValueError",
+            "last 2 dimensions of the array must be square: {1} != {2}",
+            0,
+            dim1[0] as i64,
+            dim1[1] as i64
+        );
+    }
+
+    let outdim = out.get_dims();
+    let out_slice = slice::from_raw_parts_mut(out.data, outdim[0] * outdim[1]);
+    let data_slice1 = slice::from_raw_parts_mut(mat1.data, dim1[0] * dim1[1]);
+
+    let matrix = DMatrix::from_row_slice(dim1[0], dim1[1], data_slice1);
+    if !matrix.is_invertible() {
+        artiq_raise!("LinAlgError", "no inverse for Singular Matrix");
+    }
+    let inv = matrix.try_inverse().unwrap();
+    out_slice.copy_from_slice(inv.transpose().as_slice());
+}
+
+/// # Safety
+///
+/// `mat1` should point to a valid 2DArray of `f64` floats in row-major order
+#[no_mangle]
+pub unsafe extern "C" fn np_linalg_pinv(mat1: *mut InputMatrix, out: *mut InputMatrix) {
+    let mat1 = mat1.as_mut().unwrap();
+    let out = out.as_mut().unwrap();
+
+    if mat1.ndims != 2 {
+        artiq_raise!(
+            "ValueError",
+            "expected 2D Vector Input, but received {1}D input)",
+            0,
+            mat1.ndims as i64,
+            0
+        );
+    }
+    let dim1 = (*mat1).get_dims();
+    let outdim = out.get_dims();
+    let out_slice = slice::from_raw_parts_mut(out.data, outdim[0] * outdim[1]);
+    let data_slice1 = slice::from_raw_parts_mut(mat1.data, dim1[0] * dim1[1]);
+
+    let matrix = DMatrix::from_row_slice(dim1[0], dim1[1], data_slice1);
+    let svd = matrix.svd(true, true);
+    let inv = svd.pseudo_inverse(1e-15);
+
+    match inv {
+        Ok(m) => {
+            out_slice.copy_from_slice(m.transpose().as_slice());
+        }
+        Err(_) => {
+            artiq_raise!("LinAlgError", "SVD computation does not converge");
+        }
+    }
+}
+
+/// # Safety
+///
+/// `mat1` should point to a valid 2DArray of `f64` floats in row-major order
+#[no_mangle]
+pub unsafe extern "C" fn np_linalg_matrix_power(mat1: *mut InputMatrix, mat2: *mut InputMatrix, out: *mut InputMatrix) {
+    let mat1 = mat1.as_mut().unwrap();
+    let mat2 = mat2.as_mut().unwrap();
+    let out = out.as_mut().unwrap();
+
+    if mat1.ndims != 2 {
+        artiq_raise!(
+            "ValueError",
+            "expected 2D Vector Input, but received {1}D input)",
+            0,
+            mat1.ndims as i64,
+            0
+        );
+    }
+
+    let dim1 = (*mat1).get_dims();
+    let power = slice::from_raw_parts_mut(mat2.data, 1);
+    let power = power[0];
+    let outdim = out.get_dims();
+    let out_slice = slice::from_raw_parts_mut(out.data, outdim[0] * outdim[1]);
+    let data_slice1 = slice::from_raw_parts_mut(mat1.data, dim1[0] * dim1[1]);
+    let mut abs_power = power;
+    if abs_power < 0.0 {
+        abs_power = abs_power * -1.0;
+    }
+    let matrix1 = DMatrix::from_row_slice(dim1[0], dim1[1], data_slice1);
+    if !matrix1.is_square() {
+        artiq_raise!(
+            "ValueError",
+            "last 2 dimensions of the array must be square: {1} != {2}",
+            0,
+            dim1[0] as i64,
+            dim1[1] as i64
+        );
+    }
+    let mut result = matrix1.pow(abs_power as u32);
+
+    if power < 0.0 {
+        if !matrix1.is_invertible() {
+            artiq_raise!("LinAlgError", "no inverse for Singular Matrix");
+        }
+        result = result.try_inverse().unwrap();
+    }
+    out_slice.copy_from_slice(result.transpose().as_slice());
+}
+
+/// # Safety
+///
+/// `mat1` should point to a valid 2DArray of `f64` floats in row-major order
+#[no_mangle]
+pub unsafe extern "C" fn np_linalg_det(mat1: *mut InputMatrix, out: *mut InputMatrix) {
+    let mat1 = mat1.as_mut().unwrap();
+    let out = out.as_mut().unwrap();
+
+    if mat1.ndims != 2 {
+        artiq_raise!(
+            "ValueError",
+            "expected 2D Vector Input, but received {1}D input)",
+            0,
+            mat1.ndims as i64,
+            0
+        );
+    }
+    let dim1 = (*mat1).get_dims();
+    let out_slice = slice::from_raw_parts_mut(out.data, 1);
+    let data_slice1 = slice::from_raw_parts_mut(mat1.data, dim1[0] * dim1[1]);
+
+    let matrix = DMatrix::from_row_slice(dim1[0], dim1[1], data_slice1);
+    if !matrix.is_square() {
+        artiq_raise!(
+            "ValueError",
+            "last 2 dimensions of the array must be square: {1} != {2}",
+            0,
+            dim1[0] as i64,
+            dim1[1] as i64
+        );
+    }
+    out_slice[0] = matrix.determinant();
+}
+
+/// # Safety
+///
+/// `mat1` should point to a valid 2DArray of `f64` floats in row-major order
+#[no_mangle]
+pub unsafe extern "C" fn sp_linalg_lu(mat1: *mut InputMatrix, out_l: *mut InputMatrix, out_u: *mut InputMatrix) {
+    let mat1 = mat1.as_mut().unwrap();
+    let out_l = out_l.as_mut().unwrap();
+    let out_u = out_u.as_mut().unwrap();
+
+    if mat1.ndims != 2 {
+        artiq_raise!(
+            "ValueError",
+            "expected 2D Vector Input, but received {1}D input)",
+            0,
+            mat1.ndims as i64,
+            0
+        );
+    }
+
+    let dim1 = (*mat1).get_dims();
+    let outl_dim = (*out_l).get_dims();
+    let outu_dim = (*out_u).get_dims();
+
+    let data_slice1 = slice::from_raw_parts_mut(mat1.data, dim1[0] * dim1[1]);
+    let out_l_slice = slice::from_raw_parts_mut(out_l.data, outl_dim[0] * outl_dim[1]);
+    let out_u_slice = slice::from_raw_parts_mut(out_u.data, outu_dim[0] * outu_dim[1]);
+
+    let matrix = DMatrix::from_row_slice(dim1[0], dim1[1], data_slice1);
+    let (_, l, u) = matrix.lu().unpack();
+
+    out_l_slice.copy_from_slice(l.transpose().as_slice());
+    out_u_slice.copy_from_slice(u.transpose().as_slice());
+}
+
+/// # Safety
+///
+/// `mat1` should point to a valid 2DArray of `f64` floats in row-major order
+#[no_mangle]
+pub unsafe extern "C" fn sp_linalg_schur(mat1: *mut InputMatrix, out_t: *mut InputMatrix, out_z: *mut InputMatrix) {
+    let mat1 = mat1.as_mut().unwrap();
+    let out_t = out_t.as_mut().unwrap();
+    let out_z = out_z.as_mut().unwrap();
+
+    if mat1.ndims != 2 {
+        artiq_raise!(
+            "ValueError",
+            "expected 2D Vector Input, but received {1}D input)",
+            0,
+            mat1.ndims as i64,
+            0
+        );
+    }
+
+    let dim1 = (*mat1).get_dims();
+
+    if dim1[0] != dim1[1] {
+        artiq_raise!(
+            "ValueError",
+            "last 2 dimensions of the array must be square: {1} != {2}",
+            0,
+            dim1[0] as i64,
+            dim1[1] as i64
+        );
+    }
+
+    let out_t_dim = (*out_t).get_dims();
+    let out_z_dim = (*out_z).get_dims();
+
+    let data_slice1 = slice::from_raw_parts_mut(mat1.data, dim1[0] * dim1[1]);
+    let out_t_slice = slice::from_raw_parts_mut(out_t.data, out_t_dim[0] * out_t_dim[1]);
+    let out_z_slice = slice::from_raw_parts_mut(out_z.data, out_z_dim[0] * out_z_dim[1]);
+
+    let matrix = DMatrix::from_row_slice(dim1[0], dim1[1], data_slice1);
+    let (z, t) = matrix.schur().unpack();
+
+    out_t_slice.copy_from_slice(t.transpose().as_slice());
+    out_z_slice.copy_from_slice(z.transpose().as_slice());
+}
+
+/// # Safety
+///
+/// `mat1` should point to a valid 2DArray of `f64` floats in row-major order
+#[no_mangle]
+pub unsafe extern "C" fn sp_linalg_hessenberg(
+    mat1: *mut InputMatrix,
+    out_h: *mut InputMatrix,
+    out_q: *mut InputMatrix,
+) {
+    let mat1 = mat1.as_mut().unwrap();
+    let out_h = out_h.as_mut().unwrap();
+    let out_q = out_q.as_mut().unwrap();
+
+    if mat1.ndims != 2 {
+        artiq_raise!(
+            "ValueError",
+            "expected 2D Vector Input, but received {1}D input)",
+            0,
+            mat1.ndims as i64,
+            0
+        );
+    }
+
+    let dim1 = (*mat1).get_dims();
+
+    if dim1[0] != dim1[1] {
+        artiq_raise!(
+            "ValueError",
+            "last 2 dimensions of the array must be square: {1} != {2}",
+            0,
+            dim1[0] as i64,
+            dim1[1] as i64
+        );
+    }
+
+    let out_h_dim = (*out_h).get_dims();
+    let out_q_dim = (*out_q).get_dims();
+
+    let data_slice1 = slice::from_raw_parts_mut(mat1.data, dim1[0] * dim1[1]);
+    let out_h_slice = slice::from_raw_parts_mut(out_h.data, out_h_dim[0] * out_h_dim[1]);
+    let out_q_slice = slice::from_raw_parts_mut(out_q.data, out_q_dim[0] * out_q_dim[1]);
+
+    let matrix = DMatrix::from_row_slice(dim1[0], dim1[1], data_slice1);
+    let (q, h) = matrix.hessenberg().unpack();
+
+    out_h_slice.copy_from_slice(h.transpose().as_slice());
+    out_q_slice.copy_from_slice(q.transpose().as_slice());
+}

src/libksupport/src/kernel/mod.rs

@@ -13,6 +13,7 @@ mod dma;
 mod rpc;
 pub use dma::DmaRecorder;
 mod cache;
+mod linalg;
 #[cfg(has_drtio)]
 mod subkernel;
 
@@ -23,6 +24,7 @@ pub enum SubkernelStatus {
     Timeout,
     IncorrectState,
     CommLost,
+    Exception(Vec<u8>),
     OtherError,
 }
 
@@ -90,9 +92,7 @@ pub enum Message {
         timeout: i64,
     },
     #[cfg(has_drtio)]
-    SubkernelAwaitFinishReply {
-        status: SubkernelStatus,
-    },
+    SubkernelAwaitFinishReply,
     #[cfg(has_drtio)]
     SubkernelMsgSend {
         id: u32,
@@ -109,9 +109,10 @@ pub enum Message {
     },
     #[cfg(has_drtio)]
     SubkernelMsgRecvReply {
-        status: SubkernelStatus,
         count: u8,
     },
+    #[cfg(has_drtio)]
+    SubkernelError(SubkernelStatus),
 }
 
 static CHANNEL_0TO1: Mutex<Option<sync_channel::Sender<'static, Message>>> = Mutex::new(None);

src/libksupport/src/kernel/subkernel.rs

@@ -3,7 +3,7 @@ use alloc::vec::Vec;
 use cslice::CSlice;
 
 use super::{Message, SubkernelStatus, KERNEL_CHANNEL_0TO1, KERNEL_CHANNEL_1TO0};
-use crate::{artiq_raise, rpc::send_args};
+use crate::{artiq_raise, eh_artiq, rpc::send_args};
 
 pub extern "C" fn load_run(id: u32, destination: u8, run: bool) {
     unsafe {
@@ -36,21 +36,18 @@ pub extern "C" fn await_finish(id: u32, timeout: i64) {
             });
     }
     match unsafe { KERNEL_CHANNEL_0TO1.as_mut().unwrap() }.recv() {
-        Message::SubkernelAwaitFinishReply {
-            status: SubkernelStatus::NoError,
-        } => (),
-        Message::SubkernelAwaitFinishReply {
-            status: SubkernelStatus::IncorrectState,
-        } => artiq_raise!("SubkernelError", "Subkernel not running"),
-        Message::SubkernelAwaitFinishReply {
-            status: SubkernelStatus::Timeout,
-        } => artiq_raise!("SubkernelError", "Subkernel timed out"),
-        Message::SubkernelAwaitFinishReply {
-            status: SubkernelStatus::CommLost,
-        } => artiq_raise!("SubkernelError", "Lost communication with satellite"),
-        Message::SubkernelAwaitFinishReply {
-            status: SubkernelStatus::OtherError,
-        } => artiq_raise!("SubkernelError", "An error occurred during subkernel operation"),
+        Message::SubkernelAwaitFinishReply => (),
+        Message::SubkernelError(SubkernelStatus::IncorrectState) => {
+            artiq_raise!("SubkernelError", "Subkernel not running")
+        }
+        Message::SubkernelError(SubkernelStatus::Timeout) => artiq_raise!("SubkernelError", "Subkernel timed out"),
+        Message::SubkernelError(SubkernelStatus::CommLost) => {
+            artiq_raise!("SubkernelError", "Lost communication with satellite")
+        }
+        Message::SubkernelError(SubkernelStatus::OtherError) => {
+            artiq_raise!("SubkernelError", "An error occurred during subkernel operation")
+        }
+        Message::SubkernelError(SubkernelStatus::Exception(raw_exception)) => eh_artiq::raise_raw(&raw_exception),
         _ => panic!("expected SubkernelAwaitFinishReply after SubkernelAwaitFinishRequest"),
     }
 }
@@ -92,30 +89,22 @@ pub extern "C" fn await_message(id: i32, timeout: i64, tags: &CSlice<u8>, min: u
             });
     }
     match unsafe { KERNEL_CHANNEL_0TO1.as_mut().unwrap() }.recv() {
-        Message::SubkernelMsgRecvReply {
-            status: SubkernelStatus::NoError,
-            count,
-        } => {
+        Message::SubkernelMsgRecvReply { count } => {
             if min > count || count > max {
                 artiq_raise!("SubkernelError", "Received more or less arguments than required")
             }
         }
-        Message::SubkernelMsgRecvReply {
-            status: SubkernelStatus::IncorrectState,
-            ..
-        } => artiq_raise!("SubkernelError", "Subkernel not running"),
-        Message::SubkernelMsgRecvReply {
-            status: SubkernelStatus::Timeout,
-            ..
-        } => artiq_raise!("SubkernelError", "Subkernel timed out"),
-        Message::SubkernelMsgRecvReply {
-            status: SubkernelStatus::CommLost,
-            ..
-        } => artiq_raise!("SubkernelError", "Lost communication with satellite"),
-        Message::SubkernelMsgRecvReply {
-            status: SubkernelStatus::OtherError,
-            ..
-        } => artiq_raise!("SubkernelError", "An error occurred during subkernel operation"),
+        Message::SubkernelError(SubkernelStatus::IncorrectState) => {
+            artiq_raise!("SubkernelError", "Subkernel not running")
+        }
+        Message::SubkernelError(SubkernelStatus::Timeout) => artiq_raise!("SubkernelError", "Subkernel timed out"),
+        Message::SubkernelError(SubkernelStatus::CommLost) => {
+            artiq_raise!("SubkernelError", "Lost communication with satellite")
+        }
+        Message::SubkernelError(SubkernelStatus::OtherError) => {
+            artiq_raise!("SubkernelError", "An error occurred during subkernel operation")
+        }
+        Message::SubkernelError(SubkernelStatus::Exception(raw_exception)) => eh_artiq::raise_raw(&raw_exception),
         _ => panic!("expected SubkernelMsgRecvReply after SubkernelMsgRecvRequest"),
     }
     // RpcRecvRequest should be called after this to receive message data

src/libksupport/src/lib.rs

@@ -35,6 +35,8 @@ pub mod rtio;
 #[path = "../../../build/pl.rs"]
 pub mod pl;
 
+#[cfg(has_cxp_phys)]
+pub mod cxp;
 
 #[derive(Debug, Clone)]
 pub struct RPCException {

src/libunwind/build.rs

@@ -23,6 +23,7 @@ mod llvm_libunwind {
         cfg.flag("--target=armv7-none-eabihf");
         cfg.flag("-O2");
         cfg.flag("-flto");
+        cfg.flag("-Wno-everything");
 
         cfg.flag("-std=c99");
         cfg.flag("-fstrict-aliasing");

src/runtime/src/comms.rs

@@ -422,33 +422,23 @@ async fn handle_run_kernel(
             #[cfg(has_drtio)]
             kernel::Message::SubkernelAwaitFinishRequest { id, timeout } => {
                 let res = subkernel::await_finish(aux_mutex, routing_table, timer, id, timeout).await;
-                let status = match res {
-                    Ok(ref res) => {
+                let response = match res {
+                    Ok(res) => {
                         if res.status == subkernel::FinishStatus::CommLost {
-                            kernel::SubkernelStatus::CommLost
-                        } else if let Some(exception) = &res.exception {
-                            error!("Exception in subkernel");
-                            match stream {
-                                None => (),
-                                Some(stream) => {
-                                    write_chunk(stream, exception).await?;
-                                }
-                            }
-                            // will not be called after exception is served
-                            kernel::SubkernelStatus::OtherError
+                            kernel::Message::SubkernelError(kernel::SubkernelStatus::CommLost)
+                        } else if let Some(exception) = res.exception {
+                            kernel::Message::SubkernelError(kernel::SubkernelStatus::Exception(exception))
                         } else {
-                            kernel::SubkernelStatus::NoError
+                            kernel::Message::SubkernelAwaitFinishReply
                         }
                     }
-                    Err(SubkernelError::Timeout) => kernel::SubkernelStatus::Timeout,
-                    Err(SubkernelError::IncorrectState) => kernel::SubkernelStatus::IncorrectState,
-                    Err(_) => kernel::SubkernelStatus::OtherError,
+                    Err(SubkernelError::Timeout) => kernel::Message::SubkernelError(kernel::SubkernelStatus::Timeout),
+                    Err(SubkernelError::IncorrectState) => {
+                        kernel::Message::SubkernelError(kernel::SubkernelStatus::IncorrectState)
+                    }
+                    Err(_) => kernel::Message::SubkernelError(kernel::SubkernelStatus::OtherError),
                 };
-                control
-                    .borrow_mut()
-                    .tx
-                    .async_send(kernel::Message::SubkernelAwaitFinishReply { status: status })
-                    .await;
+                control.borrow_mut().tx.async_send(response).await;
             }
             #[cfg(has_drtio)]
             kernel::Message::SubkernelMsgSend { id, destination, data } => {
@@ -469,35 +459,23 @@ async fn handle_run_kernel(
             #[cfg(has_drtio)]
             kernel::Message::SubkernelMsgRecvRequest { id, timeout, tags } => {
                 let message_received = subkernel::message_await(id as u32, timeout, timer).await;
-                let (status, count) = match message_received {
-                    Ok(ref message) => (kernel::SubkernelStatus::NoError, message.count),
-                    Err(SubkernelError::Timeout) => (kernel::SubkernelStatus::Timeout, 0),
-                    Err(SubkernelError::IncorrectState) => (kernel::SubkernelStatus::IncorrectState, 0),
-                    Err(SubkernelError::CommLost) => (kernel::SubkernelStatus::CommLost, 0),
+                let response = match message_received {
+                    Ok(ref message) => kernel::Message::SubkernelMsgRecvReply { count: message.count },
+                    Err(SubkernelError::Timeout) => kernel::Message::SubkernelError(kernel::SubkernelStatus::Timeout),
+                    Err(SubkernelError::IncorrectState) => {
+                        kernel::Message::SubkernelError(kernel::SubkernelStatus::IncorrectState)
+                    }
+                    Err(SubkernelError::CommLost) => kernel::Message::SubkernelError(kernel::SubkernelStatus::CommLost),
                     Err(SubkernelError::SubkernelException) => {
-                        error!("Exception in subkernel");
                         // just retrieve the exception
                         let status = subkernel::await_finish(aux_mutex, routing_table, timer, id as u32, timeout)
                             .await
                             .unwrap();
-                        match stream {
-                            None => (),
-                            Some(stream) => {
-                                write_chunk(stream, &status.exception.unwrap()).await?;
-                            }
-                        }
-                        (kernel::SubkernelStatus::OtherError, 0)
+                        kernel::Message::SubkernelError(kernel::SubkernelStatus::Exception(status.exception.unwrap()))
                     }
-                    Err(_) => (kernel::SubkernelStatus::OtherError, 0),
+                    Err(_) => kernel::Message::SubkernelError(kernel::SubkernelStatus::OtherError),
                 };
-                control
-                    .borrow_mut()
-                    .tx
-                    .async_send(kernel::Message::SubkernelMsgRecvReply {
-                        status: status,
-                        count: count,
-                    })
-                    .await;
+                control.borrow_mut().tx.async_send(response).await;
                 if let Ok(message) = message_received {
                     // receive code almost identical to RPC recv, except we are not reading from a stream
                     let mut reader = Cursor::new(message.data);
@@ -529,7 +507,7 @@ async fn handle_run_kernel(
                             .async_send(kernel::Message::RpcRecvReply(Ok(0)))
                             .await;
                         i += 1;
-                        if i < count {
+                        if i < message.count {
                             current_tags = remaining_tags;
                         } else {
                             break;
@@ -718,6 +696,27 @@ async fn handle_connection(
     }
 }
 
+async fn load_and_run_idle_kernel(
+    buffer: &Vec<u8>,
+    control: &Rc<RefCell<kernel::Control>>,
+    up_destinations: &Rc<RefCell<[bool; drtio_routing::DEST_COUNT]>>,
+    aux_mutex: &Rc<Mutex<bool>>,
+    routing_table: &drtio_routing::RoutingTable,
+    timer: GlobalTimer,
+) {
+    info!("Loading idle kernel");
+    let res = handle_flash_kernel(buffer, control, up_destinations, aux_mutex, routing_table, timer).await;
+    match res {
+        Err(_) => warn!("error loading idle kernel"),
+        _ => (),
+    }
+    info!("Running idle kernel");
+    let _ = handle_run_kernel(None, control, up_destinations, aux_mutex, routing_table, timer)
+        .await
+        .map_err(|_| warn!("error running idle kernel"));
+    info!("Idle kernel terminated");
+}
+
 pub fn main(timer: GlobalTimer, cfg: Config) {
     let net_addresses = net_settings::get_addresses(&cfg);
     info!("network addresses: {}", net_addresses);
@@ -771,7 +770,7 @@ pub fn main(timer: GlobalTimer, cfg: Config) {
     #[cfg(has_drtio_routing)]
     drtio_routing::interconnect_disable_all();
 
-    rtio_mgt::startup(&aux_mutex, &drtio_routing_table, &up_destinations, timer);
+    rtio_mgt::startup(&aux_mutex, &drtio_routing_table, &up_destinations, &cfg, timer);
     ksupport::setup_device_map(&cfg);
 
     analyzer::start(&aux_mutex, &drtio_routing_table, &up_destinations, timer);
@@ -808,8 +807,30 @@ pub fn main(timer: GlobalTimer, cfg: Config) {
     mgmt::start(cfg);
 
     task::spawn(async move {
-        let connection = Rc::new(Semaphore::new(1, 1));
+        let connection = Rc::new(Semaphore::new(0, 1));
         let terminate = Rc::new(Semaphore::new(0, 1));
+        {
+            let control = control.clone();
+            let idle_kernel = idle_kernel.clone();
+            let connection = connection.clone();
+            let terminate = terminate.clone();
+            let up_destinations = up_destinations.clone();
+            let aux_mutex = aux_mutex.clone();
+            let routing_table = drtio_routing_table.clone();
+            task::spawn(async move {
+                let routing_table = routing_table.borrow();
+                select_biased! {
+                    _ = (async {
+                        if let Some(buffer) = &*idle_kernel {
+                            load_and_run_idle_kernel(&buffer, &control, &up_destinations, &aux_mutex, &routing_table, timer).await;
+                        }
+                    }).fuse() => (),
+                    _ = terminate.async_wait().fuse() => ()
+                }
+                connection.signal();
+            });
+        }
+
         loop {
             let mut stream = TcpStream::accept(1381, 0x10_000, 0x10_000).await.unwrap();
 
@@ -837,22 +858,7 @@ pub fn main(timer: GlobalTimer, cfg: Config) {
                             .await
                             .map_err(|e| warn!("connection terminated: {}", e));
                         if let Some(buffer) = &*idle_kernel {
-                            info!("Loading idle kernel");
-                            let res = handle_flash_kernel(&buffer, &control, &up_destinations,  &aux_mutex, &routing_table, timer)
-                                .await;
-                            match res {
-                                #[cfg(has_drtio)]
-                                Err(Error::DestinationDown) => {
-                                    let mut countdown = timer.countdown();
-                                    delay(&mut countdown, Milliseconds(500)).await;
-                                }
-                                Err(_) => warn!("error loading idle kernel"),
-                                _ => (),
-                            }
-                            info!("Running idle kernel");
-                            let _ = handle_run_kernel(None, &control, &up_destinations, &aux_mutex, &routing_table, timer)
-                                .await.map_err(|_| warn!("error running idle kernel"));
-                            info!("Idle kernel terminated");
+                            load_and_run_idle_kernel(&buffer, &control, &up_destinations, &aux_mutex, &routing_table, timer).await;
                         }
                     }).fuse() => (),
                     _ = terminate.async_wait().fuse() => ()

src/runtime/src/main.rs

@@ -17,7 +17,7 @@ use libasync::task;
 use libboard_artiq::drtio_eem;
 #[cfg(feature = "target_kasli_soc")]
 use libboard_artiq::io_expander;
-use libboard_artiq::{identifier_read, logger, pl};
+use libboard_artiq::{cxp, identifier_read, logger, pl};
 use libboard_zynq::{gic, mpcore, timer::GlobalTimer};
 use libconfig::Config;
 use libcortex_a9::l2c::enable_l2_cache;
@@ -150,5 +150,7 @@ pub fn main_core0() {
 
     task::spawn(ksupport::report_async_rtio_errors());
 
+    cxp::setup(&mut timer);
+
     comms::main(timer, cfg);
 }

src/runtime/src/rtio_mgt.rs

@@ -3,7 +3,9 @@ use core::cell::RefCell;
 
 use libboard_artiq::{drtio_routing, drtio_routing::RoutingTable, pl::csr};
 use libboard_zynq::timer::GlobalTimer;
+use libconfig::Config;
 use libcortex_a9::mutex::Mutex;
+use log::{info, warn};
 
 #[cfg(has_drtio)]
 pub mod drtio {
@@ -127,6 +129,8 @@ pub mod drtio {
             | Packet::SubkernelLoadRunReply { destination, .. }
             | Packet::SubkernelMessage { destination, .. }
             | Packet::SubkernelMessageAck { destination, .. }
+            | Packet::SubkernelException { destination, .. }
+            | Packet::SubkernelExceptionRequest { destination, .. }
             | Packet::DmaPlaybackStatus { destination, .. }
             | Packet::SubkernelFinished { destination, .. } => {
                 if destination == 0 {
@@ -181,10 +185,7 @@ pub mod drtio {
 
     async fn drain_buffer(linkno: u8, draining_time: Milliseconds, timer: GlobalTimer) {
         let max_time = timer.get_time() + draining_time;
-        loop {
-            if timer.get_time() > max_time {
-                return;
-            }
+        while timer.get_time() < max_time {
             let _ = drtioaux_async::recv(linkno).await;
         }
     }
@@ -833,13 +834,19 @@ pub mod drtio {
                 linkno,
                 routing_table,
                 &Packet::SubkernelExceptionRequest {
+                    source: 0,
                     destination: destination,
                 },
                 timer,
             )
             .await?;
             match reply {
-                Packet::SubkernelException { last, length, data } => {
+                Packet::SubkernelException {
+                    destination: 0,
+                    last,
+                    length,
+                    data,
+                } => {
                     remote_data.extend(&data[0..length as usize]);
                     if last {
                         return Ok(remote_data);
@@ -898,12 +905,36 @@ pub mod drtio {
     pub fn reset(_aux_mutex: Rc<Mutex<bool>>, _routing_table: &RoutingTable, mut _timer: GlobalTimer) {}
 }
 
+fn toggle_sed_spread(val: u8) {
+    unsafe {
+        csr::rtio_core::sed_spread_enable_write(val);
+    }
+}
+
+fn setup_sed_spread(cfg: &Config) {
+    if let Ok(spread_enable) = cfg.read_str("sed_spread_enable") {
+        match spread_enable.as_ref() {
+            "1" => toggle_sed_spread(1),
+            "0" => toggle_sed_spread(0),
+            _ => {
+                warn!("sed_spread_enable value not supported (only 1, 0 allowed), disabling by default");
+                toggle_sed_spread(0)
+            }
+        };
+    } else {
+        info!("SED spreading disabled by default");
+        toggle_sed_spread(0);
+    }
+}
+
 pub fn startup(
     aux_mutex: &Rc<Mutex<bool>>,
     routing_table: &Rc<RefCell<RoutingTable>>,
     up_destinations: &Rc<RefCell<[bool; drtio_routing::DEST_COUNT]>>,
+    cfg: &Config,
     timer: GlobalTimer,
 ) {
+    setup_sed_spread(cfg);
     drtio::startup(aux_mutex, routing_table, up_destinations, timer);
     unsafe {
         csr::rtio_core::reset_phy_write(1);

src/satman/src/main.rs

@@ -12,6 +12,7 @@ extern crate io;
 extern crate ksupport;
 extern crate libboard_artiq;
 extern crate libboard_zynq;
+extern crate libconfig;
 extern crate libcortex_a9;
 extern crate libregister;
 extern crate libsupport_zynq;
@@ -38,6 +39,7 @@ use libboard_artiq::{drtio_routing, drtioaux,
 #[cfg(feature = "target_kasli_soc")]
 use libboard_zynq::error_led::ErrorLED;
 use libboard_zynq::{i2c::I2c, print, println, time::Milliseconds, timer::GlobalTimer};
+use libconfig::Config;
 use libcortex_a9::{l2c::enable_l2_cache, regs::MPIDR};
 use libregister::RegisterR;
 use libsupport_zynq::{exception_vectors, ram};
@@ -81,15 +83,37 @@ fn drtiosat_tsc_loaded() -> bool {
     }
 }
 
+fn toggle_sed_spread(val: u8) {
+    unsafe {
+        csr::drtiosat::sed_spread_enable_write(val);
+    }
+}
+
 #[cfg(has_drtio_routing)]
 macro_rules! forward {
-    ($routing_table:expr, $destination:expr, $rank:expr, $repeaters:expr, $packet:expr, $timer:expr) => {{
+    (
+        $router:expr,
+        $routing_table:expr,
+        $destination:expr,
+        $rank:expr,
+        $self_destination:expr,
+        $repeaters:expr,
+        $packet:expr,
+        $timer:expr
+    ) => {{
         let hop = $routing_table.0[$destination as usize][$rank as usize];
         if hop != 0 {
             let repno = (hop - 1) as usize;
             if repno < $repeaters.len() {
                 if $packet.expects_response() {
-                    return $repeaters[repno].aux_forward($packet, $timer);
+                    return $repeaters[repno].aux_forward(
+                        $packet,
+                        $router,
+                        $routing_table,
+                        $rank,
+                        $self_destination,
+                        $timer,
+                    );
                 } else {
                     return $repeaters[repno].aux_send($packet);
                 }
@@ -102,7 +126,16 @@ macro_rules! forward {
 
 #[cfg(not(has_drtio_routing))]
 macro_rules! forward {
-    ($routing_table:expr, $destination:expr, $rank:expr, $repeaters:expr, $packet:expr, $timer:expr) => {};
+    (
+        $router:expr,
+        $routing_table:expr,
+        $destination:expr,
+        $rank:expr,
+        $self_destination:expr,
+        $repeaters:expr,
+        $packet:expr,
+        $timer:expr
+    ) => {};
 }
 
 fn process_aux_packet(
@@ -183,6 +216,10 @@ fn process_aux_packet(
                             &drtioaux::Packet::DestinationStatusRequest {
                                 destination: destination,
                             },
+                            router,
+                            _routing_table,
+                            *rank,
+                            *self_destination,
                             timer,
                         ) {
                             Ok(()) => (),
@@ -244,7 +281,16 @@ fn process_aux_packet(
             channel,
             probe,
         } => {
-            forward!(_routing_table, _destination, *rank, _repeaters, &packet, timer);
+            forward!(
+                router,
+                _routing_table,
+                _destination,
+                *rank,
+                *self_destination,
+                _repeaters,
+                &packet,
+                timer
+            );
             let value;
             #[cfg(has_rtio_moninj)]
             unsafe {
@@ -266,7 +312,16 @@ fn process_aux_packet(
             overrd,
             value,
         } => {
-            forward!(_routing_table, _destination, *rank, _repeaters, &packet, timer);
+            forward!(
+                router,
+                _routing_table,
+                _destination,
+                *rank,
+                *self_destination,
+                _repeaters,
+                &packet,
+                timer
+            );
             #[cfg(has_rtio_moninj)]
             unsafe {
                 csr::rtio_moninj::inj_chan_sel_write(channel as _);
@@ -280,7 +335,16 @@ fn process_aux_packet(
             channel,
             overrd,
         } => {
-            forward!(_routing_table, _destination, *rank, _repeaters, &packet, timer);
+            forward!(
+                router,
+                _routing_table,
+                _destination,
+                *rank,
+                *self_destination,
+                _repeaters,
+                &packet,
+                timer
+            );
             let value;
             #[cfg(has_rtio_moninj)]
             unsafe {
@@ -299,7 +363,16 @@ fn process_aux_packet(
             destination: _destination,
             busno: _busno,
         } => {
-            forward!(_routing_table, _destination, *rank, _repeaters, &packet, timer);
+            forward!(
+                router,
+                _routing_table,
+                _destination,
+                *rank,
+                *self_destination,
+                _repeaters,
+                &packet,
+                timer
+            );
             let succeeded = i2c.start().is_ok();
             drtioaux::send(0, &drtioaux::Packet::I2cBasicReply { succeeded: succeeded })
         }
@@ -307,7 +380,16 @@ fn process_aux_packet(
             destination: _destination,
             busno: _busno,
         } => {
-            forward!(_routing_table, _destination, *rank, _repeaters, &packet, timer);
+            forward!(
+                router,
+                _routing_table,
+                _destination,
+                *rank,
+                *self_destination,
+                _repeaters,
+                &packet,
+                timer
+            );
             let succeeded = i2c.restart().is_ok();
             drtioaux::send(0, &drtioaux::Packet::I2cBasicReply { succeeded: succeeded })
         }
@@ -315,7 +397,16 @@ fn process_aux_packet(
             destination: _destination,
             busno: _busno,
         } => {
-            forward!(_routing_table, _destination, *rank, _repeaters, &packet, timer);
+            forward!(
+                router,
+                _routing_table,
+                _destination,
+                *rank,
+                *self_destination,
+                _repeaters,
+                &packet,
+                timer
+            );
             let succeeded = i2c.stop().is_ok();
             drtioaux::send(0, &drtioaux::Packet::I2cBasicReply { succeeded: succeeded })
         }
@@ -324,7 +415,16 @@ fn process_aux_packet(
             busno: _busno,
             data,
         } => {
-            forward!(_routing_table, _destination, *rank, _repeaters, &packet, timer);
+            forward!(
+                router,
+                _routing_table,
+                _destination,
+                *rank,
+                *self_destination,
+                _repeaters,
+                &packet,
+                timer
+            );
             match i2c.write(data) {
                 Ok(ack) => drtioaux::send(
                     0,
@@ -347,7 +447,16 @@ fn process_aux_packet(
             busno: _busno,
             ack,
         } => {
-            forward!(_routing_table, _destination, *rank, _repeaters, &packet, timer);
+            forward!(
+                router,
+                _routing_table,
+                _destination,
+                *rank,
+                *self_destination,
+                _repeaters,
+                &packet,
+                timer
+            );
             match i2c.read(ack) {
                 Ok(data) => drtioaux::send(
                     0,
@@ -371,7 +480,16 @@ fn process_aux_packet(
             address,
             mask,
         } => {
-            forward!(_routing_table, _destination, *rank, _repeaters, &packet, timer);
+            forward!(
+                router,
+                _routing_table,
+                _destination,
+                *rank,
+                *self_destination,
+                _repeaters,
+                &packet,
+                timer
+            );
             let ch = match mask {
                 //decode from mainline, PCA9548-centric API
                 0x00 => None,
@@ -397,7 +515,16 @@ fn process_aux_packet(
             div: _div,
             cs: _cs,
         } => {
-            forward!(_routing_table, _destination, *rank, _repeaters, &packet, timer);
+            forward!(
+                router,
+                _routing_table,
+                _destination,
+                *rank,
+                *self_destination,
+                _repeaters,
+                &packet,
+                timer
+            );
             // todo: reimplement when/if SPI is available
             //let succeeded = spi::set_config(busno, flags, length, div, cs).is_ok();
             drtioaux::send(0, &drtioaux::Packet::SpiBasicReply { succeeded: false })
@@ -407,7 +534,16 @@ fn process_aux_packet(
             busno: _busno,
             data: _data,
         } => {
-            forward!(_routing_table, _destination, *rank, _repeaters, &packet, timer);
+            forward!(
+                router,
+                _routing_table,
+                _destination,
+                *rank,
+                *self_destination,
+                _repeaters,
+                &packet,
+                timer
+            );
             // todo: reimplement when/if SPI is available
             //let succeeded = spi::write(busno, data).is_ok();
             drtioaux::send(0, &drtioaux::Packet::SpiBasicReply { succeeded: false })
@@ -416,7 +552,16 @@ fn process_aux_packet(
             destination: _destination,
             busno: _busno,
         } => {
-            forward!(_routing_table, _destination, *rank, _repeaters, &packet, timer);
+            forward!(
+                router,
+                _routing_table,
+                _destination,
+                *rank,
+                *self_destination,
+                _repeaters,
+                &packet,
+                timer
+            );
             // todo: reimplement when/if SPI is available
             // match spi::read(busno) {
             //     Ok(data) => drtioaux::send(0,
@@ -436,7 +581,16 @@ fn process_aux_packet(
         drtioaux::Packet::AnalyzerHeaderRequest {
             destination: _destination,
         } => {
-            forward!(_routing_table, _destination, *rank, _repeaters, &packet, timer);
+            forward!(
+                router,
+                _routing_table,
+                _destination,
+                *rank,
+                *self_destination,
+                _repeaters,
+                &packet,
+                timer
+            );
             let header = analyzer.get_header();
             drtioaux::send(
                 0,
@@ -450,7 +604,16 @@ fn process_aux_packet(
         drtioaux::Packet::AnalyzerDataRequest {
             destination: _destination,
         } => {
-            forward!(_routing_table, _destination, *rank, _repeaters, &packet, timer);
+            forward!(
+                router,
+                _routing_table,
+                _destination,
+                *rank,
+                *self_destination,
+                _repeaters,
+                &packet,
+                timer
+            );
             let mut data_slice: [u8; SAT_PAYLOAD_MAX_SIZE] = [0; SAT_PAYLOAD_MAX_SIZE];
             let meta = analyzer.get_data(&mut data_slice);
             drtioaux::send(
@@ -471,7 +634,16 @@ fn process_aux_packet(
             length,
             trace,
         } => {
-            forward!(_routing_table, destination, *rank, _repeaters, &packet, timer);
+            forward!(
+                router,
+                _routing_table,
+                destination,
+                *rank,
+                *self_destination,
+                _repeaters,
+                &packet,
+                timer
+            );
             *self_destination = destination;
             let succeeded = dma_manager.add(source, id, status, &trace, length as usize).is_ok();
             router.send(
@@ -492,7 +664,16 @@ fn process_aux_packet(
             id,
             succeeded,
         } => {
-            forward!(_routing_table, _destination, *rank, _repeaters, &packet, timer);
+            forward!(
+                router,
+                _routing_table,
+                _destination,
+                *rank,
+                *self_destination,
+                _repeaters,
+                &packet,
+                timer
+            );
             dma_manager.ack_upload(
                 kernel_manager,
                 source,
@@ -510,7 +691,16 @@ fn process_aux_packet(
             destination: _destination,
             id,
         } => {
-            forward!(_routing_table, _destination, *rank, _repeaters, &packet, timer);
+            forward!(
+                router,
+                _routing_table,
+                _destination,
+                *rank,
+                *self_destination,
+                _repeaters,
+                &packet,
+                timer
+            );
             let succeeded = dma_manager.erase(source, id).is_ok();
             router.send(
                 drtioaux::Packet::DmaRemoveTraceReply {
@@ -526,7 +716,16 @@ fn process_aux_packet(
             destination: _destination,
             succeeded: _,
         } => {
-            forward!(_routing_table, _destination, *rank, _repeaters, &packet, timer);
+            forward!(
+                router,
+                _routing_table,
+                _destination,
+                *rank,
+                *self_destination,
+                _repeaters,
+                &packet,
+                timer
+            );
             Ok(())
         }
         drtioaux::Packet::DmaPlaybackRequest {
@@ -535,7 +734,16 @@ fn process_aux_packet(
             id,
             timestamp,
         } => {
-            forward!(_routing_table, _destination, *rank, _repeaters, &packet, timer);
+            forward!(
+                router,
+                _routing_table,
+                _destination,
+                *rank,
+                *self_destination,
+                _repeaters,
+                &packet,
+                timer
+            );
             let succeeded = if !kernel_manager.running() {
                 dma_manager.playback(source, id, timestamp).is_ok()
             } else {
@@ -555,7 +763,16 @@ fn process_aux_packet(
             destination: _destination,
             succeeded,
         } => {
-            forward!(_routing_table, _destination, *rank, _repeaters, &packet, timer);
+            forward!(
+                router,
+                _routing_table,
+                _destination,
+                *rank,
+                *self_destination,
+                _repeaters,
+                &packet,
+                timer
+            );
             if !succeeded {
                 kernel_manager.ddma_nack();
             }
@@ -569,7 +786,16 @@ fn process_aux_packet(
             channel,
             timestamp,
         } => {
-            forward!(_routing_table, _destination, *rank, _repeaters, &packet, timer);
+            forward!(
+                router,
+                _routing_table,
+                _destination,
+                *rank,
+                *self_destination,
+                _repeaters,
+                &packet,
+                timer
+            );
             dma_manager.remote_finished(kernel_manager, id, error, channel, timestamp);
             Ok(())
         }
@@ -581,7 +807,16 @@ fn process_aux_packet(
             length,
             data,
         } => {
-            forward!(_routing_table, destination, *rank, _repeaters, &packet, timer);
+            forward!(
+                router,
+                _routing_table,
+                destination,
+                *rank,
+                *self_destination,
+                _repeaters,
+                &packet,
+                timer
+            );
             *self_destination = destination;
             let succeeded = kernel_manager.add(id, status, &data, length as usize).is_ok();
             drtioaux::send(0, &drtioaux::Packet::SubkernelAddDataReply { succeeded: succeeded })
@@ -592,7 +827,16 @@ fn process_aux_packet(
             id,
             run,
         } => {
-            forward!(_routing_table, _destination, *rank, _repeaters, &packet, timer);
+            forward!(
+                router,
+                _routing_table,
+                _destination,
+                *rank,
+                *self_destination,
+                _repeaters,
+                &packet,
+                timer
+            );
             let mut succeeded = kernel_manager.load(id).is_ok();
             // allow preloading a kernel with delayed run
             if run {
@@ -617,7 +861,16 @@ fn process_aux_packet(
             destination: _destination,
             succeeded,
         } => {
-            forward!(_routing_table, _destination, *rank, _repeaters, &packet, timer);
+            forward!(
+                router,
+                _routing_table,
+                _destination,
+                *rank,
+                *self_destination,
+                _repeaters,
+                &packet,
+                timer
+            );
             // received if local subkernel started another, remote subkernel
             kernel_manager.subkernel_load_run_reply(succeeded);
             Ok(())
@@ -628,25 +881,73 @@ fn process_aux_packet(
             with_exception,
             exception_src,
         } => {
-            forward!(_routing_table, _destination, *rank, _repeaters, &packet, timer);
+            forward!(
+                router,
+                _routing_table,
+                _destination,
+                *rank,
+                *self_destination,
+                _repeaters,
+                &packet,
+                timer
+            );
             kernel_manager.remote_subkernel_finished(id, with_exception, exception_src);
             Ok(())
         }
         drtioaux::Packet::SubkernelExceptionRequest {
+            source,
             destination: _destination,
         } => {
-            forward!(_routing_table, _destination, *rank, _repeaters, &packet, timer);
-            let mut data_slice: [u8; SAT_PAYLOAD_MAX_SIZE] = [0; SAT_PAYLOAD_MAX_SIZE];
+            forward!(
+                router,
+                _routing_table,
+                _destination,
+                *rank,
+                *self_destination,
+                _repeaters,
+                &packet,
+                timer
+            );
+            let mut data_slice: [u8; MASTER_PAYLOAD_MAX_SIZE] = [0; MASTER_PAYLOAD_MAX_SIZE];
             let meta = kernel_manager.exception_get_slice(&mut data_slice);
-            drtioaux::send(
-                0,
-                &drtioaux::Packet::SubkernelException {
+            router.send(
+                drtioaux::Packet::SubkernelException {
+                    destination: source,
                     last: meta.status.is_last(),
                     length: meta.len,
                     data: data_slice,
                 },
+                _routing_table,
+                *rank,
+                *self_destination,
             )
         }
+        drtioaux::Packet::SubkernelException {
+            destination: _destination,
+            last,
+            length,
+            data,
+        } => {
+            forward!(
+                router,
+                _routing_table,
+                _destination,
+                *rank,
+                *self_destination,
+                _repeaters,
+                &packet,
+                timer
+            );
+            kernel_manager.received_exception(
+                &data[..length as usize],
+                last,
+                router,
+                _routing_table,
+                *rank,
+                *self_destination,
+            );
+            Ok(())
+        }
         drtioaux::Packet::SubkernelMessage {
             source,
             destination: _destination,
@@ -655,7 +956,16 @@ fn process_aux_packet(
             length,
             data,
         } => {
-            forward!(_routing_table, _destination, *rank, _repeaters, &packet, timer);
+            forward!(
+                router,
+                _routing_table,
+                _destination,
+                *rank,
+                *self_destination,
+                _repeaters,
+                &packet,
+                timer
+            );
             kernel_manager.message_handle_incoming(status, id, length as usize, &data);
             router.send(
                 drtioaux::Packet::SubkernelMessageAck { destination: source },
@@ -667,7 +977,16 @@ fn process_aux_packet(
         drtioaux::Packet::SubkernelMessageAck {
             destination: _destination,
         } => {
-            forward!(_routing_table, _destination, *rank, _repeaters, &packet, timer);
+            forward!(
+                router,
+                _routing_table,
+                _destination,
+                *rank,
+                *self_destination,
+                _repeaters,
+                &packet,
+                timer
+            );
             if kernel_manager.message_ack_slice() {
                 let mut data_slice: [u8; MASTER_PAYLOAD_MAX_SIZE] = [0; MASTER_PAYLOAD_MAX_SIZE];
                 if let Some(meta) = kernel_manager.message_get_slice(&mut data_slice) {
@@ -920,6 +1239,28 @@ pub extern "C" fn main_core0() -> i32 {
     #[cfg(has_si549)]
     si549::helper_setup(&mut timer, &SI549_SETTINGS).expect("cannot initialize helper Si549");
 
+    let cfg = match Config::new() {
+        Ok(cfg) => cfg,
+        Err(err) => {
+            warn!("config initialization failed: {}", err);
+            Config::new_dummy()
+        }
+    };
+
+    if let Ok(spread_enable) = cfg.read_str("sed_spread_enable") {
+        match spread_enable.as_ref() {
+            "1" => toggle_sed_spread(1),
+            "0" => toggle_sed_spread(0),
+            _ => {
+                warn!("sed_spread_enable value not supported (only 1, 0 allowed), disabling by default");
+                toggle_sed_spread(0)
+            }
+        };
+    } else {
+        info!("SED spreading disabled by default");
+        toggle_sed_spread(0);
+    }
+
     #[cfg(has_drtio_routing)]
     let mut repeaters = [repeater::Repeater::default(); csr::DRTIOREP.len()];
     #[cfg(not(has_drtio_routing))]

src/satman/src/repeater.rs

@@ -87,6 +87,10 @@ impl Repeater {
                 if rep_link_rx_up(self.repno) {
                     if let Ok(Some(drtioaux::Packet::EchoReply)) = drtioaux::recv(self.auxno) {
                         info!("[REP#{}] remote replied after {} packets", self.repno, ping_count);
+                        let max_time = timer.get_time() + Milliseconds(200);
+                        while timer.get_time() < max_time {
+                            let _ = drtioaux::recv(self.auxno);
+                        }
                         self.state = RepeaterState::Up;
                         if let Err(e) = self.sync_tsc(timer) {
                             error!("[REP#{}] failed to sync TSC ({:?})", self.repno, e);
@@ -204,10 +208,37 @@ impl Repeater {
         }
     }
 
-    pub fn aux_forward(&self, request: &drtioaux::Packet, timer: &mut GlobalTimer) -> Result<(), drtioaux::Error> {
+    pub fn aux_forward(
+        &self,
+        request: &drtioaux::Packet,
+        router: &mut Router,
+        routing_table: &drtio_routing::RoutingTable,
+        rank: u8,
+        self_destination: u8,
+        timer: &mut GlobalTimer,
+    ) -> Result<(), drtioaux::Error> {
         self.aux_send(request)?;
-        let reply = self.recv_aux_timeout(200, timer)?;
-        drtioaux::send(0, &reply).unwrap();
+        loop {
+            let reply = self.recv_aux_timeout(200, timer)?;
+            match reply {
+                // async/locally requested packets to be consumed or routed
+                // these may come while a packet would be forwarded
+                drtioaux::Packet::DmaPlaybackStatus { .. }
+                | drtioaux::Packet::SubkernelFinished { .. }
+                | drtioaux::Packet::SubkernelMessage { .. }
+                | drtioaux::Packet::SubkernelMessageAck { .. }
+                | drtioaux::Packet::SubkernelLoadRunReply { .. }
+                | drtioaux::Packet::SubkernelException { .. }
+                | drtioaux::Packet::DmaAddTraceReply { .. }
+                | drtioaux::Packet::DmaPlaybackReply { .. } => {
+                    router.route(reply, routing_table, rank, self_destination);
+                }
+                _ => {
+                    drtioaux::send(0, &reply).unwrap();
+                    break;
+                }
+            }
+        }
         Ok(())
     }
 

src/satman/src/routing.rs

@@ -4,7 +4,7 @@ use core::cmp::min;
 #[cfg(has_drtio_routing)]
 use libboard_artiq::pl::csr;
 use libboard_artiq::{drtio_routing, drtioaux,
-                     drtioaux_proto::{PayloadStatus, MASTER_PAYLOAD_MAX_SIZE, SAT_PAYLOAD_MAX_SIZE}};
+                     drtioaux_proto::{PayloadStatus, MASTER_PAYLOAD_MAX_SIZE}};
 
 pub struct SliceMeta {
     pub destination: u8,
@@ -57,7 +57,6 @@ impl Sliceable {
         self.data.extend(data);
     }
 
-    get_slice_fn!(get_slice_sat, SAT_PAYLOAD_MAX_SIZE);
     get_slice_fn!(get_slice_master, MASTER_PAYLOAD_MAX_SIZE);
 }
 

src/satman/src/subkernel.rs

@@ -11,7 +11,7 @@ use io::{Cursor, ProtoWrite};
 use ksupport::{eh_artiq, kernel, rpc};
 use libboard_artiq::{drtio_routing::RoutingTable,
                      drtioaux,
-                     drtioaux_proto::{PayloadStatus, MASTER_PAYLOAD_MAX_SIZE, SAT_PAYLOAD_MAX_SIZE},
+                     drtioaux_proto::{PayloadStatus, MASTER_PAYLOAD_MAX_SIZE},
                      pl::csr};
 use libboard_zynq::{time::Milliseconds, timer::GlobalTimer};
 use libcortex_a9::sync_channel::Receiver;
@@ -47,6 +47,9 @@ enum KernelState {
     DmaAwait {
         max_time: Milliseconds,
     },
+    SubkernelRetrievingException {
+        destination: u8,
+    },
 }
 
 #[derive(Debug)]
@@ -123,10 +126,11 @@ struct MessageManager {
 struct Session {
     id: u32,
     kernel_state: KernelState,
-    last_exception: Option<Sliceable>,
+    last_exception: Option<Sliceable>,   // exceptions raised locally
+    external_exception: Option<Vec<u8>>, // exceptions from sub-subkernels
     messages: MessageManager,
     source: u8, // which destination requested running the kernel
-    subkernels_finished: Vec<u32>,
+    subkernels_finished: Vec<(u32, Option<u8>)>,
 }
 
 impl Session {
@@ -135,6 +139,7 @@ impl Session {
             id: id,
             kernel_state: KernelState::Absent,
             last_exception: None,
+            external_exception: None,
             messages: MessageManager::new(),
             source: 0,
             subkernels_finished: Vec::new(),
@@ -410,9 +415,9 @@ impl<'a> Manager<'_> {
         }
     }
 
-    pub fn exception_get_slice(&mut self, data_slice: &mut [u8; SAT_PAYLOAD_MAX_SIZE]) -> SliceMeta {
+    pub fn exception_get_slice(&mut self, data_slice: &mut [u8; MASTER_PAYLOAD_MAX_SIZE]) -> SliceMeta {
         match self.session.last_exception.as_mut() {
-            Some(exception) => exception.get_slice_sat(data_slice),
+            Some(exception) => exception.get_slice_master(data_slice),
             None => SliceMeta {
                 destination: 0,
                 len: 0,
@@ -540,7 +545,7 @@ impl<'a> Manager<'_> {
             return;
         }
 
-        match self.process_external_messages(timer) {
+        match self.process_external_messages(router, routing_table, rank, destination, timer) {
             Ok(()) => (),
             Err(Error::AwaitingMessage) => return, // kernel still waiting, do not process kernel messages
             Err(Error::KernelException(exception)) => {
@@ -596,6 +601,41 @@ impl<'a> Manager<'_> {
         }
     }
 
+    fn check_finished_kernels(
+        &mut self,
+        id: u32,
+        router: &mut Router,
+        routing_table: &RoutingTable,
+        rank: u8,
+        self_destination: u8,
+    ) {
+        for (i, (status, exception_source)) in self.session.subkernels_finished.iter().enumerate() {
+            if *status == id {
+                if exception_source.is_none() {
+                    self.control.tx.send(kernel::Message::SubkernelAwaitFinishReply);
+                    self.session.kernel_state = KernelState::Running;
+                    self.session.subkernels_finished.swap_remove(i);
+                } else {
+                    let destination = exception_source.unwrap();
+                    self.session.external_exception = Some(Vec::new());
+                    self.session.kernel_state = KernelState::SubkernelRetrievingException {
+                        destination: destination,
+                    };
+                    router.route(
+                        drtioaux::Packet::SubkernelExceptionRequest {
+                            source: self_destination,
+                            destination: destination,
+                        },
+                        &routing_table,
+                        rank,
+                        self_destination,
+                    );
+                }
+                break;
+            }
+        }
+    }
+
     pub fn subkernel_load_run_reply(&mut self, succeeded: bool) {
         if self.session.kernel_state == KernelState::SubkernelAwaitLoad {
             self.control
@@ -608,16 +648,46 @@ impl<'a> Manager<'_> {
     }
 
     pub fn remote_subkernel_finished(&mut self, id: u32, with_exception: bool, exception_source: u8) {
-        if with_exception {
-            self.kernel_stop();
-            self.last_finished = Some(SubkernelFinished {
-                source: self.session.source,
-                id: self.session.id,
-                with_exception: true,
-                exception_source: exception_source,
-            })
+        let exception_src = if with_exception { Some(exception_source) } else { None };
+        self.session.subkernels_finished.push((id, exception_src));
+    }
+
+    pub fn received_exception(
+        &mut self,
+        exception_data: &[u8],
+        last: bool,
+        router: &mut Router,
+        routing_table: &RoutingTable,
+        rank: u8,
+        self_destination: u8,
+    ) {
+        if let KernelState::SubkernelRetrievingException { destination } = self.session.kernel_state {
+            self.session
+                .external_exception
+                .as_mut()
+                .unwrap()
+                .extend_from_slice(exception_data);
+            if last {
+                self.control
+                    .tx
+                    .send(kernel::Message::SubkernelError(kernel::SubkernelStatus::Exception(
+                        self.session.external_exception.take().unwrap(),
+                    )));
+                self.session.kernel_state = KernelState::Running;
+            } else {
+                /* fetch another slice */
+                router.route(
+                    drtioaux::Packet::SubkernelExceptionRequest {
+                        source: self_destination,
+                        destination: destination,
+                    },
+                    routing_table,
+                    rank,
+                    self_destination,
+                );
+            }
         } else {
-            self.session.subkernels_finished.push(id);
+            warn!("Received unsolicited exception data");
         }
     }
 
@@ -780,28 +850,35 @@ impl<'a> Manager<'_> {
         Ok(false)
     }
 
-    fn process_external_messages(&mut self, timer: &GlobalTimer) -> Result<(), Error> {
+    fn process_external_messages(
+        &mut self,
+        router: &mut Router,
+        routing_table: &RoutingTable,
+        rank: u8,
+        self_destination: u8,
+        timer: &GlobalTimer,
+    ) -> Result<(), Error> {
         match &self.session.kernel_state {
             KernelState::MsgAwait { max_time, id, tags } => {
                 if let Some(max_time) = *max_time {
                     if timer.get_time() > max_time {
-                        self.control.tx.send(kernel::Message::SubkernelMsgRecvReply {
-                            status: kernel::SubkernelStatus::Timeout,
-                            count: 0,
-                        });
+                        self.control
+                            .tx
+                            .send(kernel::Message::SubkernelError(kernel::SubkernelStatus::Timeout));
                         self.session.kernel_state = KernelState::Running;
                         return Ok(());
                     }
                 }
                 if let Some(message) = self.session.messages.get_incoming(*id) {
-                    self.control.tx.send(kernel::Message::SubkernelMsgRecvReply {
-                        status: kernel::SubkernelStatus::NoError,
-                        count: message.count,
-                    });
+                    self.control
+                        .tx
+                        .send(kernel::Message::SubkernelMsgRecvReply { count: message.count });
                     let tags = tags.clone();
                     self.session.kernel_state = KernelState::Running;
                     self.pass_message_to_kernel(&message, tags, timer)
                 } else {
+                    let id = *id;
+                    self.check_finished_kernels(id, router, routing_table, rank, self_destination);
                     Err(Error::AwaitingMessage)
                 }
             }
@@ -817,27 +894,18 @@ impl<'a> Manager<'_> {
             KernelState::SubkernelAwaitFinish { max_time, id } => {
                 if let Some(max_time) = *max_time {
                     if timer.get_time() > max_time {
-                        self.control.tx.send(kernel::Message::SubkernelAwaitFinishReply {
-                            status: kernel::SubkernelStatus::Timeout,
-                        });
+                        self.control
+                            .tx
+                            .send(kernel::Message::SubkernelError(kernel::SubkernelStatus::Timeout));
                         self.session.kernel_state = KernelState::Running;
                         return Ok(());
                     }
                 }
-                let mut i = 0;
-                for status in &self.session.subkernels_finished {
-                    if *status == *id {
-                        self.control.tx.send(kernel::Message::SubkernelAwaitFinishReply {
-                            status: kernel::SubkernelStatus::NoError,
-                        });
-                        self.session.kernel_state = KernelState::Running;
-                        self.session.subkernels_finished.swap_remove(i);
-                        break;
-                    }
-                    i += 1;
-                }
+                let id = *id;
+                self.check_finished_kernels(id, router, routing_table, rank, self_destination);
                 Ok(())
             }
+            KernelState::SubkernelRetrievingException { .. } => Err(Error::AwaitingMessage),
             KernelState::DmaAwait { max_time } | KernelState::DmaPendingAwait { max_time, .. } => {
                 if timer.get_time() > *max_time {
                     self.control.tx.send(kernel::Message::DmaAwaitRemoteReply {