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ef5b06b187
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63112919a3
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@ -165,6 +165,11 @@ class DownConn_Interface(Module, AutoCSR):
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]
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# DEBUG: tx loopback fifo control
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self.tx_stb = CSRStorage()
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self.sync += phy.tx_stb_sys.eq(self.tx_stb.storage)
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# DEBUG: Transmission Pipeline
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#
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# rtio pak ----+
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@ -178,14 +183,20 @@ class DownConn_Interface(Module, AutoCSR):
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# DEBUG: TX pipeline
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self.submodules.bootstrap_loopback = bootstrap_loopback = TX_Bootstrap()
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self.submodules.mux = mux = stream.Multiplexer(word_layout, 2)
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self.submodules.pak_wrp = pak_wrp = Packet_Wrapper()
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self.submodules.trig_ack = trig_ack = Trigger_ACK_Inserter()
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self.ack = CSR()
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self.mux_sel = CSRStorage()
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self.sync += trig_ack.stb.eq(self.ack.re),
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self.comb += [
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bootstrap_loopback.source.connect(mux.sink0),
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mux.sel.eq(self.mux_sel.storage),
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]
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tx_pipeline = [bootstrap_loopback, pak_wrp, trig_ack, phy]
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tx_pipeline = [mux , pak_wrp, trig_ack, phy]
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for s, d in zip(tx_pipeline, tx_pipeline[1:]):
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self.comb += s.source.connect(d.sink)
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@ -194,20 +205,17 @@ class DownConn_Interface(Module, AutoCSR):
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# Receiver Pipeline WIP
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#
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# 32 32+8(dchar)
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# PHY ---/---> dchar -----/-----> trigger ack ------> packet ------> CDC FIFO ------> debug buffer
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# decoder checker decoder
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# 32 32
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# PHY ---/---> CDC FIFO ---/---> trigger ack ------> packet ------> debug buffer
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# checker decoder
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#
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cdr = ClockDomainsRenamer("cxp_gtx_rx")
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# decode all incoming data as duplicate char and inject the result into the bus for downstream modules
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self.submodules.dchar_decoder = dchar_decoder = cdr(Duplicated_Char_Decoder())
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# Priority level 1 packet - Trigger ack packet
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self.submodules.trig_ack_checker = trig_ack_checker = cdr(Trigger_Ack_Checker())
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self.submodules.trig_ack_checker = trig_ack_checker = cdr(CXP_Trig_Ack_Checker())
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self.submodules.trig_ack_ps = trig_ack_ps = PulseSynchronizer("cxp_gtx_rx", "sys")
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self.sync.cxp_gtx_rx += trig_ack_ps.i.eq(trig_ack_checker.ack)
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self.comb += trig_ack_ps.i.eq(trig_ack_checker.ack)
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self.trig_ack = Signal()
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self.trig_clr = Signal()
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@ -231,7 +239,7 @@ class DownConn_Interface(Module, AutoCSR):
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test_err_ps = PulseSynchronizer("cxp_gtx_rx", "sys")
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buffer_err_ps = PulseSynchronizer("cxp_gtx_rx", "sys")
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self.submodules += decode_err_ps, test_err_ps, buffer_err_ps
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self.sync.cxp_gtx_rx += [
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self.comb += [
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decode_err_ps.i.eq(bootstrap.decode_err),
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test_err_ps.i.eq(bootstrap.test_err),
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buffer_err_ps.i.eq(bootstrap.buffer_err),
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@ -274,11 +282,23 @@ class DownConn_Interface(Module, AutoCSR):
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]
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cdc_fifo = stream.AsyncFIFO(word_layout_dchar, 512)
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# DEBUG: remove this cdc fifo
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cdc_fifo = stream.AsyncFIFO(word_layout, 512)
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self.submodules += ClockDomainsRenamer({"write": "cxp_gtx_rx", "read": "sys"})(cdc_fifo)
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self.submodules.debug_out = debug_out = RX_Debug_Buffer()
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rx_pipeline = [phy, dchar_decoder, trig_ack_checker, bootstrap, cdc_fifo, debug_out]
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self.dmux_sel = CSRStorage()
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self.submodules.dmux = dmux = stream.Demultiplexer(word_layout, 2)
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self.comb += [
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dmux.source0.connect(bootstrap.sink),
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dmux.source1.connect(cdc_fifo.sink),
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cdc_fifo.source.connect(debug_out.sink),
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dmux.sel.eq(self.dmux_sel.storage),
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]
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rx_pipeline = [phy, trig_ack_checker, dmux]
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for s, d in zip(rx_pipeline, rx_pipeline[1:]):
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self.comb += s.source.connect(d.sink)
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@ -299,8 +319,8 @@ class DownConn_Interface(Module, AutoCSR):
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# Instance("OBUF", i_I=phy.gtx.cd_cxp_gtx_rx.clk, o_O=debug_sma.p_tx),
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# Instance("OBUF", i_I=, o_O=debug_sma.p_rx),
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# # pmod 0-7 pin
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# Instance("OBUF", i_I=bootstrap.test_err, o_O=pmod_pads[0]),
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# Instance("OBUF", i_I=pak_start, o_O=pmod_pads[1]),
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Instance("OBUF", i_I=bootstrap.test_err, o_O=pmod_pads[0]),
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Instance("OBUF", i_I=pak_start, o_O=pmod_pads[1]),
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# Instance("OBUF", i_I=fifo_in.source.ack, o_O=pmod_pads[2]),
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# Instance("OBUF", i_I=gtx.comma_checker.aligner_en, o_O=pmod_pads[3]),
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# Instance("OBUF", i_I=gtx.comma_checker.check_reset, o_O=pmod_pads[4]),
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@ -56,12 +56,9 @@ class Receiver(Module):
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self.source = stream.Endpoint(word_layout)
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data_valid = Signal()
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self.sync.cxp_gtx_rx += [
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data_valid.eq(gtx.comma_checker.rxfsm.ongoing("READY")),
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self.source.stb.eq(0),
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If(data_valid & self.source.ack & ~((gtx.decoders[0].d == 0xBC) & (gtx.decoders[0].k == 1)),
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If(gtx.rx_ready & self.source.ack & ~((gtx.decoders[0].d == 0xBC) & (gtx.decoders[0].k == 1)),
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self.source.stb.eq(1),
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self.source.data.eq(Cat(gtx.decoders[i].d for i in range(4))),
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self.source.k.eq(Cat(gtx.decoders[i].k for i in range(4))),
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@ -69,22 +66,17 @@ class Receiver(Module):
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]
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# DEBUG: tx fifos for loopback
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# fw -> -> cdc fifo -> buffered fifo -> gtx tx
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# fw -> fifo (sys) -> cdc fifo -> gtx tx
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cdc_fifo = stream.AsyncFIFO(word_layout, 512)
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self.submodules += ClockDomainsRenamer({"write": "sys", "read": "cxp_gtx_tx"})(cdc_fifo)
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self.sink = cdc_fifo.sink
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tx_fifo = stream.AsyncFIFO(word_layout, 512)
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self.submodules += ClockDomainsRenamer({"write": "sys", "read": "cxp_gtx_tx"})(tx_fifo)
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self.sink = tx_fifo.sink
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# fix timing violation
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cdr = ClockDomainsRenamer("cxp_gtx_tx")
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self.submodules.buf = tx_fifo = cdr(stream.SyncFIFO(word_layout, 2, buffered=True))
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self.tx_stb_sys = Signal()
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txstb = Signal()
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self.specials += MultiReg(self.tx_stb_sys, txstb, odomain="cxp_gtx_tx")
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self.comb += [
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cdc_fifo.source.connect(tx_fifo.sink),
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]
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idle_period = 50 # press in word
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word_count = Signal(max=idle_period)
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word_count = Signal(max=100)
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# JANK: fix the every 98th word got eaten
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# cnt 97 98 99 0
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@ -93,11 +85,11 @@ class Receiver(Module):
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self.sync.cxp_gtx_tx += [
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tx_fifo.source.ack.eq(0),
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If(word_count == idle_period-1,
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If(word_count == 99,
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word_count.eq(word_count.reset),
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).Else(
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If(tx_fifo.source.stb,
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If(word_count != idle_period-2, tx_fifo.source.ack.eq(1)),
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If(tx_fifo.source.stb & txstb,
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If(word_count != 98, tx_fifo.source.ack.eq(1)),
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word_count.eq(word_count + 1),
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)
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)
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@ -105,7 +97,7 @@ class Receiver(Module):
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# NOTE: prevent the first word send twice due to stream stb delay
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self.comb += [
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If((tx_fifo.source.stb & tx_fifo.source.ack & (word_count != idle_period-1)),
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If((tx_fifo.source.stb & tx_fifo.source.ack & (word_count != 99)),
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gtx.encoder.d[0].eq(tx_fifo.source.data[:8]),
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gtx.encoder.d[1].eq(tx_fifo.source.data[8:16]),
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gtx.encoder.d[2].eq(tx_fifo.source.data[16:24]),
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@ -4,23 +4,12 @@ from misoc.interconnect.csr import *
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from misoc.interconnect import stream
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from misoc.cores.liteeth_mini.mac.crc import LiteEthMACCRCEngine, LiteEthMACCRCChecker
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from functools import reduce
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from itertools import combinations
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from operator import or_, and_
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char_width = 8
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char_layout = [("data", char_width), ("k", char_width//8)]
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word_dw = 32
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word_layout = [("data", word_dw), ("k", word_dw//8)]
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word_layout_dchar = [
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("data", word_dw),
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("k", word_dw//8),
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("dchar", char_width),
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("dchar_k", char_width//8)
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]
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buffer_count = 4
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buffer_depth = 512
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@ -272,7 +261,7 @@ class TX_Bootstrap(Module, AutoCSR):
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class RX_Debug_Buffer(Module,AutoCSR):
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def __init__(self):
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self.submodules.buf_out = buf_out = stream.SyncFIFO(word_layout_dchar, 128)
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self.submodules.buf_out = buf_out = stream.SyncFIFO(word_layout, 128)
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self.sink = buf_out.sink
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self.inc = CSR()
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@ -288,64 +277,21 @@ class RX_Debug_Buffer(Module,AutoCSR):
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self.dout_valid.status.eq(buf_out.source.stb),
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]
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class Duplicated_Char_Decoder(Module):
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def __init__(self):
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self.sink = stream.Endpoint(word_layout)
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self.buffer = stream.Endpoint(word_layout)
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self.source = stream.Endpoint(word_layout_dchar)
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class Duplicate_Majority_Voter(Module):
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def __init__(self, char_4x, k_4x):
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assert char_4x.nbits == 32
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assert k_4x.nbits == 4
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# # #
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# Section 9.2.2.1 (CXP-001-2021)
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# decoder should immune to single bit errors when handling duplicated characters
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self.char = Signal(char_width)
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self.k = Signal()
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# For duplicated characters, an error correction method (e.g. majority voting) is required to meet the CXP spec:
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# RX decoder should immune to single bit errors when handling duplicated characters - Section 9.2.2.1 (CXP-001-2021)
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#
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#
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# 32
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# +---> buffer -----/-----+
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# 32 | | 32+8(dchar)
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# sink ---/---+ ---> source -----/-----> downstream
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# | 8(dchar) | decoders
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# +---> majority -----/-----+
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# voting
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#
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#
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# Due to the tight setup/hold time requiremnt for 12.5Gbps CXP, the voting logic cannot be implemented as combinational logic
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# Hence, a pipeline approach is needed to avoid any s/h violation, where the majority voting result are pre-calculate and injected into the bus immediate after the PHY.
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# And any downstream modules can access the voting result without implementing the voting logic inside the decoder
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self.sync += [
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self.sink.ack.eq(self.buffer.ack),
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self.buffer.stb.eq(self.sink.stb),
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If(self.sink.stb,
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self.buffer.data.eq(self.sink.data),
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self.buffer.k.eq(self.sink.k),
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),
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]
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# cycle 1 - calculate ABC, ABD, ACD & BCD
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char = [[self.sink.data[i*8:(i+1)*8], self.sink.k[i]] for i in range(4)]
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voters = [Record([("data", 8), ("k", 1)]) for _ in range(4)]
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for i, comb in enumerate(combinations(char, 3)):
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self.sync += [
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If(self.sink.stb,
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voters[i].data.eq(reduce(and_, [code[0] for code in comb])),
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voters[i].k.eq(reduce(and_, [code[1] for code in comb])),
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)
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]
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# cycle 2 - inject the voting result
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self.sync += [
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self.buffer.ack.eq(self.source.ack),
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self.source.stb.eq(self.buffer.stb),
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If(self.buffer.stb,
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self.source.data.eq(self.buffer.data),
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self.source.k.eq(self.buffer.k),
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self.source.dchar.eq(Replicate(reduce(or_, [v.data for v in voters]), 4)),
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self.source.dchar_k.eq(Replicate(reduce(or_, [v.k for v in voters]), 4)),
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),
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a, b, c, d = [char_4x[i*8:(i+1)*8] for i in range(4)]
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a_k, b_k, c_k, d_k = [k_4x[i:(i+1)] for i in range(4)]
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self.comb += [
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self.char.eq(a&b&c | a&b&d | a&c&d | b&c&d),
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self.k.eq(a_k&b_k&c_k | a_k&b_k&d_k | a_k&c_k&d_k | b_k&c_k&d_k),
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]
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@FullMemoryWE()
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@ -368,14 +314,15 @@ class RX_Bootstrap(Module):
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"heartbeat": 0x09,
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}
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self.sink = stream.Endpoint(word_layout_dchar)
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self.source = stream.Endpoint(word_layout_dchar)
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self.sink = stream.Endpoint(word_layout)
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self.source = stream.Endpoint(word_layout)
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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self.submodules.voter = voter = Duplicate_Majority_Voter(self.sink.data, self.sink.k)
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fsm.act("IDLE",
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self.sink.ack.eq(1),
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If((self.sink.stb & (self.sink.dchar == KCode["pak_start"]) & (self.sink.dchar_k == 1)),
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If((self.sink.stb & (voter.char == KCode["pak_start"]) & (voter.k == 1)),
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NextState("DECODE"),
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)
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)
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@ -386,9 +333,9 @@ class RX_Bootstrap(Module):
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fsm.act("DECODE",
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self.sink.ack.eq(1),
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If(self.sink.stb,
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NextValue(self.packet_type, self.sink.dchar),
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NextValue(self.packet_type, voter.char),
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Case(self.sink.dchar, {
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Case(voter.char, {
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type["data_stream"]: NextState("STREAMING"),
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type["test_packet"]: [
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NextValue(cnt, cnt.reset),
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@ -416,7 +363,7 @@ class RX_Bootstrap(Module):
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)
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# For stream data packet
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fsm.act("STREAMING",
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If((self.sink.stb & (self.sink.dchar == KCode["pak_end"]) & (self.sink.dchar_k == 1)),
|
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If((self.sink.stb & (voter.char == KCode["pak_end"]) & (voter.k == 1)),
|
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# discard K29,7
|
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self.sink.ack.eq(1),
|
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NextState("IDLE")
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|
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@ -431,7 +378,7 @@ class RX_Bootstrap(Module):
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fsm.act("VERIFY_TEST_PATTERN",
|
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self.sink.ack.eq(1),
|
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If(self.sink.stb,
|
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If(((self.sink.dchar == KCode["pak_end"]) & (self.sink.dchar_k == 1)),
|
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If(((voter.char == KCode["pak_end"]) & (voter.k == 1)),
|
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NextState("IDLE"),
|
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).Else(
|
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If(((self.sink.data != Cat(cnt, cnt+1, cnt+2, cnt+3))),
|
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|
@ -458,6 +405,7 @@ class RX_Bootstrap(Module):
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self.comb += [
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mem_port.adr[:addr_nbits].eq(addr),
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mem_port.adr[addr_nbits:].eq(write_ptr),
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mem_port.dat_w.eq(self.sink.data),
|
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]
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# For control ack, event packet
|
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|
|
@ -465,11 +413,10 @@ class RX_Bootstrap(Module):
|
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mem_port.we.eq(0),
|
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self.sink.ack.eq(1),
|
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If(self.sink.stb,
|
||||
If(((self.sink.dchar == KCode["pak_end"]) & (self.sink.dchar_k == 1)),
|
||||
If(((voter.char == KCode["pak_end"]) & (voter.k == 1)),
|
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NextState("MOVE_BUFFER_PTR"),
|
||||
).Else(
|
||||
mem_port.we.eq(1),
|
||||
mem_port.dat_w.eq(self.sink.data),
|
||||
NextValue(addr, addr + 1),
|
||||
If(addr == buffer_depth - 1,
|
||||
# discard the packet
|
||||
|
|
@ -492,10 +439,10 @@ class RX_Bootstrap(Module):
|
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NextState("IDLE"),
|
||||
)
|
||||
|
||||
class Trigger_Ack_Checker(Module, AutoCSR):
|
||||
class CXP_Trig_Ack_Checker(Module, AutoCSR):
|
||||
def __init__(self):
|
||||
self.sink = stream.Endpoint(word_layout_dchar)
|
||||
self.source = stream.Endpoint(word_layout_dchar)
|
||||
self.sink = stream.Endpoint(word_layout)
|
||||
self.source = stream.Endpoint(word_layout)
|
||||
|
||||
self.ack = Signal()
|
||||
|
||||
|
|
@ -503,8 +450,10 @@ class Trigger_Ack_Checker(Module, AutoCSR):
|
|||
|
||||
self.submodules.fsm = fsm = FSM(reset_state="COPY")
|
||||
|
||||
self.submodules.voter = voter = Duplicate_Majority_Voter(self.sink.data, self.sink.k)
|
||||
|
||||
fsm.act("COPY",
|
||||
If((self.sink.stb & (self.sink.dchar == KCode["io_ack"]) & (self.sink.dchar_k == 1)),
|
||||
If((self.sink.stb & (voter.char == KCode["io_ack"]) & (voter.k == 1)),
|
||||
# discard K28,6
|
||||
self.sink.ack.eq(1),
|
||||
NextState("CHECK_ACK")
|
||||
|
|
@ -518,7 +467,7 @@ class Trigger_Ack_Checker(Module, AutoCSR):
|
|||
NextState("COPY"),
|
||||
# discard the word after K28,6
|
||||
self.sink.ack.eq(1),
|
||||
If((self.sink.dchar == 0x01) & (self.sink.dchar_k == 0),
|
||||
If((voter.char == 0x01) & (voter.k == 0),
|
||||
self.ack.eq(1),
|
||||
)
|
||||
)
|
||||
|
|
|
|||
|
|
@ -24,9 +24,9 @@ pub fn loopback_testing(channel: usize, timer: &mut GlobalTimer, speed: cxp_phys
|
|||
while (CXP[channel].downconn_rx_ready_read)() != 1 {}
|
||||
info!("rx ready!");
|
||||
|
||||
(CXP[channel].downconn_tx_stb_write)(1);
|
||||
cxp_proto::downconn_send_test_packet(channel);
|
||||
|
||||
// FIXME: why test + trig ack doesn't work well for rx??
|
||||
cxp_proto::downconn_debug_send_trig_ack(channel);
|
||||
|
||||
const DATA_MAXSIZE: usize = 253;
|
||||
|
|
@ -51,22 +51,17 @@ pub fn loopback_testing(channel: usize, timer: &mut GlobalTimer, speed: cxp_phys
|
|||
.expect("loopback gtx tx error");
|
||||
|
||||
timer.delay_us(1000); // wait packet has arrive at RX async fifo
|
||||
(CXP[channel].downconn_tx_stb_write)(0);
|
||||
|
||||
if (CXP[channel].downconn_trigger_ack_read)() == 1 {
|
||||
(CXP[channel].downconn_trigger_ack_write)(1);
|
||||
info!("trig ack and cleared");
|
||||
}
|
||||
|
||||
if (CXP[channel].downconn_bootstrap_decoder_err_read)() == 1 {
|
||||
info!("!!!!!!!DECODER ERROR!!!!!!! and cleared");
|
||||
(CXP[channel].downconn_bootstrap_decoder_err_write)(1);
|
||||
}
|
||||
|
||||
if (CXP[channel].downconn_bootstrap_test_err_read)() == 1 {
|
||||
info!("!!!!!!!TEST ERROR!!!!!!! and cleared");
|
||||
(CXP[channel].downconn_bootstrap_test_err_write)(1);
|
||||
}
|
||||
info!("trig ack = {}", (CXP[channel].downconn_trigger_ack_read)());
|
||||
(CXP[channel].downconn_trigger_ack_write)(1);
|
||||
info!("after clr trig ack = {}", (CXP[channel].downconn_trigger_ack_read)());
|
||||
|
||||
info!(
|
||||
"decoder error = {}",
|
||||
(CXP[channel].downconn_bootstrap_decoder_err_read)()
|
||||
);
|
||||
info!("test error = {}", (CXP[channel].downconn_bootstrap_test_err_read)());
|
||||
info!("packet type = {:#06X}", (CXP[channel].downconn_packet_type_read)());
|
||||
|
||||
cxp_proto::receive(channel).expect("loopback gtx rx error");
|
||||
|
|
@ -87,8 +82,6 @@ pub fn loopback_testing(channel: usize, timer: &mut GlobalTimer, speed: cxp_phys
|
|||
break;
|
||||
}
|
||||
}
|
||||
|
||||
info!("rx ready = {}", (CXP[channel].downconn_rx_ready_read)());
|
||||
// cxp_proto::print_packetu32(&pak_arr, &k_arr);
|
||||
cxp_proto::print_packetu32(&pak_arr, &k_arr);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue