add virtual LEDs, improve IO expander setup, drive TX_DISABLE

Co-authored-by: morgan <mc@m-labs.hk>
Co-committed-by: morgan <mc@m-labs.hk>

src/gateware/kasli_soc.py

@@ -10,6 +10,7 @@ from migen.genlib.cdc import MultiReg
 from migen_axi.integration.soc_core import SoCCore
 from migen_axi.platforms import kasli_soc
 from misoc.interconnect.csr import *
+from misoc.cores import virtual_leds
 from misoc.integration import cpu_interface
 
 from artiq.coredevice import jsondesc
@@ -86,6 +87,8 @@ class GenericStandalone(SoCCore):
         self.acpki = acpki
         self.rustc_cfg = dict()
 
+        self.rustc_cfg["hw_rev"] = description["hw_rev"]
+
         platform = kasli_soc.Platform()
         platform.toolchain.bitstream_commands.extend([
             "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
@@ -178,6 +181,8 @@ class GenericMaster(SoCCore):
         self.acpki = acpki
         self.rustc_cfg = dict()
 
+        self.rustc_cfg["hw_rev"] = description["hw_rev"]
+
         platform = kasli_soc.Platform()
         platform.toolchain.bitstream_commands.extend([
             "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
@@ -191,14 +196,14 @@ class GenericMaster(SoCCore):
 
         data_pads = [platform.request("sfp", i) for i in range(4)]
 
-        self.submodules.drtio_transceiver = gtx_7series.GTX(
+        self.submodules.gt_drtio = gtx_7series.GTX(
             clock_pads=platform.request("clk_gtp"),
             pads=data_pads,
             clk_freq=clk_freq)
-        self.csr_devices.append("drtio_transceiver")
+        self.csr_devices.append("gt_drtio")
 
         txout_buf = Signal()
-        gtx0 = self.drtio_transceiver.gtxs[0]
+        gtx0 = self.gt_drtio.gtxs[0]
         self.specials += Instance("BUFG", i_I=gtx0.txoutclk, o_O=txout_buf)
 
         self.submodules.bootstrap = GTP125BootstrapClock(self.platform)
@@ -237,7 +242,7 @@ class GenericMaster(SoCCore):
         drtioaux_csr_group = []
         drtioaux_memory_group = []
         self.drtio_cri = []
-        for i in range(len(self.drtio_transceiver.channels)):
+        for i in range(len(self.gt_drtio.channels)):
             core_name = "drtio" + str(i)
             coreaux_name = "drtioaux" + str(i)
             memory_name = "drtioaux" + str(i) + "_mem"
@@ -247,7 +252,7 @@ class GenericMaster(SoCCore):
 
             cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
 
-            core = cdr(DRTIOMaster(self.rtio_tsc, self.drtio_transceiver.channels[i]))
+            core = cdr(DRTIOMaster(self.rtio_tsc, self.gt_drtio.channels[i]))
             setattr(self.submodules, core_name, core)
             self.drtio_cri.append(core.cri)
             self.csr_devices.append(core_name)
@@ -305,6 +310,14 @@ class GenericMaster(SoCCore):
             self.add_csr_group("grabber", self.grabber_csr_group)
         
 
+        self.submodules.virtual_leds = virtual_leds.VirtualLeds()
+        self.csr_devices.append("virtual_leds")
+
+        self.comb += [self.virtual_leds.get(i).eq(channel.rx_ready)
+                for i, channel in enumerate(self.gt_drtio.channels)]
+
+
+
 class GenericSatellite(SoCCore):
     def __init__(self, description, acpki=False):
         clk_freq = description["rtio_frequency"]
@@ -312,6 +325,8 @@ class GenericSatellite(SoCCore):
         self.acpki = acpki
         self.rustc_cfg = dict()
 
+        self.rustc_cfg["hw_rev"] = description["hw_rev"]
+
         platform = kasli_soc.Platform()
         platform.toolchain.bitstream_commands.extend([
             "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
@@ -323,14 +338,14 @@ class GenericSatellite(SoCCore):
 
         data_pads = [platform.request("sfp", i) for i in range(4)]
         
-        self.submodules.drtio_transceiver = gtx_7series.GTX(
+        self.submodules.gt_drtio = gtx_7series.GTX(
             clock_pads=platform.request("clk_gtp"),  
             pads=data_pads,
             clk_freq=clk_freq)
-        self.csr_devices.append("drtio_transceiver")
+        self.csr_devices.append("gt_drtio")
 
         txout_buf = Signal()
-        gtx0 = self.drtio_transceiver.gtxs[0]
+        gtx0 = self.gt_drtio.gtxs[0]
         self.specials += Instance("BUFG", i_I=gtx0.txoutclk, o_O=txout_buf)
 
         self.submodules.bootstrap = GTP125BootstrapClock(self.platform)
@@ -367,7 +382,7 @@ class GenericSatellite(SoCCore):
         drtioaux_memory_group = []
         drtiorep_csr_group = []
         self.drtio_cri = []
-        for i in range(len(self.drtio_transceiver.channels)):
+        for i in range(len(self.gt_drtio.channels)):
             coreaux_name = "drtioaux" + str(i)
             memory_name = "drtioaux" + str(i) + "_mem"
             drtioaux_csr_group.append(coreaux_name)
@@ -378,7 +393,7 @@ class GenericSatellite(SoCCore):
             if i == 0:
                 self.submodules.rx_synchronizer = cdr(XilinxRXSynchronizer())
                 core = cdr(DRTIOSatellite(
-                    self.rtio_tsc, self.drtio_transceiver.channels[i],
+                    self.rtio_tsc, self.gt_drtio.channels[i],
                     self.rx_synchronizer))
                 self.submodules.drtiosat = core
                 self.csr_devices.append("drtiosat")
@@ -387,7 +402,7 @@ class GenericSatellite(SoCCore):
                 drtiorep_csr_group.append(corerep_name)
 
                 core = cdr(DRTIORepeater(
-                    self.rtio_tsc, self.drtio_transceiver.channels[i]))
+                    self.rtio_tsc, self.gt_drtio.channels[i]))
                 setattr(self.submodules, corerep_name, core)
                 self.drtio_cri.append(core.cri)
                 self.csr_devices.append(corerep_name)
@@ -452,13 +467,13 @@ class GenericSatellite(SoCCore):
             si5324_clkin=platform.request("cdr_clk"),
             rx_synchronizer=self.rx_synchronizer,
             ultrascale=False,
-            rtio_clk_freq=self.drtio_transceiver.rtio_clk_freq)
+            rtio_clk_freq=self.gt_drtio.rtio_clk_freq)
         self.csr_devices.append("siphaser")
         self.rustc_cfg["has_si5324"] = None
         self.rustc_cfg["has_siphaser"] = None
         self.rustc_cfg["si5324_soft_reset"] = None
 
-        gtx0 = self.drtio_transceiver.gtxs[0]
+        gtx0 = self.gt_drtio.gtxs[0]
         platform.add_false_path_constraints(
             gtx0.txoutclk, gtx0.rxoutclk)
 
@@ -467,6 +482,12 @@ class GenericSatellite(SoCCore):
             self.add_csr_group("grabber", self.grabber_csr_group)
             # no RTIO CRG here
         
+        self.submodules.virtual_leds = virtual_leds.VirtualLeds()
+        self.csr_devices.append("virtual_leds")
+
+        self.comb += [self.virtual_leds.get(i).eq(channel.rx_ready)
+                for i, channel in enumerate(self.gt_drtio.channels)]
+
 
 def write_mem_file(soc, filename):
     with open(filename, "w") as f:

src/gateware/zc706.py

@@ -222,15 +222,15 @@ class _MasterBase(SoCCore):
         self.submodules += SMAClkinForward(self.platform)
 
         # 1000BASE_BX10 Ethernet compatible, 125MHz RTIO clock
-        self.submodules.drtio_transceiver = gtx_7series.GTX(
+        self.submodules.gt_drtio = gtx_7series.GTX(
             clock_pads=platform.request("si5324_clkout"),
             pads=data_pads,
             clk_freq=clk_freq)
-        self.csr_devices.append("drtio_transceiver")
+        self.csr_devices.append("gt_drtio")
 
         self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3)
         txout_buf = Signal()
-        gtx0 = self.drtio_transceiver.gtxs[0]
+        gtx0 = self.gt_drtio.gtxs[0]
         self.specials += Instance("BUFG", i_I=gtx0.txoutclk, o_O=txout_buf)
         self.submodules.bootstrap = CLK200BootstrapClock(platform, clk_freq)
         self.submodules.sys_crg = zynq_clocking.SYSCRG(
@@ -247,7 +247,7 @@ class _MasterBase(SoCCore):
         drtioaux_csr_group = []
         drtioaux_memory_group = []
         self.drtio_cri = []
-        for i in range(len(self.drtio_transceiver.channels)):
+        for i in range(len(self.gt_drtio.channels)):
             core_name = "drtio" + str(i)
             coreaux_name = "drtioaux" + str(i)
             memory_name = "drtioaux" + str(i) + "_mem"
@@ -258,7 +258,7 @@ class _MasterBase(SoCCore):
             cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
 
             core = cdr(DRTIOMaster(
-                self.rtio_tsc, self.drtio_transceiver.channels[i]))
+                self.rtio_tsc, self.gt_drtio.channels[i]))
             setattr(self.submodules, core_name, core)
             self.drtio_cri.append(core.cri)
             self.csr_devices.append(core_name)
@@ -277,7 +277,7 @@ class _MasterBase(SoCCore):
         self.add_csr_group("drtioaux", drtioaux_csr_group)
         self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
 
-        self.rustc_cfg["rtio_frequency"] = str(self.drtio_transceiver.rtio_clk_freq/1e6)
+        self.rustc_cfg["rtio_frequency"] = str(self.gt_drtio.rtio_clk_freq/1e6)
 
         self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324_33").rst_n)
         self.csr_devices.append("si5324_rst_n")
@@ -290,7 +290,7 @@ class _MasterBase(SoCCore):
             gtx0.txoutclk, gtx0.rxoutclk)
         # Constrain RX timing for the each transceiver channel
         # (Each channel performs single-lane phase alignment for RX)
-        for gtx in self.drtio_transceiver.gtxs[1:]:
+        for gtx in self.gt_drtio.gtxs[1:]:
             platform.add_false_path_constraints(
                 gtx0.txoutclk, gtx.rxoutclk)
 
@@ -359,15 +359,15 @@ class _SatelliteBase(SoCCore):
         self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3)
 
         # 1000BASE_BX10 Ethernet compatible, 125MHz RTIO clock
-        self.submodules.drtio_transceiver = gtx_7series.GTX(
+        self.submodules.gt_drtio = gtx_7series.GTX(
             clock_pads=platform.request("si5324_clkout"),
             pads=data_pads,
             clk_freq=clk_freq)
-        self.csr_devices.append("drtio_transceiver")
+        self.csr_devices.append("gt_drtio")
 
         txout_buf = Signal()
         txout_buf.attr.add("keep")
-        gtx0 = self.drtio_transceiver.gtxs[0]
+        gtx0 = self.gt_drtio.gtxs[0]
         self.specials += Instance(
             "BUFG", 
             i_I=gtx0.txoutclk, 
@@ -387,7 +387,7 @@ class _SatelliteBase(SoCCore):
         drtioaux_memory_group = []
         drtiorep_csr_group = []
         self.drtio_cri = []
-        for i in range(len(self.drtio_transceiver.channels)):
+        for i in range(len(self.gt_drtio.channels)):
             coreaux_name = "drtioaux" + str(i)
             memory_name = "drtioaux" + str(i) + "_mem"
             drtioaux_csr_group.append(coreaux_name)
@@ -399,7 +399,7 @@ class _SatelliteBase(SoCCore):
             if i == 0:
                 self.submodules.rx_synchronizer = cdr(XilinxRXSynchronizer())
                 core = cdr(DRTIOSatellite(
-                    self.rtio_tsc, self.drtio_transceiver.channels[0], self.rx_synchronizer))
+                    self.rtio_tsc, self.gt_drtio.channels[0], self.rx_synchronizer))
                 self.submodules.drtiosat = core
                 self.csr_devices.append("drtiosat")
             # Repeaters
@@ -407,7 +407,7 @@ class _SatelliteBase(SoCCore):
                 corerep_name = "drtiorep" + str(i-1)
                 drtiorep_csr_group.append(corerep_name)
                 core = cdr(DRTIORepeater(
-                    self.rtio_tsc, self.drtio_transceiver.channels[i]))
+                    self.rtio_tsc, self.gt_drtio.channels[i]))
                 setattr(self.submodules, corerep_name, core)
                 self.drtio_cri.append(core.cri)
                 self.csr_devices.append(corerep_name)
@@ -431,14 +431,14 @@ class _SatelliteBase(SoCCore):
         self.add_csr_group("drtiorep", drtiorep_csr_group)
         self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
 
-        self.rustc_cfg["rtio_frequency"] = str(self.drtio_transceiver.rtio_clk_freq/1e6)
+        self.rustc_cfg["rtio_frequency"] = str(self.gt_drtio.rtio_clk_freq/1e6)
 
         # Si5324 Phaser
         self.submodules.siphaser = SiPhaser7Series(
             si5324_clkin=platform.request("si5324_clkin"),
             rx_synchronizer=self.rx_synchronizer,
             ultrascale=False,
-            rtio_clk_freq=self.drtio_transceiver.rtio_clk_freq)
+            rtio_clk_freq=self.gt_drtio.rtio_clk_freq)
         platform.add_false_path_constraints(
             self.sys_crg.cd_sys.clk, self.siphaser.mmcm_freerun_output)
         self.csr_devices.append("siphaser")
@@ -447,14 +447,14 @@ class _SatelliteBase(SoCCore):
         self.rustc_cfg["has_si5324"] = None
         self.rustc_cfg["has_siphaser"] = None
 
-        rtio_clk_period = 1e9/self.drtio_transceiver.rtio_clk_freq
+        rtio_clk_period = 1e9/self.gt_drtio.rtio_clk_freq
         # Constrain TX & RX timing for the first transceiver channel
         # (First channel acts as master for phase alignment for all channels' TX)
         platform.add_false_path_constraints(
             gtx0.txoutclk, gtx0.rxoutclk)
         # Constrain RX timing for the each transceiver channel
         # (Each channel performs single-lane phase alignment for RX)
-        for gtx in self.drtio_transceiver.gtxs[1:]:
+        for gtx in self.gt_drtio.gtxs[1:]:
             platform.add_false_path_constraints(
                 self.sys_crg.cd_sys.clk, gtx.rxoutclk)
 

src/libboard_artiq/src/io_expander.rs

@@ -1,6 +1,8 @@
 use libboard_zynq::i2c;
 use log::info;
 
+use crate::pl::csr;
+
 // Only the bare minimum registers. Bits/IO connections equivalent between IC types.
 struct Registers {
     // PCA9539 equivalent register names in comments
@@ -10,23 +12,49 @@ struct Registers {
     gpiob: u8,  // Output Port 1
 }
 
-pub struct IoExpander<'a> {
+//IO expanders pins
-    i2c: &'a mut i2c::I2c,
+const IODIR_OUT_SFP_TX_DISABLE: u8 = 0x02;
+const IODIR_OUT_SFP_LED: u8 = 0x40;
+#[cfg(hw_rev = "v1.0")]
+const IODIR_OUT_SFP0_LED: u8 = 0x40;
+#[cfg(hw_rev = "v1.1")]
+const IODIR_OUT_SFP0_LED: u8 = 0x80;
+
+//IO expander port direction
+const IODIR0: [u8; 2] = [
+    0xFF & !IODIR_OUT_SFP_TX_DISABLE & !IODIR_OUT_SFP0_LED,
+    0xFF & !IODIR_OUT_SFP_TX_DISABLE & !IODIR_OUT_SFP_LED,
+];
+
+const IODIR1: [u8; 2] = [
+    0xFF & !IODIR_OUT_SFP_TX_DISABLE & !IODIR_OUT_SFP_LED,
+    0xFF & !IODIR_OUT_SFP_TX_DISABLE & !IODIR_OUT_SFP_LED,
+];
+
+pub struct IoExpander {
     address: u8,
+    virtual_led_mapping: &'static [(u8, u8, u8)],
     iodir: [u8; 2],
     out_current: [u8; 2],
     out_target: [u8; 2],
     registers: Registers,
 }
 
-impl<'a> IoExpander<'a> {
+impl IoExpander {
-    pub fn new(i2c: &'a mut i2c::I2c, index: u8) -> Result<Self, &'static str> {
+    pub fn new(i2c: &mut i2c::I2c, index: u8) -> Result<Self, &'static str> {
+        #[cfg(hw_rev = "v1.0")]
+        const VIRTUAL_LED_MAPPING0: [(u8, u8, u8); 2] = [(0, 0, 6), (1, 1, 6)];
+        #[cfg(hw_rev = "v1.1")]
+        const VIRTUAL_LED_MAPPING0: [(u8, u8, u8); 2] = [(0, 0, 7), (1, 1, 6)];
+
+        const VIRTUAL_LED_MAPPING1: [(u8, u8, u8); 2] = [(2, 0, 6), (3, 1, 6)];
+
         // Both expanders on SHARED I2C bus
         let mut io_expander = match index {
             0 => IoExpander {
-                i2c,
                 address: 0x40,
-                iodir: [0xff; 2],
+                virtual_led_mapping: &VIRTUAL_LED_MAPPING0,
+                iodir: IODIR0,
                 out_current: [0; 2],
                 out_target: [0; 2],
                 registers: Registers {
@@ -37,9 +65,9 @@ impl<'a> IoExpander<'a> {
                 },
             },
             1 => IoExpander {
-                i2c,
                 address: 0x42,
-                iodir: [0xff; 2],
+                virtual_led_mapping: &VIRTUAL_LED_MAPPING1,
+                iodir: IODIR1,
                 out_current: [0; 2],
                 out_target: [0; 2],
                 registers: Registers {
@@ -51,7 +79,7 @@ impl<'a> IoExpander<'a> {
             },
             _ => return Err("incorrect I/O expander index"),
         };
-        if !io_expander.check_ack()? {
+        if !io_expander.check_ack(i2c)? {
             info!("MCP23017 io expander {} not found. Checking for PCA9539.", index);
             io_expander.address += 0xa8; // translate to PCA9539 addresses (see schematic)
             io_expander.registers = Registers {
@@ -60,57 +88,58 @@ impl<'a> IoExpander<'a> {
                 gpioa: 0x02,
                 gpiob: 0x03,
             };
-            if !io_expander.check_ack()? {
+            if !io_expander.check_ack(i2c)? {
                 return Err("Neither MCP23017 nor PCA9539 io expander found.");
             };
         }
         Ok(io_expander)
     }
 
-    fn select(&mut self) -> Result<(), &'static str> {
+    fn select(&self, i2c: &mut i2c::I2c) -> Result<(), &'static str> {
-        self.i2c.pca954x_select(0x70, None)?;
+        i2c.pca954x_select(0x70, None)?;
-        self.i2c.pca954x_select(0x71, Some(3))?;
+        i2c.pca954x_select(0x71, Some(3))?;
         Ok(())
     }
 
-    fn write(&mut self, addr: u8, value: u8) -> Result<(), &'static str> {
+    fn write(&self, i2c: &mut i2c::I2c, addr: u8, value: u8) -> Result<(), &'static str> {
-        self.i2c.start()?;
+        i2c.start()?;
-        self.i2c.write(self.address)?;
+        i2c.write(self.address)?;
-        self.i2c.write(addr)?;
+        i2c.write(addr)?;
-        self.i2c.write(value)?;
+        i2c.write(value)?;
-        self.i2c.stop()?;
+        i2c.stop()?;
         Ok(())
     }
 
-    fn check_ack(&mut self) -> Result<bool, &'static str> {
+    fn check_ack(&self, i2c: &mut i2c::I2c) -> Result<bool, &'static str> {
         // Check for ack from io expander
-        self.select()?;
+        self.select(i2c)?;
-        self.i2c.start()?;
+        i2c.start()?;
-        let ack = self.i2c.write(self.address)?;
+        let ack = i2c.write(self.address)?;
-        self.i2c.stop()?;
+        i2c.stop()?;
         Ok(ack)
     }
 
-    fn update_iodir(&mut self) -> Result<(), &'static str> {
+    fn update_iodir(&self, i2c: &mut i2c::I2c) -> Result<(), &'static str> {
-        self.write(self.registers.iodira, self.iodir[0])?;
+        self.write(i2c, self.registers.iodira, self.iodir[0])?;
-        self.write(self.registers.iodirb, self.iodir[1])?;
+        self.write(i2c, self.registers.iodirb, self.iodir[1])?;
         Ok(())
     }
 
-    pub fn init(&mut self) -> Result<(), &'static str> {
+    pub fn init(&mut self, i2c: &mut i2c::I2c) -> Result<(), &'static str> {
-        self.select()?;
+        self.select(i2c)?;
-        self.update_iodir()?;
+
+        self.update_iodir(i2c)?;
 
         self.out_current[0] = 0x00;
-        self.write(self.registers.gpioa, 0x00)?;
+        self.write(i2c, self.registers.gpioa, 0x00)?;
         self.out_current[1] = 0x00;
-        self.write(self.registers.gpiob, 0x00)?;
+        self.write(i2c, self.registers.gpiob, 0x00)?;
         Ok(())
     }
 
-    pub fn set_oe(&mut self, port: u8, outputs: u8) -> Result<(), &'static str> {
+    pub fn set_oe(&mut self, i2c: &mut i2c::I2c, port: u8, outputs: u8) -> Result<(), &'static str> {
         self.iodir[port as usize] &= !outputs;
-        self.update_iodir()?;
+        self.update_iodir(i2c)?;
         Ok(())
     }
 
@@ -122,15 +151,20 @@ impl<'a> IoExpander<'a> {
         }
     }
 
-    pub fn service(&mut self) -> Result<(), &'static str> {
+    pub fn service(&mut self, i2c: &mut i2c::I2c) -> Result<(), &'static str> {
+        for (led, port, bit) in self.virtual_led_mapping.iter() {
+            let level = unsafe { csr::virtual_leds::status_read() >> led & 1 };
+            self.set(*port, *bit, level != 0);
+        }
+
         if self.out_target != self.out_current {
-            self.select()?;
+            self.select(i2c)?;
             if self.out_target[0] != self.out_current[0] {
-                self.write(self.registers.gpioa, self.out_target[0])?;
+                self.write(i2c, self.registers.gpioa, self.out_target[0])?;
                 self.out_current[0] = self.out_target[0];
             }
             if self.out_target[1] != self.out_current[1] {
-                self.write(self.registers.gpiob, self.out_target[1])?;
+                self.write(i2c, self.registers.gpiob, self.out_target[1])?;
                 self.out_current[1] = self.out_target[1];
             }
         }

src/runtime/src/main.rs

@@ -12,6 +12,8 @@
 #[macro_use]
 extern crate alloc;
 
+use core::cell::RefCell;
+
 use libasync::{block_async, task};
 #[cfg(feature = "target_kasli_soc")]
 use libboard_artiq::io_expander;
@@ -102,6 +104,25 @@ async fn report_async_rtio_errors() {
     }
 }
 
+#[cfg(feature = "target_kasli_soc")]
+async fn io_expanders_service(
+    i2c_bus: RefCell<&mut libboard_zynq::i2c::I2c>,
+    io_expander0: RefCell<io_expander::IoExpander>,
+    io_expander1: RefCell<io_expander::IoExpander>,
+) {
+    loop {
+        task::r#yield().await;
+        io_expander0
+            .borrow_mut()
+            .service(&mut i2c_bus.borrow_mut())
+            .expect("I2C I/O expander #0 service failed");
+        io_expander1
+            .borrow_mut()
+            .service(&mut i2c_bus.borrow_mut())
+            .expect("I2C I/O expander #1 service failed");
+    }
+}
+
 static mut LOG_BUFFER: [u8; 1 << 17] = [0; 1 << 17];
 
 #[no_mangle]
@@ -122,20 +143,26 @@ pub fn main_core0() {
     info!("gateware ident: {}", identifier_read(&mut [0; 64]));
 
     i2c::init();
+    let i2c_bus = unsafe { (i2c::I2C_BUS).as_mut().unwrap() };
 
+    let (mut io_expander0, mut io_expander1);
     #[cfg(feature = "target_kasli_soc")]
     {
-        let i2c = unsafe { (&mut i2c::I2C_BUS).as_mut().unwrap() };
+        io_expander0 = io_expander::IoExpander::new(i2c_bus, 0).unwrap();
-        for expander_i in 0..=1 {
+        io_expander1 = io_expander::IoExpander::new(i2c_bus, 1).unwrap();
-            let mut io_expander = io_expander::IoExpander::new(i2c, expander_i).unwrap();
+        io_expander0
-            io_expander.init().expect("I2C I/O expander #0 initialization failed");
+            .init(i2c_bus)
+            .expect("I2C I/O expander #0 initialization failed");
+        io_expander1
+            .init(i2c_bus)
+            .expect("I2C I/O expander #1 initialization failed");
         // Actively drive TX_DISABLE to false on SFP0..3
-            io_expander.set_oe(0, 1 << 1).unwrap();
+        io_expander0.set(0, 1, false);
-            io_expander.set_oe(1, 1 << 1).unwrap();
+        io_expander1.set(0, 1, false);
-            io_expander.set(0, 1, false);
+        io_expander0.set(1, 1, false);
-            io_expander.set(1, 1, false);
+        io_expander1.set(1, 1, false);
-            io_expander.service().unwrap();
+        io_expander0.service(i2c_bus).unwrap();
-        }
+        io_expander1.service(i2c_bus).unwrap();
     }
 
     let cfg = match Config::new() {
@@ -150,5 +177,11 @@ pub fn main_core0() {
 
     task::spawn(report_async_rtio_errors());
 
+    #[cfg(feature = "target_kasli_soc")]
+    task::spawn(io_expanders_service(
+        RefCell::new(i2c_bus),
+        RefCell::new(io_expander0),
+        RefCell::new(io_expander1),
+    ));
     comms::main(timer, cfg);
 }

src/runtime/src/rtio_clocking.rs

@@ -92,7 +92,7 @@ fn init_rtio(timer: &mut GlobalTimer) {
 #[cfg(has_drtio)]
 fn init_drtio(timer: &mut GlobalTimer) {
     unsafe {
-        pl::csr::drtio_transceiver::stable_clkin_write(1);
+        pl::csr::gt_drtio::stable_clkin_write(1);
     }
 
     timer.delay_ms(20); // wait for CPLL/QPLL/SYS PLL lock
@@ -104,7 +104,7 @@ fn init_drtio(timer: &mut GlobalTimer) {
     }
     unsafe {
         pl::csr::rtio_core::reset_phy_write(1);
-        pl::csr::drtio_transceiver::txenable_write(0xffffffffu32 as _);
+        pl::csr::gt_drtio::txenable_write(0xffffffffu32 as _);
     }
 }
 

src/satman/src/main.rs

@@ -611,18 +611,25 @@ pub extern "C" fn main_core0() -> i32 {
 
     let mut i2c = I2c::i2c0();
     i2c.init().expect("I2C initialization failed");
+
+    let (mut io_expander0, mut io_expander1);
     #[cfg(feature = "target_kasli_soc")]
     {
-        for expander_i in 0..=1 {
+        io_expander0 = io_expander::IoExpander::new(&mut i2c, 0).unwrap();
-            let mut io_expander = io_expander::IoExpander::new(&mut i2c, expander_i).unwrap();
+        io_expander1 = io_expander::IoExpander::new(&mut i2c, 1).unwrap();
-            io_expander.init().expect("I2C I/O expander #0 initialization failed");
+        io_expander0
+            .init(&mut i2c)
+            .expect("I2C I/O expander #0 initialization failed");
+        io_expander1
+            .init(&mut i2c)
+            .expect("I2C I/O expander #1 initialization failed");
         // Actively drive TX_DISABLE to false on SFP0..3
-            io_expander.set_oe(0, 1 << 1).unwrap();
+        io_expander0.set(0, 1, false);
-            io_expander.set_oe(1, 1 << 1).unwrap();
+        io_expander1.set(0, 1, false);
-            io_expander.set(0, 1, false);
+        io_expander0.set(1, 1, false);
-            io_expander.set(1, 1, false);
+        io_expander1.set(1, 1, false);
-            io_expander.service().unwrap();
+        io_expander0.service(&mut i2c).unwrap();
-        }
+        io_expander1.service(&mut i2c).unwrap();
     }
 
     #[cfg(has_si5324)]
@@ -631,7 +638,7 @@ pub extern "C" fn main_core0() -> i32 {
     timer.delay_us(100_000);
     info!("Switching SYS clocks...");
     unsafe {
-        csr::drtio_transceiver::stable_clkin_write(1);
+        csr::gt_drtio::stable_clkin_write(1);
     }
     timer.delay_us(50_000); // wait for CPLL/QPLL/MMCM lock
     let clk = unsafe { csr::sys_crg::current_clock_read() };
@@ -642,7 +649,7 @@ pub extern "C" fn main_core0() -> i32 {
     }
 
     unsafe {
-        csr::drtio_transceiver::txenable_write(0xffffffffu32 as _);
+        csr::gt_drtio::txenable_write(0xffffffffu32 as _);
     }
 
     #[cfg(has_drtio_routing)]
@@ -664,6 +671,16 @@ pub extern "C" fn main_core0() -> i32 {
             for mut rep in repeaters.iter_mut() {
                 rep.service(&routing_table, rank, &mut timer);
             }
+            #[cfg(feature = "target_kasli_soc")]
+            {
+                io_expander0
+                    .service(&mut i2c)
+                    .expect("I2C I/O expander #0 service failed");
+                io_expander1
+                    .service(&mut i2c)
+                    .expect("I2C I/O expander #1 service failed");
+            }
+
             hardware_tick(&mut hardware_tick_ts, &mut timer);
         }
 
@@ -700,6 +717,15 @@ pub extern "C" fn main_core0() -> i32 {
             for mut rep in repeaters.iter_mut() {
                 rep.service(&routing_table, rank, &mut timer);
             }
+            #[cfg(feature = "target_kasli_soc")]
+            {
+                io_expander0
+                    .service(&mut i2c)
+                    .expect("I2C I/O expander #0 service failed");
+                io_expander1
+                    .service(&mut i2c)
+                    .expect("I2C I/O expander #1 service failed");
+            }
             hardware_tick(&mut hardware_tick_ts, &mut timer);
             if drtiosat_tsc_loaded() {
                 info!("TSC loaded from uplink");