fix cargo-xbuild dependency

.pre-commit-config.yaml

@@ -1,8 +0,0 @@
-repos: 
-  - repo: local
-    hooks:
-      - id: cargo_format
-        name: cargo_format
-        entry: cargofmt.sh
-        language: script
-        pass_filenames: false

build_CI.sh

@@ -1,38 +0,0 @@
-#!/usr/bin/env bash
-
-set -e
-
-if [ -z "$OPENOCD_ZYNQ" ]; then
-    echo "OPENOCD_ZYNQ environment variable must be set"
-    exit 1
-fi
-if [ -z "$SZL" ]; then
-    echo "SZL environment variable must be set"
-    exit 1
-fi
-
-
-# variant="firmware"
-# variant="gateware"
-# variant="jtag"
-variant="sd"
-
-nix build .#kasli_soc-demo-$variant -L
-nix build .#kasli_soc-master-$variant -L
-nix build .#kasli_soc-satellite-$variant -L
-
-# nix build .#zc706-acpki_nist_clock-$variant -L
-# nix build .#zc706-acpki_nist_clock_master-$variant -L
-# nix build .#zc706-acpki_nist_clock_satellite-$variant -L
-
-# nix build .#zc706-acpki_nist_qc2-$variant -L
-# nix build .#zc706-acpki_nist_qc2_master-$variant -L
-# nix build .#zc706-acpki_nist_qc2_satellite-$variant -L
-
-# nix build .#zc706-nist_clock-$variant -L
-# nix build .#zc706-nist_clock_master-$variant -L
-# nix build .#zc706-nist_clock_satellite-$variant -L
-
-# nix build .#zc706-nist_qc2-$variant -L
-# nix build .#zc706-nist_qc2_master-$variant -L
-# nix build .#zc706-nist_qc2_satellite-$variant -L

build_gw.sh

@@ -1,4 +0,0 @@
-#!/usr/bin/env bash
-set -e
-
-python src/gateware/zc706.py -r build/pl.rs -c build/rustc-cfg -m build/mem.rs  -V CXP_Demo -g build/gateware/

cargofmt.sh

@@ -1,5 +0,0 @@
-#!/usr/bin/env bash
-
-nix-shell -p gnumake --command 'make manifests -B'
-cd src
-cargo fmt -- --check

coaxpress.drawio

@@ -1,338 +0,0 @@
-<mxfile host="65bd71144e">
-    <diagram id="en7HUHNV3kVsTTCxeEt8" name="Page-1">
-        <mxGraphModel dx="1155" dy="1481" grid="1" gridSize="10" guides="1" tooltips="1" connect="1" arrows="1" fold="1" page="0" pageScale="1" pageWidth="850" pageHeight="1100" background="none" math="0" shadow="0">
-            <root>
-                <mxCell id="0"/>
-                <mxCell id="1" parent="0"/>
-                <mxCell id="7" style="edgeStyle=none;html=1;exitX=1;exitY=0.5;exitDx=0;exitDy=0;rounded=0;" parent="1" edge="1">
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-                        <mxPoint x="320" y="280" as="targetPoint"/>
-                        <mxPoint x="240" y="280.0000000000001" as="sourcePoint"/>
-                    </mxGeometry>
-                </mxCell>
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-                    </mxGeometry>
-                </mxCell>
-                <mxCell id="14" value="" style="endArrow=classic;html=1;entryX=1;entryY=0.5;entryDx=0;entryDy=0;rounded=0;dashed=1;" parent="1" edge="1">
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-                        <mxPoint x="390" y="600" as="sourcePoint"/>
-                        <mxPoint x="240" y="599.76" as="targetPoint"/>
-                    </mxGeometry>
-                </mxCell>
-                <mxCell id="15" value="CTRL/Trig" style="edgeLabel;html=1;align=center;verticalAlign=middle;resizable=0;points=[];rounded=0;" parent="14" vertex="1" connectable="0">
-                    <mxGeometry x="-0.375" y="4" relative="1" as="geometry">
-                        <mxPoint x="-15" y="-14" as="offset"/>
-                    </mxGeometry>
-                </mxCell>
-                <mxCell id="21" value="TX&lt;br style=&quot;border-color: var(--border-color);&quot;&gt;Low speed" style="shape=offPageConnector;whiteSpace=wrap;html=1;rotation=0;size=0.3333333333333333;direction=south;fillColor=#DAE8FC;strokeColor=#6c8ebf;rounded=0;" parent="1" vertex="1">
-                    <mxGeometry x="120" y="400" width="120" height="80" as="geometry"/>
-                </mxCell>
-                <mxCell id="24" value="RX GTX&lt;br style=&quot;border-color: var(--border-color);&quot;&gt;High Speed&lt;br&gt;Master" style="shape=offPageConnector;whiteSpace=wrap;html=1;rotation=0;size=0.3333333333333333;direction=north;fillColor=#f8cecc;strokeColor=#b85450;rounded=0;" parent="1" vertex="1">
-                    <mxGeometry x="120" y="240" width="120" height="80" as="geometry"/>
-                </mxCell>
-                <mxCell id="25" value="TX High Speed&lt;br&gt;(optional)" style="shape=offPageConnector;whiteSpace=wrap;html=1;rotation=0;size=0.3333333333333333;direction=south;fillColor=#f8cecc;strokeColor=#b85450;dashed=1;rounded=0;" parent="1" vertex="1">
-                    <mxGeometry x="120" y="560" width="120" height="80" as="geometry"/>
-                </mxCell>
-                <mxCell id="26" value="RX GTX&lt;br style=&quot;border-color: var(--border-color);&quot;&gt;High Speed&amp;nbsp;&lt;br&gt;Extension&lt;br&gt;(Optional)" style="shape=offPageConnector;whiteSpace=wrap;html=1;rotation=0;size=0.4166666666666667;direction=north;fillColor=#f8cecc;strokeColor=#b85450;rounded=0;dashed=1;" parent="1" vertex="1">
-                    <mxGeometry x="120" width="120" height="80" as="geometry"/>
-                </mxCell>
-                <mxCell id="30" value="" style="endArrow=classic;html=1;entryX=1;entryY=0.5;entryDx=0;entryDy=0;rounded=0;" parent="1" edge="1">
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-                    </mxGeometry>
-                </mxCell>
-                <mxCell id="31" value="CTRL/Trig &lt;br&gt;DATA PACKET" style="edgeLabel;html=1;align=center;verticalAlign=middle;resizable=0;points=[];rounded=0;" parent="30" vertex="1" connectable="0">
-                    <mxGeometry x="-0.375" y="4" relative="1" as="geometry">
-                        <mxPoint x="-30" y="-24" as="offset"/>
-                    </mxGeometry>
-                </mxCell>
-                <mxCell id="33" value="&lt;div style=&quot;text-align: justify;&quot;&gt;&lt;span style=&quot;background-color: initial;&quot;&gt;TX pipeline&lt;/span&gt;&lt;/div&gt;&lt;div style=&quot;text-align: justify;&quot;&gt;&lt;span style=&quot;background-color: initial;&quot;&gt;- priority transmission&lt;/span&gt;&lt;/div&gt;&lt;div style=&quot;text-align: justify;&quot;&gt;&lt;span style=&quot;background-color: initial;&quot;&gt;- IDLE&lt;/span&gt;&lt;/div&gt;" style="rounded=0;whiteSpace=wrap;html=1;align=center;" parent="1" vertex="1">
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-                </mxCell>
-                <mxCell id="38" value="Red: clocked by cxp_gtx_rx/tx (31.25MHz - 312.5MHz)&amp;nbsp;" style="rounded=0;whiteSpace=wrap;html=1;labelBackgroundColor=none;strokeColor=#b85450;fillColor=#f8cecc;align=left;" parent="1" vertex="1">
-                    <mxGeometry x="120" y="680" width="360" height="40" as="geometry"/>
-                </mxCell>
-                <mxCell id="39" value="Blue: clocked by sys with CEInserter (20.83MHz - 41.66MHz)&amp;nbsp;" style="rounded=0;whiteSpace=wrap;html=1;labelBackgroundColor=none;strokeColor=#6c8ebf;fillColor=#dae8fc;align=left;" parent="1" vertex="1">
-                    <mxGeometry x="120" y="720" width="360" height="40" as="geometry"/>
-                </mxCell>
-                <mxCell id="40" value="White: clocked by sys (125MHz)" style="rounded=0;whiteSpace=wrap;html=1;labelBackgroundColor=none;strokeColor=default;fontColor=#000000;fillColor=default;align=left;" parent="1" vertex="1">
-                    <mxGeometry x="120" y="800" width="360" height="40" as="geometry"/>
-                </mxCell>
-                <mxCell id="43" value="&lt;div style=&quot;text-align: justify;&quot;&gt;&lt;span style=&quot;background-color: initial;&quot;&gt;&lt;b&gt;&lt;u&gt;CXP Bootstrap FW&lt;/u&gt;&lt;/b&gt;&lt;/span&gt;&lt;/div&gt;&lt;div style=&quot;text-align: justify;&quot;&gt;&lt;span style=&quot;background-color: initial;&quot;&gt;- handle GTX speed&lt;/span&gt;&lt;/div&gt;&lt;div style=&quot;text-align: justify;&quot;&gt;&lt;span style=&quot;background-color: initial;&quot;&gt;- test connection&lt;/span&gt;&lt;/div&gt;&lt;div style=&quot;text-align: justify;&quot;&gt;&lt;span style=&quot;background-color: initial;&quot;&gt;- hand over to RTIO after init&lt;/span&gt;&lt;/div&gt;&lt;div style=&quot;text-align: justify;&quot;&gt;&lt;span style=&quot;background-color: initial;&quot;&gt;&lt;span style=&quot;white-space: pre;&quot;&gt;&#9;&lt;/span&gt;- cannot access CTRL PAK&lt;/span&gt;&lt;/div&gt;&lt;div style=&quot;text-align: justify;&quot;&gt;&lt;span style=&quot;background-color: initial;&quot;&gt;- with camera specific .rs file&lt;/span&gt;&lt;/div&gt;&lt;div style=&quot;text-align: justify;&quot;&gt;&lt;span style=&quot;background-color: initial;&quot;&gt;- compare heatbeat to check connection status&lt;/span&gt;&lt;/div&gt;&lt;div style=&quot;text-align: justify;&quot;&gt;&lt;span style=&quot;background-color: initial;&quot;&gt;- handle event ack??&lt;/span&gt;&lt;/div&gt;&lt;div style=&quot;text-align: justify;&quot;&gt;&lt;span style=&quot;background-color: initial;&quot;&gt;- don't use tag?&lt;/span&gt;&lt;/div&gt;" style="rounded=0;whiteSpace=wrap;html=1;align=center;fillColor=#fff2cc;strokeColor=#d6b656;" parent="1" vertex="1">
-                    <mxGeometry x="800" y="240" width="240" height="240" as="geometry"/>
-                </mxCell>
-                <mxCell id="53" value="&lt;div style=&quot;text-align: justify;&quot;&gt;&lt;span style=&quot;background-color: initial;&quot;&gt;&lt;u&gt;&lt;b&gt;CXP Camera specific prog&lt;/b&gt;&lt;/u&gt;&lt;br&gt;GenICam interface @&amp;nbsp;&lt;/span&gt;&lt;/div&gt;&lt;div style=&quot;text-align: justify;&quot;&gt;&lt;span style=&quot;background-color: initial;&quot;&gt;RTIO coredevice&lt;/span&gt;&lt;/div&gt;&lt;div style=&quot;text-align: justify;&quot;&gt;&lt;span style=&quot;background-color: initial;&quot;&gt;- handle frame programming&lt;/span&gt;&lt;/div&gt;&lt;div style=&quot;text-align: justify;&quot;&gt;&lt;span style=&quot;background-color: initial;&quot;&gt;- handle event as well??&lt;/span&gt;&lt;/div&gt;&lt;div style=&quot;text-align: justify;&quot;&gt;&lt;span style=&quot;background-color: initial;&quot;&gt;- two interface&lt;/span&gt;&lt;/div&gt;&lt;div style=&quot;text-align: justify;&quot;&gt;&lt;span style=&quot;background-color: initial;&quot;&gt;&amp;nbsp; &amp;nbsp;- IO CTRL packet via API!&lt;/span&gt;&lt;/div&gt;&lt;div style=&quot;text-align: justify;&quot;&gt;&lt;span style=&quot;background-color: initial;&quot;&gt;&amp;nbsp; &amp;nbsp;- on master ch only&lt;/span&gt;&lt;/div&gt;&lt;div style=&quot;text-align: justify;&quot;&gt;&lt;span style=&quot;background-color: initial;&quot;&gt;&amp;nbsp; &amp;nbsp;- O Frame data&lt;/span&gt;&lt;/div&gt;" style="rounded=0;whiteSpace=wrap;html=1;fillColor=#d5e8d4;strokeColor=#82b366;" parent="1" vertex="1">
-                    <mxGeometry x="1120" y="80" width="160" height="480" as="geometry"/>
-                </mxCell>
-                <mxCell id="54" value="RX pipeline" style="rounded=0;whiteSpace=wrap;html=1;fillColor=#f8cecc;strokeColor=#b85450;" parent="1" vertex="1">
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-                <mxCell id="71" value="&lt;div style=&quot;text-align: justify;&quot;&gt;&lt;span style=&quot;background-color: initial;&quot;&gt;TX Bootstrap&lt;/span&gt;&lt;/div&gt;&lt;div style=&quot;text-align: justify;&quot;&gt;&lt;span style=&quot;background-color: initial;&quot;&gt;- testseq&lt;/span&gt;&lt;br&gt;&lt;/div&gt;&lt;div style=&quot;text-align: justify;&quot;&gt;&lt;span style=&quot;background-color: initial;&quot;&gt;- DMA&lt;/span&gt;&lt;/div&gt;" style="rounded=0;whiteSpace=wrap;html=1;align=center;" parent="1" vertex="1">
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-                <mxCell id="185" value="&lt;div style=&quot;&quot;&gt;&lt;span style=&quot;background-color: initial;&quot;&gt;- 32bit pixel data&lt;/span&gt;&lt;/div&gt;- frame valid (new frame)&lt;br&gt;- line break" style="text;html=1;align=left;verticalAlign=middle;resizable=0;points=[];autosize=1;strokeColor=none;fillColor=none;" parent="1" vertex="1">
-                    <mxGeometry x="1520" y="-430" width="160" height="60" as="geometry"/>
-                </mxCell>
-                <mxCell id="186" value="CRC Checker" style="rounded=0;whiteSpace=wrap;html=1;fillColor=#f8cecc;strokeColor=#b85450;" parent="1" vertex="1">
-                    <mxGeometry x="920" y="-360.42" width="80" height="80" as="geometry"/>
-                </mxCell>
-                <mxCell id="187" value="" style="edgeStyle=none;orthogonalLoop=1;jettySize=auto;html=1;" parent="1" edge="1">
-                    <mxGeometry width="100" relative="1" as="geometry">
-                        <mxPoint x="1000" y="-321.25000000000017" as="sourcePoint"/>
-                        <mxPoint x="1080" y="-320.87000000000006" as="targetPoint"/>
-                        <Array as="points"/>
-                    </mxGeometry>
-                </mxCell>
-                <mxCell id="188" value="Double&lt;br&gt;Buffered&lt;br&gt;Memory" style="rounded=0;whiteSpace=wrap;html=1;fillColor=#f8cecc;strokeColor=#b85450;" parent="1" vertex="1">
-                    <mxGeometry x="1080" y="-360.42" width="80" height="80" as="geometry"/>
-                </mxCell>
-                <mxCell id="194" value="Pixel Decoder" style="rounded=0;whiteSpace=wrap;html=1;fillColor=#fad9d5;strokeColor=#ae4132;" parent="1" vertex="1">
-                    <mxGeometry x="1400" y="-360" width="80" height="80" as="geometry"/>
-                </mxCell>
-                <mxCell id="195" value="&lt;div style=&quot;&quot;&gt;&lt;span style=&quot;background-color: initial;&quot;&gt;- extract line break &amp;amp; new frame&lt;/span&gt;&lt;/div&gt;" style="text;html=1;align=left;verticalAlign=middle;resizable=0;points=[];autosize=1;strokeColor=none;fillColor=none;" parent="1" vertex="1">
-                    <mxGeometry x="1400" y="-270" width="190" height="30" as="geometry"/>
-                </mxCell>
-                <mxCell id="203" value="" style="edgeStyle=none;orthogonalLoop=1;jettySize=auto;html=1;" parent="1" edge="1">
-                    <mxGeometry width="100" relative="1" as="geometry">
-                        <mxPoint x="1160" y="-319.9999999999999" as="sourcePoint"/>
-                        <mxPoint x="1240" y="-319.6199999999998" as="targetPoint"/>
-                        <Array as="points"/>
-                    </mxGeometry>
-                </mxCell>
-                <mxCell id="205" value="" style="edgeStyle=none;orthogonalLoop=1;jettySize=auto;html=1;" parent="1" edge="1">
-                    <mxGeometry width="100" relative="1" as="geometry">
-                        <mxPoint x="840" y="-320.4200000000002" as="sourcePoint"/>
-                        <mxPoint x="920" y="-320.0400000000001" as="targetPoint"/>
-                        <Array as="points"/>
-                    </mxGeometry>
-                </mxCell>
-                <mxCell id="206" value="CRC Checker" style="rounded=0;whiteSpace=wrap;html=1;fillColor=#f8cecc;strokeColor=#b85450;dashed=1;" parent="1" vertex="1">
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-                </mxCell>
-                <mxCell id="207" value="" style="edgeStyle=none;orthogonalLoop=1;jettySize=auto;html=1;dashed=1;" parent="1" edge="1">
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-                        <mxPoint x="1000" y="-440.83000000000027" as="sourcePoint"/>
-                        <mxPoint x="1080" y="-440.45000000000016" as="targetPoint"/>
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-                    <mxGeometry x="1080" y="-480" width="80" height="80" as="geometry"/>
-                </mxCell>
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-                        <mxPoint x="760" y="-279.62000000000006" as="targetPoint"/>
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-                        <mxPoint x="760" y="-359.62000000000006" as="targetPoint"/>
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-                    </mxGeometry>
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-                        <mxPoint x="760" y="-200.11000000000007" as="targetPoint"/>
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-                        <mxPoint x="920" y="-440.04000000000025" as="targetPoint"/>
-                        <Array as="points"/>
-                    </mxGeometry>
-                </mxCell>
-                <mxCell id="214" value="Stream&lt;br&gt;Parser" style="rounded=0;whiteSpace=wrap;html=1;fillColor=#f8cecc;strokeColor=#b85450;" parent="1" vertex="1">
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-                <mxCell id="215" value="" style="edgeStyle=none;orthogonalLoop=1;jettySize=auto;html=1;" parent="1" edge="1">
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-                        <mxPoint x="1400" y="-320.03999999999985" as="targetPoint"/>
-                        <Array as="points"/>
-                    </mxGeometry>
-                </mxCell>
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-                </mxCell>
-                <mxCell id="217" value="Stream pipeline #1" style="rounded=0;whiteSpace=wrap;html=1;fillColor=#f8cecc;strokeColor=#b85450;" vertex="1" parent="1">
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-                </mxCell>
-                <mxCell id="218" value="" style="edgeStyle=none;orthogonalLoop=1;jettySize=auto;html=1;" edge="1" parent="1">
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-                        <mxPoint x="880" y="119.57999999999993" as="sourcePoint"/>
-                        <mxPoint x="960" y="119.96000000000004" as="targetPoint"/>
-                        <Array as="points"/>
-                    </mxGeometry>
-                </mxCell>
-            </root>
-        </mxGraphModel>
-    </diagram>
-</mxfile>

cxp_kernel.py

@@ -1,375 +0,0 @@
-"""
-Non-realtime drivers for CXP.
-"""
-
-# TODO: add api calls for CTRL packet similar i2c
-# TODO: add timing critical trigger ack
-
-from numpy import int32, int64, uint32
-
-from artiq.language.core import syscall, kernel
-from artiq.language.types import TInt32, TNone, TByteArray
-from artiq.coredevice.rtio import rtio_output,rtio_input_timestamped_data
-from artiq.coredevice.grabber import OutOfSyncException, GrabberTimeoutException
-from artiq.experiment import *
-
-@syscall(flags={"nounwind", "nowrite"})
-def cxp_read_chars(addr: TInt32, val: TByteArray) -> TInt32:
-    raise NotImplementedError("syscall not simulated")
-
-
-@syscall(flags={"nounwind", "nowrite"})
-def cxp_readu32(addr: TInt32) -> TInt32:
-    raise NotImplementedError("syscall not simulated")
-
-
-@syscall(flags={"nounwind", "nowrite"})
-def cxp_readu64(addr: TInt32) -> TInt64:
-    raise NotImplementedError("syscall not simulated")
-
-
-@syscall(flags={"nounwind", "nowrite"})
-def cxp_writeu32(addr: TInt32, val: TInt32) -> TNone:
-    raise NotImplementedError("syscall not simulated")
-
-
-@syscall(flags={"nounwind", "nowrite"})
-def cxp_writeu64(addr: TInt32, val: TInt64) -> TNone:
-    raise NotImplementedError("syscall not simulated")
-
-
-@syscall(flags={"nounwind", "nowrite"})
-def cxp_debug_frame_print() -> TNone:
-    raise NotImplementedError("syscall not simulated")
-
-
-# Bootstrap register
-_XML_MANIFEST_SIZE = 0x0008
-_XML_MANIFEST_SEL = 0x000C
-_XML_VER = 0x0010
-_XML_SCHEMA_VER = 0x0014
-_XML_URL_ADDR = 0x0018
-_WIDTH_ADDR = 0x3000
-_HEIGHT_ADDR = 0x3004
-_ACQUISITION_MODE_ADDR = 0x3008
-_ACQUISITION_START_ADDR = 0x300C
-_ACQUISITION_STOP_ADDR = 0x3010
-_PIXEL_FORMAT_ADDR = 0x3014
-_DEVICE_TAP_GEOG_ADDR = 0x3018
-_IMG_1_STREAMID_ADDR = 0x301C
-
-_MAX_BYTE_SIZE = 100
-
-class CoaXPress:
-    def __init__(self, channel_base, core_device="core"):
-        # __device_mgr is private
-        # self.core = dmgr.get(core_device)
-
-        # you can get the channel via `print(len(rtio_channels))` before calling
-        # `rtio_channels.append(rtio.Channel.from_phy(cxp_interface))`
-        self.channel_base = channel_base
-        # ch base + 0: trigger
-        # ch base + 1: roi config
-        # ch base + 2: gate data
-
-        # the first 8 bits is reserved for the rtlink.OInterface.addr not for channel no.
-        self.target_o = channel_base << 8
-
-        self.xml_addr = 0
-        self.width_addr = 0
-        self.height_addr = 0
-        self.acq_mode_addr = 0
-        self.acq_start_addr = 0
-        self.acq_stop_addr = 0
-        self.pixel_fmt_addr = 0
-        self.device_tap_geog_addr = 0
-        self.img_1_streamid_addr = 0
-
-        self.xml_url = bytearray(_MAX_BYTE_SIZE)
-
-        self.econ_roi = False
-
-        count_width = 31
-        # This value is inserted by the gateware to mark the start of a series of
-        # ROI engine outputs for one video frame.
-        self.sentinel = int32(int64(2**count_width))
-
-    @staticmethod
-    def get_rtio_channels(channel, **kwargs):
-        return [(channel, None)]
-
-    @kernel
-    def trigger(self, linktrig, trigdelay):
-        rtio_output(self.channel_base << 8, linktrig | trigdelay << 1)
-
-    @kernel
-    def setup_roi(self, n, x0, y0, x1, y1):
-        if self.econ_roi:
-            assert x1-x0 >= 4
-        # DEBUG:
-        # c = int64(self.core.ref_multiplier)
-        c = int64(8)
-        rtio_output(((self.channel_base + 1) << 8) | (4*n+0), x0)
-        delay_mu(c)
-        rtio_output(((self.channel_base + 1) << 8) | (4*n+1), y0)
-        delay_mu(c)
-        rtio_output(((self.channel_base + 1) << 8) | (4*n+2), x1)
-        delay_mu(c)
-        rtio_output(((self.channel_base + 1) << 8) | (4*n+3), y1)
-        delay_mu(c)
-
-    @kernel
-    def gate_roi(self, mask):
-        rtio_output((self.channel_base + 2) << 8, mask)
-
-    @kernel
-    def input_mu(self, data, tt, timeout_mu=-1):
-        assert len(data) == len(tt)
-        channel = self.channel_base + 2
-
-        # TODO: add timeout error and sentinel error
-        timestamp, sentinel = rtio_input_timestamped_data(timeout_mu, channel)
-        if timestamp == -1:
-            raise GrabberTimeoutException("Timeout before Grabber frame available")
-        if sentinel != self.sentinel:
-            raise OutOfSyncException
-
-        for i in range(len(data)):
-            timestamp, roi_output = rtio_input_timestamped_data(timeout_mu, channel)
-            if roi_output == self.sentinel:
-                raise OutOfSyncException
-            if timestamp == -1:
-                raise GrabberTimeoutException(
-                    "Timeout retrieving ROIs (attempting to read more ROIs than enabled?)")
-            data[i] = roi_output
-            tt[i] = timestamp
-
-    @kernel
-    def init(self):
-        self.xml_addr = self.read_u32(_XML_URL_ADDR)
-        # self.width_addr = self.read_u32(_WIDTH_ADDR)
-        # self.height_addr = self.read_u32(_HEIGHT_ADDR)
-        self.acq_mode_addr = self.read_u32(_ACQUISITION_MODE_ADDR)
-        self.acq_start_addr = self.read_u32(_ACQUISITION_START_ADDR)
-        self.acq_stop_addr = self.read_u32(_ACQUISITION_STOP_ADDR)
-        self.pixel_fmt_addr = self.read_u32(_PIXEL_FORMAT_ADDR)
-        # self.device_tap_geog_addr = self.read_u32(_DEVICE_TAP_GEOG_ADDR)
-        self.img_1_streamid_addr = self.read_u32(_IMG_1_STREAMID_ADDR)
-
-        self.read_chars(self.xml_addr, self.xml_url)
-
-    @kernel
-    def read_chars(self, addr: TInt32, val: TByteArray):
-        cxp_read_chars(addr, val)
-
-    @kernel
-    def read_u32(self, addr: TInt32) -> TInt32:
-        return cxp_readu32(addr)
-
-    @kernel
-    def read_u64(self, addr: TInt32) -> TInt64:
-        return cxp_readu64(addr)
-
-    @kernel
-    def read_words(self, addr: TInt32, val: TList(TInt32)):
-        cxp_read_words(addr, val)
-
-    @kernel
-    def write_u32(self, addr: TInt32, val: TInt32):
-        cxp_writeu32(addr, val)
-
-    @kernel
-    def write_u64(self, addr: TInt32, val: TInt64):
-        cxp_writeu64(addr, val)
-
-    @kernel
-    def write_wide(self, addr: TInt32, vals: TList(TInt32)):
-        for i in range(len(vals)):
-            cxp_writeu32(addr + i * 4, vals[i])
-
-    @host_only
-    def print_xml_url(self):
-        url = self.xml_url.decode("ascii")
-        if "Local:" in url:
-            file_name, start_addr, size = url.split(";", 2)
-            print(
-                f"file name: {file_name.replace("Local:", "")}, start addr: 0x{start_addr}, size: 0x{size.split("?", 1)[0]} bytes"
-            )
-        else:
-            print(self.xml_url.decode("ascii"))
-
-    @kernel
-    def get_xml_data(self, start_addr, data):
-        addr_offset = 0
-        for i in range(len(data) // _MAX_BYTE_SIZE):
-            buf = bytearray([0x00]*_MAX_BYTE_SIZE)
-            self.read_chars(start_addr + addr_offset, buf)
-            for j in range(len(buf)):
-                data[addr_offset + j] = buf[j]
-            addr_offset += _MAX_BYTE_SIZE
-
-        if len(data) % _MAX_BYTE_SIZE:
-            leftover = len(data) % _MAX_BYTE_SIZE
-            buf = bytearray([0x00]*leftover)
-            self.read_chars(start_addr + addr_offset, buf)
-            for j in range(len(buf)):
-                data[addr_offset + j] = buf[j]
-
-    @host_only
-    def write_xml_file(self, data, file_path):
-        with open(file_path, "wb") as binary_file:
-            binary_file.write(data)
-
-
-# From the camera XML files
-_USER_SET_SELECTOR = 0x10000050
-_REAL_ACQ_MODE = 0x10000bb4
-_REAL_ACQ_START = 0x10000498
-_REAL_ACQ_STOP = 0x100004a4
-_REAL_ACQ_ABORT = 0x100004b0 #stop all acq immediately
-_BSL_SENSOR_ON = 0x100004d4 # power on sensor
-_BSL_SENSOR_STAND_BY = 0x100004c8 # put sensor in standby mode, certain parameter can only be change during standby
-_BSL_SENSOR_OFF = 0x100004bc # power down sensor
-_BSL_POWER_MODE = 0x100000b4
-# strange d_470 -> d_469 (= 3) perhaps a obscure security trick? So I guess looking @ Index"3" is fine?
-_TRIG_MODE_INDEX_3 = 0x10001424 # d_87
-_TRIG_SRC_INDEX_3 = 0x100081ac # d_479
-_TRIG_ACT_INDEX_3 = 0x1000293c # d_502
-_TRIG_SOFTWARE_INDEX_3 = 0x10000c34 # d_525
-# https://docs.baslerweb.com/test-patterns useful for testing out ROI
-_TEST_PATTERN = 0x10003500 # d_1431
-_PIXEL_FORMAT = 0x100078b4 #d_17
-
-CXP_TRIG = True
-PIXELFORMAT = "MONO8"
-FORMAT_DICT = {
-    "MONO8": 17301505,
-    "MONO10": 17825795,
-    "MONO12": 17825797,
-}
-TESTPATTERN = "WHITE"
-PATTERN_DICT = {
-    "OFF" : 0, # normal operation
-    "BLACK" : 1, # all pixels set to 0
-    "WHITE" : 2, # all pixels set to (2^N)-1
-}
-
-class IdleKernel(EnvExperiment):
-    def build(self):
-        self.setattr_device("core")
-        self.setattr_device("led0")
-
-        # declare the class before using it in kernel
-        self.cxp = CoaXPress(0x0)
-
-        self.vals = bytearray(0x11ab3)
-
-        self.gate_mask = 0b11011
-        self.cnt = [0]*self.gate_mask.bit_count()
-        self.timestamp = [int64(0)]*self.gate_mask.bit_count()
-
-    @kernel
-    def extract_camera_xml(self):
-        self.cxp.get_xml_data(0xc0000000, self.vals)
-
-    @kernel
-    def camera_init(self):
-        self.cxp.init()
-
-    @kernel
-    def camera_trigger_setup(self, pixel_format, test_pattern):
-        # DEBUG: Try to setup trigger
-        # All address below is from the XML, what's the point of bootstrap anyway?
-        # NOTE: setting is persistent over ConnectionReset but NOT power cycle
-        # self.cxp.write_u32(_REAL_ACQ_MODE, 1) # single frame mode
-        # self.cxp.write_u32(_REAL_ACQ_START, 1) # single acq start
-        # self.cxp.write_u32(_REAL_ACQ_STOP, 1) # single acq end
-        # self.cxp.write_u32(_REAL_ACQ_ABORT, 1) # single acq ABORT
-
-        # boA2448-250cm is area scan camera:
-        # see https://docs.baslerweb.com/triggered-image-acquisition#hardware-and-software-triggering to setup triggering properly
-        
-        self.cxp.write_u32(_PIXEL_FORMAT, pixel_format)
-        
-        # TEST parttern setup 
-        self.cxp.write_u32(_TEST_PATTERN, test_pattern)
-
-        # TRIGGER: setup
-        # self.cxp.write_u32(_TRIG_SELECTOR, 3) # FrameStart by default, boA xml b_469 don't have an address for some reason
-        self.cxp.write_u32(_TRIG_MODE_INDEX_3, 1) # ON
-        if CXP_TRIG:
-            self.cxp.write_u32(_TRIG_SRC_INDEX_3, 7) # CXPTrigger0
-        else:
-            self.cxp.write_u32(_TRIG_SRC_INDEX_3, 0) # use software trigger 
-        self.cxp.write_u32(_TRIG_ACT_INDEX_3, 2) # trig on anyedge
-        
-        # cxp_debug_frame_print()
-
-        # TAKING PICTURE
-        self.cxp.write_u32(_REAL_ACQ_MODE, 1) # single frame mode
-        self.cxp.write_u32(_REAL_ACQ_START, 1) # single acq start
-
-        # STOP acq
-        # self.cxp.write_u32(_REAL_ACQ_STOP, 1) # single acq end
-        # self.cxp.write_u32(_REAL_ACQ_ABORT, 1) # single acq ABORT
-        
-        # self.cxp.write_u32(_BSL_SENSOR_STAND_BY, 1)
-        return self.cxp.read_u32(_BSL_POWER_MODE)
-
-    @kernel
-    def camera_trigger(self):
-        # reset mu for rtio
-        self.core.reset()
-        self.core.break_realtime()
-
-        self.cxp.setup_roi(0, 1, 1, 5, 5)
-        self.cxp.setup_roi(1, 1, 1, 4, 4)
-        self.cxp.setup_roi(2, 1, 1, 3, 3)
-        self.cxp.setup_roi(3, 1, 1, 4, 4)
-        self.cxp.setup_roi(4, 1, 1, 5, 5)
-        self.cxp.gate_roi(self.gate_mask)
-        delay_mu(1000000)
-        
-        if CXP_TRIG:
-            self.cxp.trigger(0 ,0x00)
-        else:
-            self.cxp.write_u32(_TRIG_SOFTWARE_INDEX_3, 0) # software trigger via register write
-
-        delay_mu(100)
-        
-        # self.cxp.write_u32(_REAL_ACQ_STOP, 1) # single acq end
-        # self.cxp.write_u32(_REAL_ACQ_ABORT, 1) # single acq ABORT
-        # self.cxp.write_u32(_BSL_SENSOR_STAND_BY, 1)
-         
-        # NOTE: This may not print when using CXP hardware TRIG
-        # As the write_u32 trigger a packet printout that delays the CPU enough that the frame arrive
-        # But using hw trigger, the print is not necessory i.e. not enough time delay for the zc706 to receive the frame
-        # cxp_debug_frame_print()
-
-        self.cxp.input_mu(self.cnt, self.timestamp, -1)
-
-        # for _ in range(4):
-        #     cxp_debug_frame_print()
-        
-        # reduce power draw & temperature
-        # overtemperature can cause unstable connection
-        self.cxp.write_u32(_BSL_SENSOR_OFF, 1) 
-
-        return self.cxp.read_u32(_BSL_POWER_MODE)
-
-    def print_hex(self, arr: TList(TInt32)):
-        print("[{}]".format(", ".join(hex(uint32(x)) for x in arr)))
-
-    def run(self):
-        self.camera_init()
-
-        for fmt in FORMAT_DICT:
-            print(f"set pixel format to {fmt}")
-            print(f"power mode before trigger = {self.camera_trigger_setup(FORMAT_DICT[fmt], PATTERN_DICT[TESTPATTERN])}")
-            print(f"power mode after trigger = {self.camera_trigger()}")
-            print(f"count = {uint32(self.cnt)} | timestamp = {self.timestamp}")
-
-        
-        # self.cxp.print_xml_url()
-        # self.extract_camera_xml()
-        # self.cxp.write_xml_file(self.vals, "hello.zip")

cxp_note.md

@@ -1,89 +0,0 @@
-# CXP
-
-## Finished
-- Upconn - Low speed serial 
-  [x] Low speed serial PHY
-    [x] 20.833Mbps & 41.666Mbps change
-    [x] 8b10b encoder
-  [x] TX Pipeline with priority transmission
-    [x] Trigger
-    [x] Trigger ack
-    [x] Test & Ctrl packet with DMA
-  [x] CTRL Packet serialize firmware
-    [x] follow DRTIO DMA
-    [x] check crc
-- Downconn - GTX
-  [x] GTX serial PHY
-    [x] QPLL & GTX DRP to config linerate
-    [x] Comma checker & restart rx
-  [x] RX Pipeline with priority decoder
-    [x] Trigger ack 
-    [x] CTRL packet DMA with extra buffer
-    [x] Connection test sequence checker
-  [x] CTRL Packet deserialize firmware
-    [x] follow DRTIO DMA
-    [x] check crc
-  [x] GTX Multilane setup
-    [x] add tx/rx mode for gtx 
-- Camera boostrap
-  [x] get the CXP version
-  [x] test connection
-  [x] discovery other extension (links)
-  [x] set bitrate
-- Camera frame pipeline
-  [x] CXP frame packet routing (maybe no need to routing non zero streaming id (we have ROI buildin anyways)?)
-  [x] CXP CRC32 detection
-  [x] Region of interest engine (32 bits mode)
-      [x] pixel gearbox
-      [x] pixel parser (xy pos)
-      [x] Test out CXP trigger
-        [x] 8, 10, 12 bits in white test image mode
-
-
-## TODO
-[] remove ALL debug tools
-  [] flake.nix mod
-  [] local_run.sh mod
-### Gateware
-[x] refactor error_cnt 
-[x] Heartbeat (is it useful?? lol)
-[x] rename circular buffer to slots
-[x] use `from misoc.interconnect.stream import Endpoint` instead
-[x] add __init__.py for cxp??
-[] Try to fix tight s/h time pins
-[] remove self.source.ack in fsm
-  - seems to kill timing :V
-[] multilane ROI
-  [] Region of interest engine (n*32 bits mode)
-  [] bus widener + fifo
-[] remove pmod/debug_sma in fns args
-[] rtio to getting the frame
-  - O: trigger
-  - I: frame
-
-### Firmware (design with driver)
-[x] API programming
-[x] add tag handling for api calls
-  - support lane reset in kernel using syscall
-[] double check cfg gating
-  [] add libboard_artiq/src/lib.rs cfg gating
-[] Camera auto linkup/linkdown using threads
-  [] Camera linkdown detection
-  [] add mutex support for tx/rx camera programming (or block them when camera is not ready)
-  [] add xml url printout in uart (so user can just download the xml using api)
-  [] add heartbeat checking
-[] add flashing LED (non-essential)
-[] add PoCXP (non-essential)
-
-### Coredevice Driver
-[x] use camera test pattern black/white to verify roi https://docs.baslerweb.com/test-patterns
-[x] test out 8/10/12 bit mode
-[] support simple camera programming interface (Not real time)
-  - basic i2c-like interface with read/write u32
-[] add grabber like fns & docs
-
-
-### PR
-1. push the gtx init fix
-2. push the cxp core to misoc
-3. push the cxp rtio core to artiq-zynq & artiq

device_db.py

@@ -1,30 +0,0 @@
-device_db = {
-    "core": {
-        "type": "local",
-        "module": "artiq.coredevice.core",
-        "class": "Core",
-        "arguments": {
-            "host": "192.168.1.14",
-            "ref_period": 1e-9,
-            "ref_multiplier": 8,
-            "target": "cortexa9"
-        }
-    },
-    "core_cache": {
-        "type": "local",
-        "module": "artiq.coredevice.cache",
-        "class": "CoreCache"
-    },
-    "core_dma": {
-        "type": "local",
-        "module": "artiq.coredevice.dma",
-        "class": "CoreDMA"
-    },
-
-    "led0": {
-        "type": "local",
-        "module": "artiq.coredevice.ttl",
-        "class": "TTLOut",
-        "arguments": {"channel": 0x000001},
-    },
-}

flake.lock

@@ -11,11 +11,11 @@
         "src-pythonparser": "src-pythonparser"
       },
       "locked": {
-        "lastModified": 1736946744,
+        "lastModified": 1739502015,
-        "narHash": "sha256-RKqrWcJfkLlm5JYVfz46KOVg1FYch1pNkKDpW5VzehU=",
+        "narHash": "sha256-IrFzxGNbi6V4SVNb49T9ZXFZDZPA65hdPkfoVmDhBHs=",
         "ref": "refs/heads/master",
-        "rev": "33c91d73bb768a06fa427c237b124916261c5ab9",
+        "rev": "994f60edd5bb646ad4c29744c471a70b8fa6046e",
-        "revCount": 9135,
+        "revCount": 9158,
         "type": "git",
         "url": "https://github.com/m-labs/artiq.git"
       },
@@ -70,11 +70,11 @@
     },
     "nixpkgs": {
       "locked": {
-        "lastModified": 1736798957,
+        "lastModified": 1739446958,
-        "narHash": "sha256-qwpCtZhSsSNQtK4xYGzMiyEDhkNzOCz/Vfu4oL2ETsQ=",
+        "narHash": "sha256-+/bYK3DbPxMIvSL4zArkMX0LQvS7rzBKXnDXLfKyRVc=",
         "owner": "NixOS",
         "repo": "nixpkgs",
-        "rev": "9abb87b552b7f55ac8916b6fc9e5cb486656a2f3",
+        "rev": "2ff53fe64443980e139eaa286017f53f88336dd0",
         "type": "github"
       },
       "original": {
@@ -158,11 +158,11 @@
     "src-migen": {
       "flake": false,
       "locked": {
-        "lastModified": 1735131698,
+        "lastModified": 1738906518,
-        "narHash": "sha256-P4vaF+9iVekRAC2/mc9G7IwI6baBpPAxiDQ8uye4sAs=",
+        "narHash": "sha256-GproDJowtcgbccsT+I0mObzFhE483shcS8MSszKXwlc=",
         "owner": "m-labs",
         "repo": "migen",
-        "rev": "4c2ae8dfeea37f235b52acb8166f12acaaae4f7c",
+        "rev": "2828df54594673653a641ab551caf6c6b1bfeee5",
         "type": "github"
       },
       "original": {
@@ -174,11 +174,11 @@
     "src-misoc": {
       "flake": false,
       "locked": {
-        "lastModified": 1736416570,
+        "lastModified": 1739436988,
-        "narHash": "sha256-tbcN/fzejZIaYbTbwk8Ir1glYevESqMinMeDB3z8oxg=",
+        "narHash": "sha256-zEihEV6kqRtrZWyu7uCNyHOXE/rluVloPuT4ECYVJ+g=",
         "ref": "refs/heads/master",
-        "rev": "1f5318e9edc1085ac77e9b85b8f5e03371dba54c",
+        "rev": "e3f4fd040b90b05d580bf578ca49244f0b7d861a",
-        "revCount": 2464,
+        "revCount": 2483,
         "submodules": true,
         "type": "git",
         "url": "https://github.com/m-labs/misoc.git"
@@ -229,11 +229,11 @@
         "rust-overlay": "rust-overlay_2"
       },
       "locked": {
-        "lastModified": 1734668221,
+        "lastModified": 1739756131,
-        "narHash": "sha256-X0U2yPmlsD3VLBZQyfWv8qw04Qn0qFWIONJUPPigB0U=",
+        "narHash": "sha256-pSRdhgBSi75cYB9PweNwsJk00/ksLpwt39NoG/43WEE=",
         "ref": "refs/heads/master",
-        "rev": "213529cf7a50aa1b2d9ffdf575e3e38202ff9bd6",
+        "rev": "4f90c61442c5b64acf149b1837aa9a5aa7659a38",
-        "revCount": 666,
+        "revCount": 680,
         "type": "git",
         "url": "https://git.m-labs.hk/m-labs/zynq-rs"
       },

flake.nix

@@ -134,14 +134,14 @@
         nativeBuildInputs = [
           pkgs.gnumake
           (pkgs.python3.withPackages(ps: [ ps.jsonschema artiqpkgs.migen migen-axi artiqpkgs.misoc artiqpkgs.artiq ]))
-          zynqpkgs.cargo-xbuild
+          pkgs.cargo-xbuild
-          pkgs.llvmPackages_13.llvm
+          pkgs.llvmPackages_14.llvm
-          pkgs.llvmPackages_13.clang-unwrapped
+          pkgs.llvmPackages_14.clang-unwrapped
         ];
         buildPhase = ''
           export ZYNQ_REV=${zynqRev}
           export XARGO_RUST_SRC="${rust}/lib/rustlib/src/rust/library"
-          export CLANG_EXTRA_INCLUDE_DIR="${pkgs.llvmPackages_13.clang-unwrapped.lib}/lib/clang/13.0.1/include"
+          export CLANG_EXTRA_INCLUDE_DIR="${pkgs.llvmPackages_14.clang-unwrapped.lib}/lib/clang/14.0.6/include"
           export CARGO_HOME=$(mktemp -d cargo-home.XXX)
           export ZYNQ_RS=${zynq-rs}
           make TARGET=${target} GWARGS="${if json == null then "-V ${variant}" else json}" ${fwtype}
@@ -345,7 +345,6 @@
       {
         inherit fastnumbers artiq-netboot ramda migen-axi binutils-arm;
       } //
-      (board-package-set { target = "zc706"; variant = "cxp_grabber"; }) //
       (board-package-set { target = "zc706"; variant = "nist_clock"; }) //
       (board-package-set { target = "zc706"; variant = "nist_clock_master"; }) //
       (board-package-set { target = "zc706"; variant = "nist_clock_master_100mhz"; }) //
@@ -377,11 +376,11 @@
       name = "artiq-zynq-dev-shell";
       buildInputs = with pkgs; [
         rust
-        llvmPackages_13.llvm
+        llvmPackages_14.llvm
-        llvmPackages_13.clang-unwrapped
+        llvmPackages_14.clang-unwrapped
         gnumake
         cacert
-        zynqpkgs.cargo-xbuild
+        pkgs.cargo-xbuild
         zynqpkgs.mkbootimage
         openocd  
         openssh rsync
@@ -393,7 +392,7 @@
       ];
       ZYNQ_REV="${zynqRev}";
       XARGO_RUST_SRC = "${rust}/lib/rustlib/src/rust/library";
-      CLANG_EXTRA_INCLUDE_DIR = "${pkgs.llvmPackages_13.clang-unwrapped.lib}/lib/clang/13.0.1/include";
+      CLANG_EXTRA_INCLUDE_DIR = "${pkgs.llvmPackages_14.clang-unwrapped.lib}/lib/clang/14.0.6/include";
       ZYNQ_RS = "${zynq-rs}";
       OPENOCD_ZYNQ = "${zynq-rs}/openocd";
       SZL = "${zynqpkgs.szl}";

local_run.sh

@@ -13,7 +13,7 @@ fi
 
 impure=0
 load_bitstream=1
-board_type="zc706"
+board_type="kasli_soc"
 fw_type="runtime"
 
 while getopts "ilb:t:f:" opt; do
@@ -36,7 +36,7 @@ done
 if [ -z "$board_host" ]; then
     case $board_type in
     kasli_soc) board_host="192.168.1.56";;
-    zc706) board_host="192.168.1.14";;
+    zc706) board_host="192.168.1.52";;
     *) echo "Unknown board type"; exit 1;;
     esac
 fi
@@ -58,4 +58,4 @@ else
         load_bitstream_cmd="-g $result_dir/top.bit"
     fi
     artiq_netboot $load_bitstream_cmd -f $result_dir/$fw_type.bin -b $board_host
-fi
+fi

notes.drawio

@@ -1,82 +0,0 @@
-<mxfile host="65bd71144e">
-    <diagram id="en7HUHNV3kVsTTCxeEt8" name="Page-1">
-        <mxGraphModel dx="924" dy="545" grid="1" gridSize="10" guides="1" tooltips="1" connect="1" arrows="1" fold="1" page="0" pageScale="1" pageWidth="850" pageHeight="1100" background="none" math="0" shadow="0">
-            <root>
-                <mxCell id="0"/>
-                <mxCell id="1" parent="0"/>
-                <mxCell id="50" value="" style="shape=flexArrow;endArrow=classic;html=1;fillColor=#647687;strokeColor=#314354;" edge="1" parent="1">
-                    <mxGeometry width="50" height="50" relative="1" as="geometry">
-                        <mxPoint x="280" y="200" as="sourcePoint"/>
-                        <mxPoint x="440" y="200" as="targetPoint"/>
-                    </mxGeometry>
-                </mxCell>
-                <mxCell id="52" value="Payload (layout)" style="edgeLabel;html=1;align=center;verticalAlign=middle;resizable=0;points=[];" vertex="1" connectable="0" parent="50">
-                    <mxGeometry x="-0.8404" y="-1" relative="1" as="geometry">
-                        <mxPoint x="-63" as="offset"/>
-                    </mxGeometry>
-                </mxCell>
-                <mxCell id="53" value="" style="shape=flexArrow;endArrow=classic;html=1;fillColor=#647687;strokeColor=#314354;" edge="1" parent="1">
-                    <mxGeometry width="50" height="50" relative="1" as="geometry">
-                        <mxPoint x="280" y="239.81" as="sourcePoint"/>
-                        <mxPoint x="440" y="239.81" as="targetPoint"/>
-                    </mxGeometry>
-                </mxCell>
-                <mxCell id="54" value="stb (valid/readable)" style="edgeLabel;html=1;align=center;verticalAlign=middle;resizable=0;points=[];" vertex="1" connectable="0" parent="53">
-                    <mxGeometry x="-0.8404" y="-1" relative="1" as="geometry">
-                        <mxPoint x="-63" y="-1" as="offset"/>
-                    </mxGeometry>
-                </mxCell>
-                <mxCell id="55" value="" style="shape=flexArrow;endArrow=classic;html=1;fillColor=#647687;strokeColor=#314354;" edge="1" parent="1">
-                    <mxGeometry width="50" height="50" relative="1" as="geometry">
-                        <mxPoint x="440" y="279.80999999999995" as="sourcePoint"/>
-                        <mxPoint x="280" y="279.80999999999995" as="targetPoint"/>
-                    </mxGeometry>
-                </mxCell>
-                <mxCell id="56" value="ack (ready)" style="edgeLabel;html=1;align=center;verticalAlign=middle;resizable=0;points=[];" vertex="1" connectable="0" parent="55">
-                    <mxGeometry x="-0.8404" y="-1" relative="1" as="geometry">
-                        <mxPoint x="-197" y="1" as="offset"/>
-                    </mxGeometry>
-                </mxCell>
-                <mxCell id="48" value="Source" style="rounded=0;whiteSpace=wrap;html=1;fillColor=#d5e8d4;strokeColor=#82b366;" vertex="1" parent="1">
-                    <mxGeometry x="320" y="160" width="80" height="160" as="geometry"/>
-                </mxCell>
-                <mxCell id="57" value="" style="shape=flexArrow;endArrow=classic;html=1;fillColor=#647687;strokeColor=#314354;" edge="1" parent="1">
-                    <mxGeometry width="50" height="50" relative="1" as="geometry">
-                        <mxPoint x="520" y="200" as="sourcePoint"/>
-                        <mxPoint x="680" y="200" as="targetPoint"/>
-                    </mxGeometry>
-                </mxCell>
-                <mxCell id="58" value="Payload (layout)" style="edgeLabel;html=1;align=center;verticalAlign=middle;resizable=0;points=[];" vertex="1" connectable="0" parent="57">
-                    <mxGeometry x="-0.8404" y="-1" relative="1" as="geometry">
-                        <mxPoint x="197" as="offset"/>
-                    </mxGeometry>
-                </mxCell>
-                <mxCell id="59" value="" style="shape=flexArrow;endArrow=classic;html=1;fillColor=#647687;strokeColor=#314354;" edge="1" parent="1">
-                    <mxGeometry width="50" height="50" relative="1" as="geometry">
-                        <mxPoint x="520" y="239.80999999999995" as="sourcePoint"/>
-                        <mxPoint x="680" y="239.80999999999995" as="targetPoint"/>
-                    </mxGeometry>
-                </mxCell>
-                <mxCell id="60" value="stb (valid)" style="edgeLabel;html=1;align=center;verticalAlign=middle;resizable=0;points=[];" vertex="1" connectable="0" parent="59">
-                    <mxGeometry x="-0.8404" y="-1" relative="1" as="geometry">
-                        <mxPoint x="197" y="-1" as="offset"/>
-                    </mxGeometry>
-                </mxCell>
-                <mxCell id="61" value="" style="shape=flexArrow;endArrow=classic;html=1;fillColor=#647687;strokeColor=#314354;" edge="1" parent="1">
-                    <mxGeometry width="50" height="50" relative="1" as="geometry">
-                        <mxPoint x="680" y="279.99999999999994" as="sourcePoint"/>
-                        <mxPoint x="520" y="279.99999999999994" as="targetPoint"/>
-                    </mxGeometry>
-                </mxCell>
-                <mxCell id="62" value="ack (ready/writeable)" style="edgeLabel;html=1;align=center;verticalAlign=middle;resizable=0;points=[];" vertex="1" connectable="0" parent="61">
-                    <mxGeometry x="-0.8404" y="-1" relative="1" as="geometry">
-                        <mxPoint x="73" y="1" as="offset"/>
-                    </mxGeometry>
-                </mxCell>
-                <mxCell id="49" value="Sink" style="rounded=0;whiteSpace=wrap;html=1;fillColor=#ffe6cc;strokeColor=#d79b00;" vertex="1" parent="1">
-                    <mxGeometry x="560" y="160" width="80" height="160" as="geometry"/>
-                </mxCell>
-            </root>
-        </mxGraphModel>
-    </diagram>
-</mxfile>

reset.py

@@ -1,17 +0,0 @@
-from time import sleep
-from pyftdi.ftdi import Ftdi
-
-POR = 1 << 7
-
-def main():
-    dev = Ftdi()
-    dev.open_bitbang_from_url("ftdi://ftdi:4232h/0")
-    dev.set_bitmode(POR, Ftdi.BitMode.BITBANG)
-    dev.write_data(bytes([0]))
-    sleep(0.1)
-    dev.write_data(bytes([POR]))
-    sleep(0.1)
-    dev.close()
-
-if __name__ == "__main__":
-    main()

sat_run.sh

@@ -1,63 +0,0 @@
-#!/usr/bin/env bash
-
-python reset.py
-
-set -e
-
-if [ -z "$OPENOCD_ZYNQ" ]; then
-    echo "OPENOCD_ZYNQ environment variable must be set"
-    exit 1
-fi
-if [ -z "$SZL" ]; then
-    echo "SZL environment variable must be set"
-    exit 1
-fi
-
-impure=0
-load_bitstream=1
-board_type="kasli_soc"
-fw_type="satman"
-
-while getopts "ilb:t:f:" opt; do
-    case "$opt" in
-    \?) exit 1
-        ;;
-    i)  impure=1
-        ;;
-    l)  load_bitstream=0
-        ;;
-    b)  board_host=$OPTARG
-        ;;
-    t)  board_type=$OPTARG
-        ;;
-    f)  fw_type=$OPTARG
-        ;;
-    esac
-done
-
-if [ -z "$board_host" ]; then
-    case $board_type in
-    kasli_soc) board_host="192.168.1.56";;
-    zc706) board_host="192.168.1.52";;
-    *) echo "Unknown board type"; exit 1;;
-    esac
-fi
-
-load_bitstream_cmd=""
-
-build_dir=`pwd`/build
-result_dir=`pwd`/result
-cd $OPENOCD_ZYNQ
-openocd -f $board_type.cfg -c "load_image $SZL/szl-$board_type.elf; resume 0; exit"
-sleep 5
-if [ $impure -eq 1 ]; then
-    if [ $load_bitstream -eq 1 ]; then
-        load_bitstream_cmd="-g $build_dir/gateware/top.bit"
-    fi
-    artiq_netboot $load_bitstream_cmd -f $build_dir/$fw_type.bin -b $board_host
-else
-    if [ $load_bitstream -eq 1 ]; then
-        load_bitstream_cmd="-g $result_dir/top.bit"
-    fi
-    artiq_netboot $load_bitstream_cmd -f $result_dir/$fw_type.bin -b $board_host
-fi

sim.py

@@ -1,55 +0,0 @@
-from migen import *
-from misoc.interconnect.csr import *
-
-from functools import reduce
-from itertools import combinations
-from operator import or_, and_
-
-class Voter(Module):
-    def __init__(self):
-        self.data_4x = Signal(32)
-        self.k_4x = Signal(4)
-        
-        # Section 9.2.2.1 (CXP-001-2021)
-        # decoder should immune to single bit errors when handling duplicated characters
-        self.char = Signal(8)
-        self.k = Signal()
-
-
-        # majority voting
-        char = [[self.data_4x[i*8:(i+1)*8], self.k_4x[i]] for i in range(4)]
-        voter = [Record([("data", 8), ("k", 1)]) for _ in range(4)]
-
-        # stage 1
-        for i, code in enumerate(combinations(char, 3)):
-            self.sync += [
-                voter[i].data.eq(reduce(and_, [c[0] for c in code])),
-                voter[i].k.eq(reduce(and_, [c[1] for c in code])),
-            ]
-
-        # stage 2
-        self.sync += [
-            self.char.eq(reduce(or_, [v.data for v in voter])),
-            self.k.eq(reduce(or_, [v.k for v in voter])),
-        ]
-
-        
-
-
-dut = Voter()
-def check_case(data_4x, k_4x, char, k):
-  yield dut.data_4x.eq(data_4x)
-  yield dut.k_4x.eq(k_4x)
-  yield
-  yield
-  yield
-  print(f"char = {yield dut.char:#X} k = {yield dut.k:#X}")
-  assert (yield dut.char) == char and (yield dut.k) == k
-
-def testbench():
-  yield from check_case(0xFFFFFFFF, 0b1111, 0xFF, 1)
-  yield from check_case(0xFFFFFF00, 0b1110, 0xFF, 1)
-  yield from check_case(0xFFFFF00f, 0b0001, 0xFF, 0)
-  yield from check_case(0xFFFFFFFF, 0b1111, 0xFF, 1)
-
-run_simulation(dut, testbench())

sim_4xgearbox.py

@@ -1,92 +0,0 @@
-from migen import *
-from misoc.interconnect.csr import *
-from misoc.interconnect import stream
-
-from src.gateware.cxp_router import *
-
-class DUT(Module):
-    def __init__(self):
-        self.submodules.gearbox = gearbox = Stream_Packet_Gearbox()
-        self.sink, self.source = gearbox.sink, gearbox.source
-
-        self.comb += self.source.ack.eq(1)
-
-
-dut = DUT()
-
-
-def packet_sim(packets=[]):
-    print("=================TEST========================")
-    sink = dut.sink
-    source = dut.source
-
-    for i, p in enumerate(packets):
-        yield sink.data.eq(p["data"])
-        yield sink.k.eq(p["k"])
-
-        if "stb_break" in p:
-            yield sink.stb.eq(0)
-        else:
-            yield sink.stb.eq(1)
-
-        if "eop" in p:
-            yield sink.eop.eq(1)
-        else:
-            yield sink.eop.eq(0)
-        yield
-
-    for _ in range(10):
-        yield sink.data.eq(0)
-        yield sink.k.eq(0)
-        yield sink.stb.eq(0)
-        yield sink.eop.eq(0)
-
-        yield source.ack.eq(1)
-        yield
-
-    assert True
-
-
-def testbench():
-    paks = [
-        {"data": C(0x7C7C7C7C, word_width), "k" : Replicate(1, 4)}, 
-        {"data": C(0x01010101, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x00000000, word_width), "k" : Replicate(0, 4)}, # stream id
-        {"data": C(0x00000001, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x6AEFACF6, word_width), "k" : Replicate(0, 4), "eop":0}, # crc
-
-        {"data": C(0, word_width), "k" : Replicate(0, 4), "stb_break":0}, # cyc break
-
-        {"data": C(0x02020202, word_width), "k" : Replicate(0, 4)},  
-        {"data": C(0x00000000, word_width), "k" : Replicate(0, 4)}, # Xsize[23:16]
-        {"data": C(0x09090909, word_width), "k" : Replicate(0, 4)}, # Xsize[15:8] 
-        {"data": C(0x90909090, word_width), "k" : Replicate(0, 4)}, # Xsize[7:0] 
-        {"data": C(0x00000000, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x00000000, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x00000000, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x00000000, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x8EE1DAA1, word_width), "k" : Replicate(0, 4), "eop":0}, # crc
-
-        {"data": C(0, word_width), "k" : Replicate(0, 4), "stb_break":0}, # cyc break
-
-        {"data": C(0x08080808, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x00000000, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x00000000, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x00000000, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x08080808, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x00000000, word_width), "k" : Replicate(0, 4)}, # DsizeL[23:16] 
-        {"data": C(0x02020202, word_width), "k" : Replicate(0, 4)}, # DsizeL[15:8] 
-        {"data": C(0x64646464, word_width), "k" : Replicate(0, 4)}, # DsizeL[7:0] 
-        {"data": C(0x01010101, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x01010101, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x00000000, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x00000000, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x00000000, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x51C243EA, word_width), "k" : Replicate(0, 4), "eop":0}, # crc
-
-    ]
-
-    
-    yield from packet_sim(paks)
-
-run_simulation(dut, testbench(), vcd_name="sim-cxp.vcd")

sim_arbiter.py

@@ -1,149 +0,0 @@
-from migen import *
-from misoc.interconnect.csr import *
-from misoc.interconnect import stream
-
-from sim_generator import CXPCRC32Inserter
-from src.gateware.cxp_frame_pipeline import *
-from src.gateware.cxp_pipeline import *
-
-CXP_CHANNELS = 2
-
-
-class Frame_Pipeline(Module):
-    def __init__(self, n_downconn):
-        # to construct correct crc and ack/stb signal
-        self.submodules.arbiter = arbiter = Stream_Arbiter(n_downconn)
-        self.submodules.broadcaster = broadcaster = Stream_Broadcaster(1)
-        self.submodules.buffer = buffer = Buffer(word_layout_dchar)
-        self.sinks = []
-
-        for i in range(n_downconn):
-            # generating the packet
-            dchar_decoder = Duplicated_Char_Decoder()
-            eop_marker = EOP_Marker()
-
-            pipeline = [dchar_decoder, eop_marker]
-            self.submodules += pipeline
-
-            for s, d in zip(pipeline, pipeline[1:]):
-                self.comb += s.source.connect(d.sink)
-            self.sinks.append(pipeline[0].sink)
-
-            self.comb += pipeline[-1].source.connect(arbiter.sinks[i])
-
-        # self.comb += arbiter.source.ack.eq(1)
-         
-        self.comb += [
-            arbiter.source.connect(broadcaster.sink),
-            broadcaster.sources[0].connect(buffer.sink),
-        ]
-        self.comb += buffer.source.ack.eq(1)
-
-
-
-dut = Frame_Pipeline(CXP_CHANNELS)
-
-
-def packet_sim(packets=[], active_ch=2):
-    assert active_ch <= CXP_CHANNELS
-
-    print("=================TEST========================")
-    # yield dut.arbiter.active_channels.eq((2**active_ch) - 1)
-    yield dut.arbiter.active_channels.eq((2**active_ch) - 1)
-    sinks = dut.sinks
-
-    for p in packets:
-        for i in range(CXP_CHANNELS):
-            if p["sink_id"] == i:
-                yield sinks[p["sink_id"]].data.eq(p["data"])
-                yield sinks[p["sink_id"]].k.eq(p["k"])
-                yield sinks[p["sink_id"]].stb.eq(1)
-                if "eop" in p:
-                    yield sinks[p["sink_id"]].eop.eq(1)
-                else:
-                    yield sinks[p["sink_id"]].eop.eq(0)
-            else:
-                yield sinks[i].data.eq(0)
-                yield sinks[i].k.eq(0)
-                yield sinks[i].stb.eq(0)
-                yield sinks[i].eop.eq(0)
-        yield
-
-    # extra clk cycles
-    for _ in range(100):
-        for i in range(CXP_CHANNELS):
-            yield sinks[i].data.eq(0)
-            yield sinks[i].k.eq(0)
-            yield sinks[i].stb.eq(0)
-            yield sinks[i].eop.eq(0)
-            yield
-    assert True
-
-
-def testbench(n_downconn, with_header=True, with_crc=True):
-    paks = []
-
-    stream_id = 0
-    pix_len = 10
-    for p in range(20):
-        n_conn = p % n_downconn
-        if with_header:
-            frame_pak_len = pix_len if with_crc else pix_len - 1
-            frame = [
-                {
-                    "sink_id": n_conn,
-                    "data": Replicate(C(stream_id, char_width), 4),
-                    "k": Replicate(0, 4),
-                },
-                {
-                    "sink_id": n_conn,
-                    "data": Replicate(C(0, char_width), 4),
-                    "k": Replicate(0, 4),
-                },
-                {
-                    "sink_id": n_conn,
-                    "data": Replicate(C(frame_pak_len, 2 * char_width)[8:], 4),
-                    "k": Replicate(0, 4),
-                },
-                {
-                    "sink_id": n_conn,
-                    "data": Replicate(C(frame_pak_len, 2 * char_width)[:8], 4),
-                    "k": Replicate(0, 4),
-                },
-            ]
-        else:
-            frame = []
-
-        for n_pix in range(pix_len):
-            if n_pix < pix_len - 1:
-                frame.append(
-                    {
-                        "sink_id": n_conn,
-                        # "data": C((n_conn + 1) << 28 | p << 24 | n_pix, word_width),
-                        "data": C( p << 24 | n_pix, word_width),
-                        "k": Replicate(0, 4),
-                    }
-                )
-            else:
-                frame.append(
-                    {
-                        "sink_id": n_conn,
-                        # "data": C((n_conn + 1) << 28 | p << 24 | n_pix, word_width),
-                        "data": C( p << 24 | n_pix, word_width),
-                        "k": Replicate(0, 4),
-                    }
-                )
-                frame.append(
-                    {
-                        "sink_id": n_conn,
-                        "data": Replicate(KCode["pak_end"], 4),
-                        "k": Replicate(1, 4),
-                    }
-                )
-
-        paks += frame
-
-    yield from packet_sim(paks)
-
-
-run_simulation(dut, testbench(CXP_CHANNELS,with_crc=False), vcd_name="sim-cxp.vcd")

sim_broadcaster.py

@@ -1,91 +0,0 @@
-from migen import *
-from misoc.interconnect.csr import *
-from misoc.interconnect import stream
-
-from sim_generator import CXPCRC32Inserter
-from src.gateware.cxp_frame_pipeline import *
-from src.gateware.cxp_pipeline import *
-
-class double_buffer_pipeline(Module):
-    def __init__(self):
-        fifo = stream.SyncFIFO(word_layout, 32)
-        dchar_decoder = Duplicated_Char_Decoder()
-        broadcaster = Stream_Broadcaster(1)
-        pipeline = [fifo, dchar_decoder, broadcaster]
-        self.submodules += pipeline
-
-        for s, d in zip(pipeline, pipeline[1:]):
-            self.comb += s.source.connect(d.sink)
-
-        self.sink = pipeline[0].sink
-
-        self.submodules.buffer = buffer = Buffer(word_layout_dchar)
-        self.comb += broadcaster.sources[0].connect(buffer.sink)
-        self.source = buffer.source
-       
-
-        # for sim, no backpressure
-        self.comb += self.source.ack.eq(1)
-
-
-
-dut = double_buffer_pipeline()
-
-
-def packet_sim(packets=[]):
-    print("=================TEST========================")
-    sink = dut.sink
-
-    cyc = len(packets)
-    pak = packets
-    for c in range(cyc):
-        yield sink.data.eq(pak[c]["data"])
-        yield sink.k.eq(pak[c]["k"])
-        yield sink.stb.eq(1)
-        if "eop" in pak[c]:
-            yield sink.eop.eq(1)
-        else:
-            yield sink.eop.eq(0)
-        yield
-
-    # extra clk cycles
-    for _ in range(cyc, cyc + 20):
-        yield sink.data.eq(0)
-        yield sink.k.eq(0)
-        yield sink.stb.eq(0)
-        yield sink.eop.eq(0)
-        yield
-    assert True
-
-
-def testbench():
-    paks = [
-        {"data": Replicate(C(0, char_width), 4), "k": Replicate(0, 4)},
-        {"data": Replicate(C(0, char_width), 4), "k": Replicate(0, 4)},
-        {"data": Replicate(C(4, 2 * char_width)[8:], 4), "k": Replicate(0, 4)},
-        {"data": Replicate(C(4, 2 * char_width)[:8], 4), "k": Replicate(0, 4)}, # CRC doesn't count
-        {"data": C(0x7C7C7C7C, word_width), "k": Replicate(1, 4)},
-        {"data": C(0x01010101, word_width), "k": Replicate(0, 4)},
-        {"data": C(0x00000000, word_width), "k": Replicate(0, 4)},
-        {"data": C(0x00000000, word_width), "k": Replicate(0, 4)},
-        {"data": C(0xF6ACEF6A, word_width), "k": Replicate(0, 4)},
-
-
-        {"data": Replicate(C(0, char_width), 4), "k": Replicate(0, 4)},
-        {"data": Replicate(C(1, char_width), 4), "k": Replicate(0, 4)},
-        {"data": Replicate(C(8, 2 * char_width)[8:], 4), "k": Replicate(0, 4)},
-        {"data": Replicate(C(8, 2 * char_width)[:8], 4), "k": Replicate(0, 4)}, # CRC doesn't count
-        {"data": C(0x19191919, word_width), "k": Replicate(0, 4)},
-        {"data": C(0x00000000, word_width), "k": Replicate(0, 4)},
-        {"data": C(0x09090909, word_width), "k": Replicate(0, 4)},
-        {"data": C(0x90909090, word_width), "k": Replicate(0, 4)},
-        {"data": C(0x00000000, word_width), "k": Replicate(0, 4)},
-        {"data": C(0x00000000, word_width), "k": Replicate(0, 4)},
-        {"data": C(0x00000000, word_width), "k": Replicate(0, 4)},
-        {"data": C(0x00000000, word_width), "k": Replicate(0, 4)},
-        {"data": C(0x985EFDB2, word_width), "k": Replicate(0, 4)},
-    ]
-    yield from packet_sim(paks)
-
-
-run_simulation(dut, testbench(), vcd_name="sim-cxp.vcd")

sim_buffer.py

@@ -1,93 +0,0 @@
-from migen import *
-from misoc.interconnect.csr import *
-from misoc.interconnect import stream
-
-# from src.gateware.cxp_frame_pipeline import *
-from src.gateware.cxp_pipeline import *
-
-from types import SimpleNamespace
-
-class DUT(Module):
-    def __init__(self):
-        # PHY
-        phy = SimpleNamespace()
-        phy.sink = stream.Endpoint(word_layout)
-        phy.source = stream.Endpoint(word_layout)
-
-        self.sync += [
-            phy.source.stb.eq(0),
-            If(~((phy.sink.data[:8] == 0xBC) & (phy.sink.k[0] == 1)),
-                phy.source.stb.eq(1),
-                phy.source.data.eq(phy.sink.data),
-                phy.source.k.eq(phy.sink.k),
-            ),
-        ]
-
-        # # #
-        
-        dchar_decoder = Duplicated_Char_Decoder()
-        eop_marker = EOP_Marker()
-
-        pipeline = [phy, dchar_decoder, eop_marker]
-        self.submodules += pipeline[1:] #phy is not a submodules
-
-        for s, d in zip(pipeline, pipeline[1:]):
-            self.comb += s.source.connect(d.sink)
-
-        self.sink, self.source = pipeline[0].sink, pipeline[-1].source
-
-
-
-dut = DUT()
-
-
-def packet_sim(packets=[]):
-    print("=================TEST========================")
-    sink = dut.sink
-    source = dut.source
-
-    for i, p in enumerate(packets):
-        yield sink.data.eq(p["data"])
-        yield sink.k.eq(p["k"])
-        yield sink.stb.eq(p["stb"])
-
-        yield source.ack.eq(1)
-        # if i % 2 == 0:
-        #     yield source.ack.eq(1)
-        # else:
-        #     yield source.ack.eq(0)
-        
-        yield
-
-    for _ in range(10):
-        yield sink.data.eq(0)
-        yield sink.k.eq(0)
-        yield sink.stb.eq(0)
-        yield sink.eop.eq(0)
-
-        yield source.ack.eq(1)
-        yield
-
-    assert True
-
-
-def testbench():
-    paks = []
-    for i in range(1, 10):
-        paks += [
-            {"data": C(i << 8 | 1, word_width), "k" : Replicate(0, 4), "stb":1},
-            {"data": C(i << 8 | 2, word_width), "k" : Replicate(0, 4), "stb":1},
-            {"data": C(i << 8 | 3, word_width), "k" : Replicate(0, 4), "stb":1},
-            {"data": C(i << 8 | 4, word_width), "k" : Replicate(0, 4), "stb":1},
-            {"data": C(0xB53C3CBC, word_width), "k" : C(0b0111, 4), "stb":0},
-            {
-                "data": Replicate(KCode["pak_end"], 4),
-                "k": Replicate(1, 4),
-                "stb": 1,
-            },
-        ]
-
-    
-    yield from packet_sim(paks)
-
-run_simulation(dut, testbench(), vcd_name="sim-cxp.vcd")

sim_comb.py

@@ -1,28 +0,0 @@
-from migen import *
-from misoc.interconnect import stream
-
-class Frame(Module):
-    def __init__(self):
-        self.a = Signal()
-        self.b = Signal()
-        self.comb += [
-            self.a.eq(self.b),
-            # self.b.eq(self.a),
-        ]
-
-dut = Frame()
-
-def check_case():
-    yield dut.a.eq(1)
-    yield 
-    yield dut.a.eq(0)
-    yield 
-    for i in range(10):
-        yield
-
-
-def testbench():
-    yield from check_case()
-
-
-run_simulation(dut, testbench(), vcd_name="sim-cxp.vcd")

sim_crc.py

@@ -1,58 +0,0 @@
-from migen import *
-from misoc.interconnect import stream
-from sim_pipeline import *
-from src.gateware.cxp_pipeline import *
-
-dut = StreamData_Generator()
-
-
-def check_case(packet=[], ack=0):
-    print("=================TEST========================")
-    for i, p in enumerate(packet):
-        yield dut.sink.data.eq(p["data"])
-        yield dut.sink.k.eq(p["k"])
-        yield dut.sink.stb.eq(1)
-        if "eop" in p:
-            yield dut.sink.eop.eq(1)
-
-        # CLK 
-        yield
-
-        sink = dut.sink
-        source = dut.source
-        crc = dut.crc_inserter.crc
-        print(
-            # f"\n CYCLE#{i} : sink char = {yield sink.data:#X} k = {yield sink.k:#X}"
-            f"\nCYCLE#{i} : source char = {yield source.data:#X} k = {yield source.k:#X}"
-            f" stb = {yield source.stb} eop = {yield source.eop} ack = {yield source.ack} "
-            f"\nCYCLE#{i} : crc error = {yield crc.error:#X} crc value = {yield crc.value:#X}"
-            f" crc data = {yield crc.data:#X} engine next = {yield crc.engine.next:#X}"
-            f"\nCYCLE#{i} : crc ce = {yield crc.ce:#X} "
-        )
-    # extra clk cycles
-    cyc = i + 1
-    for i in range(cyc, cyc + 11):
-        # yield has memory for some reason
-        yield dut.sink.stb.eq(0)
-        yield dut.source.ack.eq(1)
-        yield
-        print(
-            # f"\n CYCLE#{i} : sink char = {yield sink.data:#X} k = {yield sink.k:#X}"
-            f"\nCYCLE#{i} : source char = {yield source.data:#X} k = {yield source.k:#X}"
-            f" stb = {yield source.stb} eop = {yield source.eop} ack = {yield source.ack} "
-            f"\nCYCLE#{i} : crc error = {yield crc.error:#X} crc value = {yield crc.value:#X}"
-            f" crc data = {yield crc.data:#X} engine next = {yield crc.engine.next:#X}"
-            f"\nCYCLE#{i} : crc ce = {yield crc.ce:#X} "
-        )
-    assert True
-
-
-def testbench():
-    packet = [
-        {"data": 0x0000_0004, "k": Replicate(0, 4)},
-        {"data": 0x0000_0000, "k": Replicate(0, 4), "eop":1},
-    ]
-    yield from check_case(packet)
-
-
-run_simulation(dut, testbench())

sim_crc_checker.py

@@ -1,92 +0,0 @@
-from migen import *
-from misoc.interconnect.csr import *
-from misoc.interconnect import stream
-
-from src.gateware.cxp_frame_pipeline import *
-
-class DUT(Module):
-    def __init__(self):
-        self.submodules.crc_checker = crc_checker = CXPCRC32_Checker()
-        self.sink, self.source = crc_checker.sink, crc_checker.source
-
-        self.comb += self.source.ack.eq(1)
-
-
-dut = DUT()
-
-
-def packet_sim(packets=[]):
-    print("=================TEST========================")
-    sink = dut.sink
-    source = dut.source
-
-    for i, p in enumerate(packets):
-        yield sink.data.eq(p["data"])
-        yield sink.k.eq(p["k"])
-
-        if "stb_break" in p:
-            yield sink.stb.eq(0)
-        else:
-            yield sink.stb.eq(1)
-
-        if "eop" in p:
-            yield sink.eop.eq(1)
-        else:
-            yield sink.eop.eq(0)
-        yield
-
-    for _ in range(10):
-        yield sink.data.eq(0)
-        yield sink.k.eq(0)
-        yield sink.stb.eq(0)
-        yield sink.eop.eq(0)
-
-        yield source.ack.eq(1)
-        yield
-
-    assert True
-
-
-def testbench():
-    paks = [
-        {"data": C(0x7C7C7C7C, word_width), "k" : Replicate(1, 4)}, 
-        {"data": C(0x01010101, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x00000000, word_width), "k" : Replicate(0, 4)}, # stream id
-        {"data": C(0x00000001, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x6AEFACF6, word_width), "k" : Replicate(0, 4), "eop":0}, # crc
-
-        {"data": C(0, word_width), "k" : Replicate(0, 4), "stb_break":0}, # cyc break
-
-        {"data": C(0x02020202, word_width), "k" : Replicate(0, 4)},  
-        {"data": C(0x00000000, word_width), "k" : Replicate(0, 4)}, # Xsize[23:16]
-        {"data": C(0x09090909, word_width), "k" : Replicate(0, 4)}, # Xsize[15:8] 
-        {"data": C(0x90909090, word_width), "k" : Replicate(0, 4)}, # Xsize[7:0] 
-        {"data": C(0x00000000, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x00000000, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x00000000, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x00000000, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x8EE1DAA1, word_width), "k" : Replicate(0, 4), "eop":0}, # crc
-
-        {"data": C(0, word_width), "k" : Replicate(0, 4), "stb_break":0}, # cyc break
-
-        {"data": C(0x08080808, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x00000000, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x00000000, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x00000000, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x08080808, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x00000000, word_width), "k" : Replicate(0, 4)}, # DsizeL[23:16] 
-        {"data": C(0x02020202, word_width), "k" : Replicate(0, 4)}, # DsizeL[15:8] 
-        {"data": C(0x64646464, word_width), "k" : Replicate(0, 4)}, # DsizeL[7:0] 
-        {"data": C(0x01010101, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x01010101, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x00000000, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x00000000, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x00000000, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x51C243EA, word_width), "k" : Replicate(0, 4), "eop":0}, # crc
-
-    ]
-
-    
-    yield from packet_sim(paks)
-
-run_simulation(dut, testbench(), vcd_name="sim-cxp.vcd")

sim_double_buffer.py

@@ -1,80 +0,0 @@
-from migen import *
-from misoc.interconnect.csr import *
-from misoc.interconnect import stream
-
-from sim_generator import CXPCRC32Inserter
-from src.gateware.cxp_frame_pipeline import *
-from src.gateware.cxp_pipeline import *
-
-class double_buffer_pipeline(Module):
-    def __init__(self):
-        fifo = stream.SyncFIFO(word_layout_dchar, 32)
-        double_buffer = CXPCRC32_Checker(0x100)
-        dchar_dropper = DChar_Dropper()
-        pipeline = [double_buffer, dchar_dropper]
-        self.submodules += pipeline
-
-        for s, d in zip(pipeline, pipeline[1:]):
-            self.comb += s.source.connect(d.sink)
-
-        self.sink = pipeline[0].sink
-        self.source = pipeline[-1].source
-
-        # for sim, no backpressure
-        self.comb += self.source.ack.eq(1)
-
-
-
-dut = double_buffer_pipeline()
-
-
-def packet_sim(packets=[]):
-    print("=================TEST========================")
-    sink = dut.sink
-
-    cyc = len(packets)
-    pak = packets
-    for c in range(cyc):
-        yield sink.data.eq(pak[c]["data"])
-        yield sink.k.eq(pak[c]["k"])
-        yield sink.stb.eq(1)
-        if "eop" in pak[c]:
-            yield sink.eop.eq(1)
-        else:
-            yield sink.eop.eq(0)
-        yield
-
-    # extra clk cycles
-    for _ in range(cyc, cyc + 20):
-        yield sink.data.eq(0)
-        yield sink.k.eq(0)
-        yield sink.stb.eq(0)
-        yield sink.eop.eq(0)
-        yield
-    assert True
-
-
-def testbench():
-    paks = [
-        {"data": C(0x7C7C7C7C, word_width), "k": Replicate(1, 4)},
-        {"data": C(0x01010101, word_width), "k": Replicate(0, 4)},
-        {"data": C(0x00000000, word_width), "k": Replicate(0, 4)},
-        {"data": C(0x00000000, word_width), "k": Replicate(0, 4)},
-        # {"data": C(0xF6ACEF6B, word_dw), "k": Replicate(0, 4), "eop":1},
-        {"data": C(0x6AEFACF6, word_width), "k": Replicate(0, 4), "eop":1},
-
-
-        {"data": C(0x19191919, word_width), "k": Replicate(0, 4)},
-        {"data": C(0x00000000, word_width), "k": Replicate(0, 4)},
-        {"data": C(0x09090909, word_width), "k": Replicate(0, 4)},
-        {"data": C(0x90909090, word_width), "k": Replicate(0, 4)},
-        {"data": C(0x00000000, word_width), "k": Replicate(0, 4)},
-        {"data": C(0x00000000, word_width), "k": Replicate(0, 4)},
-        {"data": C(0x00000000, word_width), "k": Replicate(0, 4)},
-        {"data": C(0x00000000, word_width), "k": Replicate(0, 4)},
-        {"data": C(0xB2FD5E98, word_width), "k": Replicate(0, 4), "eop":1},
-    ]
-    yield from packet_sim(paks)
-
-
-run_simulation(dut, testbench(), vcd_name="sim-cxp.vcd")

sim_eop.py

@@ -1,72 +0,0 @@
-from migen import *
-from misoc.interconnect.csr import *
-from misoc.interconnect import stream
-
-from sim_generator import CXPCRC32Inserter
-from src.gateware.cxp_frame_pipeline import *
-from src.gateware.cxp_pipeline import *
-
-class EOP_Pipeline(Module):
-    def __init__(self):
-        dchar_decoder = Duplicated_Char_Decoder()
-        eop_inserter = EOP_Marker()
-        buffer = stream.SyncFIFO(word_layout_dchar, 32)
-        pipeline = [dchar_decoder, eop_inserter, buffer]
-        self.submodules += pipeline
-
-        for s, d in zip(pipeline, pipeline[1:]):
-            self.comb += s.source.connect(d.sink)
-
-        self.sink = pipeline[0].sink
-        self.source = pipeline[-1].source
-
-        # for sim, no backpressure
-        self.comb += self.source.ack.eq(1)
-
-
-
-dut = EOP_Pipeline()
-
-
-def packet_sim(packets=[]):
-    print("=================TEST========================")
-    sink = dut.sink
-
-    cyc = len(packets)
-    pak = packets
-    for c in range(cyc):
-        yield sink.data.eq(pak[c]["data"])
-        yield sink.k.eq(pak[c]["k"])
-        yield sink.stb.eq(1)
-        yield
-
-    # extra clk cycles
-    for _ in range(cyc, cyc + 10):
-        yield sink.data.eq(0)
-        yield sink.k.eq(0)
-        yield sink.stb.eq(0)
-        yield sink.eop.eq(0)
-        yield
-    assert True
-
-
-def testbench():
-    paks = [
-        {"data": Replicate(KCode["pak_start"], 4), "k": Replicate(1, 4)},
-        {"data": C(0x1111, word_width), "k": Replicate(1, 4)},
-        {"data": C(0x2222, word_width), "k": Replicate(0, 4)},
-        {"data": C(0x3333, word_width), "k": Replicate(0, 4)},
-        {"data": C(0x4444, word_width), "k": Replicate(0, 4)},
-        {"data": Replicate(KCode["pak_end"], 4), "k": Replicate(1, 4)},
-
-        {"data": Replicate(KCode["pak_start"], 4), "k": Replicate(1, 4)},
-        {"data": C(0xAAAA, word_width), "k": Replicate(1, 4)},
-        {"data": C(0xBBBB, word_width), "k": Replicate(0, 4)},
-        {"data": C(0xCCCC, word_width), "k": Replicate(0, 4)},
-        {"data": C(0xDDDD, word_width), "k": Replicate(0, 4)},
-        {"data": Replicate(KCode["pak_end"], 4), "k": Replicate(1, 4)},
-    ]
-    yield from packet_sim(paks)
-
-
-run_simulation(dut, testbench(), vcd_name="sim-cxp.vcd")

sim_frame.py

@@ -1,134 +0,0 @@
-from migen import *
-from misoc.interconnect import stream
-
-from sim_generator import CXPCRC32Inserter
-from sim_frame_gen import get_frame_packet
-
-from src.gateware.cxp_pipeline import *
-from src.gateware.cxp_frame_pipeline import *
-
-import numpy as np
-from PIL import Image
-
-
-class Frame(Module):
-    def __init__(self):
-        # to construct correct crc and ack/stb signal
-        self.submodules.buffer = buffer = stream.SyncFIFO(word_layout, 32)
-        self.submodules.crc_inserter = crc_inserter = CXPCRC32Inserter()
-        self.submodules.dchar_decoder = dchar_decoder = Duplicated_Char_Decoder()
-
-        # NOTE: eop is needed for crc to work correctly and RX_Bootstrap need to be followed by a EOP marker anyway
-        self.submodules.eop_marker = eop_marker = EOP_Marker()
-
-        self.submodules.stream_pipe = stream_pipe = Pixel_Pipeline()
-
-        pipeline = [buffer, crc_inserter, dchar_decoder, eop_marker, stream_pipe]
-        for s, d in zip(pipeline, pipeline[1:]):
-            self.comb += s.source.connect(d.sink)
-        self.sink = pipeline[0].sink
-        self.source = pipeline[-1].source
-
-        # no backpressure for sim
-        self.sync += self.source.ack.eq(1)
-
-
-dut = Frame()
-
-
-def check_case(packet=[]):
-    print("=================TEST========================")
-
-    sink = dut.sink
-    stream_pipe = dut.stream_pipe
-
-    for i, p in enumerate(packet):
-        yield sink.data.eq(p["data"])
-        yield sink.k.eq(p["k"])
-        yield sink.stb.eq(1)
-        if "eop" in p:
-            yield sink.eop.eq(1)
-        else:
-            yield sink.eop.eq(0)
-
-        # check cycle result
-        yield
-        # source = dut.dchar_decoder.source
-        # source = dut.stream_pipe.frame_extractor.sink
-        source = dut.sink
-        # print(
-        #     f"\nCYCLE#{i} : source char = {yield source.data:#X} k = {yield source.k:#X} stb = {yield source.stb} ack = {yield source.ack} eop = {yield source.eop}"
-        # )
-
-    # extra clk cycles
-    cyc = i + 1
-    img = []
-    line = -1
-    total_pixel = 1000
-    for i in range(cyc, cyc + total_pixel):
-        yield sink.data.eq(0)
-        yield sink.k.eq(0)
-        yield sink.stb.eq(0)
-        yield sink.eop.eq(0)
-        yield
-        # print(
-        #     f"\nCYCLE#{i} : source char = {yield source.data:#X} k = {yield source.k:#X} stb = {yield source.stb} ack = {yield source.ack} eop = {yield source.eop}"
-        # )
-
-        frame_extractoer = dut.stream_pipe.frame_extractor
-        new_line = yield frame_extractoer.new_line
-        if new_line:
-            img.append([])
-            line += 1
-            
-        stb = yield frame_extractoer.source.stb 
-        data = yield frame_extractoer.source.data
-        if stb:
-            # CXP use MSB
-            img[line].append(np.uint16(data & 0xFFFF))
-            img[line].append(np.uint16(data >> 16))
-
-        # metadata = dut.stream_pipe.frame_extractor.metadata
-        # img_header_layout = [
-        #     "stream_id",
-        #     "source_tag",
-        #     "x_size",
-        #     "x_offset",
-        #     "y_size",
-        #     "y_offset",
-        #     "l_size",  # number of data words per image line
-        #     "pixel_format",
-        #     "tap_geo",
-        #     "flag",
-        # ]
-        # for name in img_header_layout:
-        #     print(f"{name} = {yield getattr(metadata, name):#04X} ", end="")
-        # print()
-    Image.fromarray(np.array(img, dtype=np.uint8)).show()
-    assert True
-
-
-def testbench():
-    stream_id = 0x69
-    packet_tag = 0
-    frame_packet = get_frame_packet(stream_id)
-    packet = [
-        {"data": Replicate(C(stream_id, char_width), 4), "k": Replicate(0, 4)},
-        {"data": Replicate(C(packet_tag, char_width), 4), "k": Replicate(0, 4)},
-        {
-            "data": Replicate(C(len(frame_packet), 2*char_width)[8:], 4),
-            "k": Replicate(0, 4),
-        },
-        {
-            "data": Replicate(C(len(frame_packet), 2*char_width)[:8], 4),
-            "k": Replicate(0, 4),
-        },
-    ]
-    packet += frame_packet
-    # NOTE: for crc inserter!!!!
-    packet[-1]["eop"] = 0
-
-    yield from check_case(packet)
-
-
-run_simulation(dut, testbench(), vcd_name="sim-cxp.vcd")

sim_frame_gen.py

@@ -1,148 +0,0 @@
-from migen import *
-from misoc.interconnect import stream
-
-from src.gateware.cxp_pipeline import *
-from src.gateware.cxp_frame_pipeline import *
-
-from PIL import Image
-import numpy as np
-
-
-def get_image_header(
-    stream_id, source_tag, xsize, xoffset, ysize, yoffset, dsize, pixelF, tag_geo, flag
-):
-    stream_id = C(stream_id, char_width)
-    source_tag = C(source_tag, 2 * char_width)
-    xsize = C(xsize, 3 * char_width)
-    xoffset = C(xoffset, 3 * char_width)
-    ysize = C(ysize, 3 * char_width)
-    yoffset = C(yoffset, 3 * char_width)
-    dsize = C(dsize, 3 * char_width)
-    pixelF = C(pixelF, 2 * char_width)
-    tag_geo = C(tag_geo, 2 * char_width)
-    flag = C(flag, char_width)
-
-    assert len(stream_id) == len(flag) == char_width
-    assert len(source_tag) == len(pixelF) == len(tag_geo) == 2 * char_width
-    assert len(xsize) == len(xoffset) == len(ysize) == len(yoffset) == 3 * char_width
-    return [
-        {"data": Replicate(KCode["stream_marker"], 4), "k": Replicate(1, 4)},
-        {"data": Replicate(C(0x01, char_width), 4), "k": Replicate(0, 4)},
-        {"data": Replicate(stream_id, 4), "k": Replicate(0, 4)},
-        {"data": Replicate(source_tag[8:], 4), "k": Replicate(0, 4)},
-        {"data": Replicate(source_tag[:8], 4), "k": Replicate(0, 4)},
-        {"data": Replicate(xsize[16:], 4), "k": Replicate(0, 4)},
-        {"data": Replicate(xsize[8:16], 4), "k": Replicate(0, 4)},
-        {"data": Replicate(xsize[:8], 4), "k": Replicate(0, 4)},
-        {"data": Replicate(xoffset[16:], 4), "k": Replicate(0, 4)},
-        {"data": Replicate(xoffset[8:16], 4), "k": Replicate(0, 4)},
-        {"data": Replicate(xoffset[:8], 4), "k": Replicate(0, 4)},
-        {"data": Replicate(ysize[16:], 4), "k": Replicate(0, 4)},
-        {"data": Replicate(ysize[8:16], 4), "k": Replicate(0, 4)},
-        {"data": Replicate(ysize[:8], 4), "k": Replicate(0, 4)},
-        {"data": Replicate(yoffset[16:], 4), "k": Replicate(0, 4)},
-        {"data": Replicate(yoffset[8:16], 4), "k": Replicate(0, 4)},
-        {"data": Replicate(yoffset[:8], 4), "k": Replicate(0, 4)},
-        {"data": Replicate(dsize[16:], 4), "k": Replicate(0, 4)},
-        {"data": Replicate(dsize[8:16], 4), "k": Replicate(0, 4)},
-        {"data": Replicate(dsize[:8], 4), "k": Replicate(0, 4)},
-        {"data": Replicate(pixelF[8:], 4), "k": Replicate(0, 4)},
-        {"data": Replicate(pixelF[:8], 4), "k": Replicate(0, 4)},
-        {"data": Replicate(tag_geo[8:], 4), "k": Replicate(0, 4)},
-        {"data": Replicate(tag_geo[:8], 4), "k": Replicate(0, 4)},
-        {"data": Replicate(flag, 4), "k": Replicate(0, 4)},
-    ]
-
-
-def get_line_marker():
-    return [
-        {"data": Replicate(KCode["stream_marker"], 4), "k": Replicate(1, 4)},
-        {"data": Replicate(C(0x02, char_width), 4), "k": Replicate(0, 4)},
-    ]
-
-
-def get_frame_packet(stream_id, pixel_format="mono16"):
-    assert pixel_format in ["mono16"]
-
-    arr = [
-        [204, 200, 203, 205, 190, 187, 189, 205, 214, 197, 188, 185, 181, 178, 193, 209, 211, 207, 211, 192, 168, 168, 171, 199, 210, 212, 203, 196],
-        [218, 205, 199, 190, 192, 197, 196, 195, 184, 178, 182, 173, 166, 132, 122, 114, 154, 184, 187, 188, 171, 168, 170, 180, 192, 196, 202, 198],
-        [223, 222, 222, 224, 216, 199, 199, 207, 205, 189, 183, 182, 144, 66,  61,  66, 80, 148, 181, 175, 169, 170, 174, 177, 196, 206, 223, 218],
-        [221, 226, 225, 222, 211, 200, 202, 208, 215, 201, 187, 180, 133, 116, 113, 118, 96, 111, 206, 193, 170, 169, 186, 211, 218, 224, 231, 223],
-        [219, 216, 206, 197, 210, 201, 206, 203, 191, 190, 185, 145, 134, 140, 159, 170, 150, 116, 180, 173, 179, 170, 172, 185, 201, 218, 227, 227],
-        [203, 198, 194, 208, 227, 201, 201, 201, 215, 221, 209, 170, 136, 113, 141, 139, 141, 145, 188, 170, 180, 169, 184, 173, 174, 192, 215, 230],
-        [206, 224, 213, 213, 233, 207, 204, 226, 233, 227, 214, 166, 145, 123, 145, 155, 147, 186, 213, 187, 171, 169, 193, 193, 171, 178, 186, 207],
-        [212, 228, 216, 205, 214, 205, 204, 230, 235, 225, 219, 187, 143, 122, 146, 163, 158, 195, 209, 203, 174, 168, 190, 185, 187, 202, 180, 174],
-        [197, 206, 201, 223, 213, 201, 203, 231, 234, 225, 218, 206, 147, 125, 149, 155, 190, 208, 206, 203, 175, 168, 171, 179, 184, 206, 189, 176],
-        [213, 202, 209, 235, 223, 200, 202, 202, 227, 227, 202, 176, 138, 122, 144, 153, 190, 209, 207, 191, 172, 167, 179, 204, 190, 191, 180, 193],
-        [225, 225, 207, 231, 219, 197, 215, 200, 194, 199, 181, 172, 131, 129, 147, 159, 113, 175, 196, 179, 184, 169, 181, 210, 202, 204, 200, 177],
-        [208, 222, 204, 223, 210, 191, 195, 198, 203, 167, 171, 168, 135, 129, 149, 175,  66,  57,  90, 121, 147, 165, 181, 205, 195, 217, 209, 173],
-        [188, 216, 201, 206, 199, 180, 185, 180, 129,  75, 139, 166, 124, 146, 189, 135,  51,  41,  38,  40,  45,  63, 131, 201, 189, 215, 193, 170],
-        [188, 194, 195, 192, 182, 180, 134,  68,  45,  41,  96, 130, 116, 156, 163,  64,  46,  41,  43,  41,  42,  42,  74, 181, 177, 198, 175, 193],
-        [179, 179, 209, 224, 198, 182,  99,  42,  44,  41,  44, 100, 116, 125, 100,  46,  45,  42,  42,  37,  44,  43,  49, 150, 183, 170, 172, 198],
-        [175, 177, 208, 223, 197, 180,  94,  40,  42,  40,  41,  99, 134, 117,  80,  43,  46,  43,  37,  37,  44,  42,  35, 129, 195, 170, 170, 180],
-        [179, 181, 187, 217, 193, 175,  91,  38,  41,  41,  42, 106, 151, 107,  62,  43,  45,  41,  33,  38,  42,  34,  33,  77, 188, 175, 173, 208],
-        [190, 191, 180, 213, 194, 175,  78,  38,  40,  40,  40,  98, 134, 97,  51,  44,  59,  50,  37,  40,  36,  26,  36,  44, 100, 178, 192, 206],
-        [199, 191, 184, 204, 196, 176,  78,  33,  38,  38,  39,  80, 102, 83,  43,  44, 112, 130, 122,  63,  33,  24,  29,  34,  33,  74, 162, 195],
-        [191, 170, 196, 193, 186, 177,  88,  27,  34,  37,  36,  74, 101, 70,  36,  37,  81, 127, 137, 113,  40,  28,  30,  32,  36,  29, 69, 173],
-        [164, 189, 190, 180, 176, 172,  83,  26,  28,  33,  32,  68,  97, 62,  32,  30,  44,  97, 123, 136,  58,  42,  44,  43,  43,  40, 58, 162],
-        [177, 202, 205, 181, 174, 163,  78,  38,  35,  47,  54,  67,  92, 51,  28,  29,  26,  21,  39,  85,  47,  46,  52,  47,  46,  45, 48, 141],
-        [181, 193, 199, 192, 171, 163,  91,  67, 121, 123,  91,  63,  89, 45,  25,  25,  23,  20,  15,  13,  20,  48,  54,  35,  34,  34, 68, 146],
-        [175, 192, 195, 179, 165, 163, 100,  64,  99,  94,  82,  58,  83, 37,  23,  22,  22,  27,  21,  15,  14,  44,  98,  83,  94, 118, 164, 157],
-        [153, 184, 171, 163, 161, 157, 140,  70,  58,  89,  61,  53,  76, 30,  20,  20,  20,  31,  24,  19,  16,  47, 159, 163, 160, 171, 160, 142],
-        [142, 150, 161, 168, 154, 154, 164, 138,  76,  55,  26,  37,  62, 24,  19,  19,  20,  21,  23,  27,  31,  46, 142, 156, 151, 153, 147, 145],
-        [153, 147, 174, 171, 151, 150, 169, 158, 142,  92,  28,  60,  59, 20,  20,  18,  20,  26,  27,  29,  33,  38, 125, 153, 150, 147, 147, 148],
-        [138, 141, 166, 164, 146, 144, 164, 149, 132,  72,  34,  88,  72, 24,  19,  18,  18,  23,  25,  28,  31,  30,  98, 150, 146, 144, 146, 144]
-    ]
-    source_tag = 0
-    xsize, ysize = len(arr[0]), len(arr)
-
-    xoffset, yoffset = 0, 0
-    if pixel_format == "mono16":
-        dsize = xsize // 2
-        pixelF = 0x0105
-    tag_geo = 0
-    flag = 0
-
-    packet = []
-    # Image header
-    packet += get_image_header(
-        stream_id,
-        source_tag,
-        xsize,
-        xoffset,
-        ysize,
-        yoffset,
-        dsize,
-        pixelF,
-        tag_geo,
-        flag,
-    )
-
-    for line in arr:
-        packet += get_line_marker()
-        if pixel_format == "mono16":
-            for i in range(len(line)):
-                if (i % 2) == 0:
-                    if i == len(line) - 1:
-                        # print(C(line[i]))
-                        packet += [
-                            {
-                                "data": C(line[i], 4 * char_width),
-                                "k": Replicate(0, 4),
-                            },
-                        ]
-                    else:
-                        # print(C(line[i], 2 * char_width), C(line[i + 1]))
-                        # CXP use MSB
-                        packet += [
-                            {
-                                "data": Cat(
-                                    C(line[i], 2 * char_width),
-                                    C(line[i + 1], 2 * char_width),
-                                ),
-                                "k": Replicate(0, 4),
-                            },
-                        ]
-
-    return packet

sim_generator.py

@@ -1,122 +0,0 @@
-from migen import *
-from misoc.interconnect.csr import *
-from misoc.interconnect import stream
-
-from src.gateware.cxp_frame_pipeline import CXPCRC32
-from src.gateware.cxp_pipeline import *
-
-class CXPCRC32Inserter(Module):
-    def __init__(self, insert_eop=True):
-        self.sink = stream.Endpoint(word_layout)
-        self.source = stream.Endpoint(word_layout)
-
-        # # #
-
-        self.submodules.crc = crc = CXPCRC32(word_width)
-        self.submodules.fsm = fsm = FSM(reset_state="IDLE")
-
-        # WARNING: this will eat data if the source don't care about ack
-        # NOTE: need one cycle to turn itself on
-        fsm.act(
-            "IDLE",
-            crc.reset.eq(1),
-            self.sink.ack.eq(1),
-            If(
-                self.sink.stb,
-                self.sink.ack.eq(0),
-                NextState("COPY"),
-            ),
-        )
-        fsm.act(
-            "COPY",
-            crc.ce.eq(self.sink.stb & self.source.ack),
-            crc.data.eq(self.sink.data),
-            self.sink.connect(self.source),
-            self.source.eop.eq(0),
-            If(
-                self.sink.stb & self.sink.eop & self.source.ack,
-                NextState("INSERT"),
-            ),
-        )
-        fsm.act(
-            "INSERT",
-            self.source.stb.eq(1),
-            self.source.eop.eq(1) if insert_eop else self.source.eop.eq(0),
-            self.source.data.eq(crc.value),
-            If(self.source.ack, NextState("IDLE")),
-        )
-
-
-class StreamPacket_Wrapper(Module):
-    def __init__(self):
-        self.sink = stream.Endpoint(word_layout)
-        self.source = stream.Endpoint(word_layout)
-
-        # # #
-
-        self.submodules.fsm = fsm = FSM(reset_state="IDLE")
-
-        fsm.act(
-            "IDLE",
-            self.sink.ack.eq(1),
-            If(
-                self.sink.stb,
-                self.sink.ack.eq(0),
-                NextState("INSERT_HEADER_0"),
-            ),
-        )
-
-        fsm.act(
-            "INSERT_HEADER_0",
-            self.sink.ack.eq(0),
-            self.source.stb.eq(1),
-            self.source.data.eq(Replicate(KCode["pak_start"], 4)),
-            self.source.k.eq(Replicate(1, 4)),
-            If(self.source.ack, NextState("INSERT_HEADER_1")),
-        )
-
-        fsm.act(
-            "INSERT_HEADER_1",
-            self.sink.ack.eq(0),
-            self.source.stb.eq(1),
-            self.source.data.eq(Replicate(C(0x01, char_width), 4)),
-            self.source.k.eq(Replicate(0, 4)),
-            If(self.source.ack, NextState("COPY")),
-        )
-
-        fsm.act(
-            "COPY",
-            self.sink.connect(self.source),
-            self.source.eop.eq(0),
-            If(
-                self.sink.stb & self.sink.eop & self.source.ack,
-                NextState("INSERT_FOOTER"),
-            ),
-        )
-
-        fsm.act(
-            "INSERT_FOOTER",
-            self.sink.ack.eq(0),
-            self.source.stb.eq(1),
-            self.source.data.eq(Replicate(KCode["pak_end"], 4)),
-            self.source.k.eq(Replicate(1, 4)),
-            # Simulate RX don't have eop tagged
-            # self.source.eop.eq(1),
-            If(self.source.ack, NextState("IDLE")),
-        )
-
-
-# With KCode & 0x01*4
-class StreamData_Generator(Module):
-    def __init__(self):
-        # should be big enough for all test
-        self.submodules.buffer = buffer = stream.SyncFIFO(word_layout, 32)
-        self.submodules.crc_inserter = crc_inserter = CXPCRC32Inserter()
-        self.submodules.wrapper = wrapper = StreamPacket_Wrapper()
-
-        # # #
-        pipeline = [buffer, crc_inserter, wrapper]
-        for s, d in zip(pipeline, pipeline[1:]):
-            self.comb += s.source.connect(d.sink)
-        self.sink = pipeline[0].sink
-        self.source = pipeline[-1].source

sim_idle.py

@@ -1,149 +0,0 @@
-from migen import *
-from misoc.interconnect import stream
-
-from src.gateware.cxp_pipeline import Packet_Wrapper
-
-char_width = 8
-word_dw = 32
-word_layout = [("data", word_dw), ("k", word_dw//8)]
-
-
-def K(x, y):
-    return ((y << 5) | x)
-
-KCode = {
-    "pak_start" : C(K(27, 7), char_width),
-    "io_ack" : C(K(28, 6), char_width), 
-    "trig_indic_28_2" : C(K(28, 2), char_width),
-    "stream_marker" : C(K(28, 3), char_width),
-    "trig_indic_28_4" : C(K(28, 4), char_width),
-    "pak_end" : C(K(29, 7), char_width),
-    "idle_comma" : C(K(28, 5), char_width),
-    "idle_alignment" : C(K(28, 1), char_width),
-}
-
-class TX_Bootstrap(Module):
-    def __init__(self):
-        self.tx_testseq = Signal()
-
-        # # #
-
-        self.submodules.fsm = fsm = FSM(reset_state="IDLE")
-        self.source = stream.Endpoint(word_layout)
-
-        self.cnt = Signal(max=0xFFF)
-        fsm.act("IDLE",
-            If(self.tx_testseq, 
-                NextValue(self.cnt, self.cnt.reset),
-                NextState("WRITE_TEST_PACKET_TYPE"),
-            )
-        )
-
-        fsm.act("WRITE_TEST_PACKET_TYPE",
-            self.source.stb.eq(1),
-            self.source.data.eq(Replicate(C(0x04, char_width), 4)),
-            self.source.k.eq(Replicate(0, 4)),
-            If(self.source.ack,NextState("WRITE_TEST_COUNTER"))
-        )
-
-        # testword = Signal(word_dw)
-        # self.comb += [
-        #     testword[:8].eq(self.cnt[:8]),
-        #     testword[8:16].eq(self.cnt[:8]+1),
-        #     testword[16:24].eq(self.cnt[:8]+2),
-        #     testword[24:].eq(self.cnt[:8]+3),
-        # ]
-
-        fsm.act("WRITE_TEST_COUNTER",
-            self.source.stb.eq(1),
-            self.source.data[:8].eq(self.cnt[:8]),
-            self.source.data[8:16].eq(self.cnt[:8]+1),
-            self.source.data[16:24].eq(self.cnt[:8]+2),
-            self.source.data[24:].eq(self.cnt[:8]+3),
-            self.source.k.eq(Cat(0, 0, 0, 0)),
-            If(self.source.ack,
-                If(self.cnt == 0x0FF-3,
-                    self.source.eop.eq(1),
-                    NextState("IDLE")
-                ).Else(
-                    NextValue(self.cnt, self.cnt + 4),
-                )
-               
-            )
-        )
-
-class Idle_Word_Inserter(Module):
-    def __init__(self):
-        # Section 9.2.5 (CXP-001-2021)
-        # Send K28.5, K28.1, K28.1, D21.5  as idle word
-        self.submodules.fsm = fsm = FSM(reset_state="WRITE_IDLE")
-        
-        self.sink = stream.Endpoint(word_layout)
-        self.source = stream.Endpoint(word_layout)
-
-        cnt = Signal(max=0x10, reset=0xF)
-        
-        fsm.act("WRITE_IDLE",
-            self.source.stb.eq(1),
-            self.source.data.eq(Cat(KCode["idle_comma"], KCode["idle_alignment"], KCode["idle_alignment"], C(0xB5, char_width))),
-            self.source.k.eq(Cat(1, 1, 1, 0)),
-
-            self.sink.ack.eq(1),
-            If(self.sink.stb,
-                self.sink.ack.eq(0),
-                If(self.source.ack,
-                    NextValue(cnt, cnt.reset),
-                    NextState("COPY"),
-                )
-            ),
-        )
-
-        fsm.act("COPY",
-            self.sink.connect(self.source),
-            # increment when upstream has data and got ack
-            If(self.sink.stb & self.source.ack, NextValue(cnt, cnt - 1)),
-            If((((~self.sink.stb) | (self.sink.eop) | (cnt == 0) ) & self.source.ack), NextState("WRITE_IDLE"))
-        )
-
-class Pipeline(Module):
-    def __init__(self):
-        self.submodules.bootstrap = boostrap = TX_Bootstrap()
-        self.submodules.wrapper = wrapper = Packet_Wrapper()
-        # self.submodules.buffer = buffer = stream.SyncFIFO(word_layout, 32)
-        self.submodules.idle_inserter = idle_inserter = Idle_Word_Inserter()
-
-        # # #
-
-        pipeline = [boostrap, wrapper, idle_inserter]
-        for s, d in zip(pipeline, pipeline[1:]):
-            self.comb += s.source.connect(d.sink)
-        # self.sink = pipeline[0].sink
-        self.source = pipeline[-1].source
-
-        # no backpressure
-        # self.comb += self.source.ack.eq(1)
-
-dut = Pipeline()
-
-def check_case():
-    source = dut.source
-    # sink = dut.sink
-    # for i in range(1, 30):
-    #     yield sink.data.eq(i)
-    #     yield sink.stb.eq(1)
-    #     yield 
-    yield dut.bootstrap.tx_testseq.eq(1)
-    yield
-    yield dut.bootstrap.tx_testseq.eq(0)
-    for i in range(10):
-        yield
-    for _ in range(100):
-        yield source.ack.eq(1)
-        yield
-
-
-def testbench():
-    yield from check_case()
-
-
-run_simulation(dut, testbench(), vcd_name="sim-cxp.vcd")

sim_roi.py

@@ -1,323 +0,0 @@
-from migen import *
-from misoc.interconnect.csr import *
-from misoc.interconnect import stream
-
-from src.gateware.cxp_frame_pipeline import *
-from src.gateware.cxp_pipeline import *
-
-from math import ceil
-
-class ROI(Module):
-    def __init__(self):
-        fifo = stream.SyncFIFO(word_layout, 32) # to avoid data getting eaten and act as delay between eop
-        dchar_decoder = Duplicated_Char_Decoder()
-        # self.crc = CXPCRC32_Checker()
-        self.pipeline = Pixel_Pipeline(24, 32)
-
-        pipeline = [fifo, dchar_decoder, self.pipeline]
-        self.submodules += pipeline
-
-        for s, d in zip(pipeline, pipeline[1:]):
-            self.comb += s.source.connect(d.sink)
-
-        self.sink = pipeline[0].sink
-        # self.source = pipeline[-1].source
-         
-        # DEBUG: test roi
-        cfg = self.pipeline.roi.cfg
-        self.comb += [
-            cfg.x0.eq(1),
-            cfg.x1.eq(2),
-            cfg.y0.eq(1),
-            cfg.y1.eq(2),
-        ]
-
-
-
-dut = ROI()
-
-
-def packet_sim(packets=[]):
-    print("=================TEST========================")
-    sink = dut.sink
-
-    cyc = len(packets)
-    pak = packets
-    for c in range(cyc):
-        yield sink.data.eq(pak[c]["data"])
-        yield sink.k.eq(pak[c]["k"])
-        yield sink.stb.eq(1)
-        if "eop" in pak[c]:
-            yield sink.eop.eq(1)
-        else:
-            yield sink.eop.eq(0)
-        yield
-
-    # extra clk cycles
-    for _ in range(cyc, cyc + 20):
-        yield sink.data.eq(0)
-        yield sink.k.eq(0)
-        yield sink.stb.eq(0)
-        yield sink.eop.eq(0)
-        yield
-    metadata = dut.pipeline.header_decoder.metadata
-    img_header_layout = [
-        "stream_id",
-        "source_tag", # image index since powering on
-        "x_size",
-        "x_offset",
-        "y_size",
-        "y_offset",
-        "l_size",  # number of data words per image line
-        "pixel_format",
-        "tap_geo",
-        "flag",
-    ]
-    for name in img_header_layout:
-        print(f"{name} = {yield getattr(metadata, name):#04X} ", end="")
-    print()
-
-    roi = dut.pipeline.roi
-    print(f"x0 = {yield roi.cfg.x0} y0 = {yield roi.cfg.y0} | x1 = {yield roi.cfg.x1} y1 = {yield roi.cfg.y1}")
-    print(f"out count = {yield roi.out.count}")
-    assert True
-
-
-def testbench():
-    paks = [
-        {"data": C(0x7C7C7C7C, word_width), "k" : Replicate(1, 4)}, 
-        {"data": C(0x01010101, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x00000000, word_width), "k" : Replicate(0, 4)}, # stream id
-        {"data": C(0x00000000, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x6AEFACF6, word_width), "k" : Replicate(0, 4), "eop":0}, # crc
-
-        {"data": C(0x02020202, word_width), "k" : Replicate(0, 4)},  
-        {"data": C(0x00000000, word_width), "k" : Replicate(0, 4)}, # Xsize[23:16]
-        {"data": C(0x09090909, word_width), "k" : Replicate(0, 4)}, # Xsize[15:8] 
-        {"data": C(0x90909090, word_width), "k" : Replicate(0, 4)}, # Xsize[7:0] 
-        {"data": C(0x00000000, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x00000000, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x00000000, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x00000000, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x8EE1DAA1, word_width), "k" : Replicate(0, 4), "eop":0}, # crc
-
-        {"data": C(0x08080808, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x00000000, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x00000000, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x00000000, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x08080808, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x00000000, word_width), "k" : Replicate(0, 4)}, # DsizeL[23:16] 
-        {"data": C(0x02020202, word_width), "k" : Replicate(0, 4)}, # DsizeL[15:8] 
-        {"data": C(0x64646464, word_width), "k" : Replicate(0, 4)}, # DsizeL[7:0] 
-        {"data": C(0x01010101, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x01010101, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x00000000, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x00000000, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x00000000, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x51C243EA, word_width), "k" : Replicate(0, 4), "eop":0}, # crc
-
-        # the new line + pixel data
-        {"data": C(0x7C7C7C7C, word_width), "k" : Replicate(1, 4)}, 
-        {"data": C(0x02020202, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x0D0D0C0C, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x0B0B0C0C, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x0B0C0B0D, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x0D0B0C0B, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x0C0C0C0C, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x0B0B0C0B, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x0B0B0B0B, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x0C0B0B0C, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x0C0B0C0B, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x0B0B0A0B, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x0B0C0B0B, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x0C0C0C0B, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x0B0C0B0C, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x0C0C0B0C, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x0C0B0B0B, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x0C0C0C0B, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x0C0B0C0B, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x0C0C0C0C, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x0B0C0B0B, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x0C0B0B0B, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x0C0B0C0B, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x0B0B0D0A, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x0B0C0C0C, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x0B0B0B0C, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x0B0B0C0C, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x0B0B0C0B, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x0B0C0C0C, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x0B0C0C0C, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x0B0A0B0D, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x0B0B0C0C, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x0B0C0B0C, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x0D0C0C0B, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x0B0A0C0B, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x0D0D0B0A, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x0B0B0C0C, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x0B0C0C0B, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x0C0B0B0B, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x0B0C0C0B, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x0B0B0B0C, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x0B0B0B0C, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0xCB5DCDD6, word_width), "k" : Replicate(0, 4), "eop": 0}, # crc
-
-        # {"data": C(0x0C0B0C0B, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0D0B0B0B, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0D0B0C0B, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0B0C0C0C, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0B0B0C0C, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0B0C0B0C, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0C0B0C0C, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0C0D0B0B, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0B0C0C0A, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0D0C0B0B, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0B0D0C0B, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0B0C0C0C, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0B0C0B0B, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0B0C0C0D, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0A0C0C0D, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0C0B0B0C, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0C0B0C0B, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0C0C0B0B, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0C0B0B0C, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0B0B0B0A, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0C0C0C0C, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0C0B0B0C, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0C0C0C0C, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0B0C0B0B, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0B0C0B0C, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0C0C0C0B, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0B0C0B0C, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0C0C0D0C, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0B0C0C0C, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0B0B0B0C, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0C0C0B0B, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0B0B0B0B, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0C0B0C0C, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0C0B0B0C, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0C0B0C0C, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0D0B0D0B, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0B0B0D0C, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0B0B0C0C, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0B0B0B0A, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0B0C0C0C, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0B0C0B0C, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0C0B0A0B, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0C0C0C0C, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0D0C0C0B, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0B0C0B0C, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0C0C0C0C, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0C0C0C0B, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0C0B0B0C, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0C0B0B0C, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0C0B0C0B, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0C0C0C0B, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0C0C0D0B, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0C0D0C0B, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0C0C0D0C, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0B0C0D0C, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0B0B0C0C, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0C0C0B0B, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0C0C0D0C, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0C0C0B0B, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0D0C0D0B, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0C0C0C0C, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0B0D0B0C, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0D0C0C0B, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0C0B0C0C, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0D0D0B0B, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0B0C0B0B, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0D0B0C0C, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0C0C0B0B, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0C0C0B0C, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0C0C0C0B, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0B0C0B0C, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0C0B0C0B, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0B0C0C0D, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0D0C0C0C, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0C0C0B0C, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0C0C0C0C, word_dw), "k" : Replicate(0, 4)},  
-        # {"data": C(0x0BADF020, word_dw), "k" : Replicate(0, 4), "eop":0},  # crc
-    ]
-    yield from packet_sim(paks)
-
-
-def testbench_fake_data():
-    # config
-    pix_size = 8
-    # x_size = 2448
-    x_size = 10
-    y_size = 2
-
-    
-    l_size = ceil(x_size*pix_size/32)
-    pix_fmt = {
-        8: 0x0101,
-        10: 0x0102,
-        12: 0x0103,
-        14: 0x0104,
-        16: 0x0105,
-    }
-    # frame header
-    paks = [
-        {"data": C(0x7C7C7C7C, word_width), "k" : Replicate(1, 4)}, 
-        {"data": C(0x01010101, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x00000000, word_width), "k" : Replicate(0, 4)}, # stream id
-        {"data": C(0x00000000, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x6AEFACF6, word_width), "k" : Replicate(0, 4), "eop":0}, # fake crc
-
-        {"data": C(0x02020202, word_width), "k" : Replicate(0, 4)},  
-        {"data": C(0x00000000, word_width), "k" : Replicate(0, 4)}, # Xsize[23:16]
-        {"data": Replicate(C(x_size >> 8, char_width), 4), "k" : Replicate(0, 4)}, # Xsize[15:8] 
-        {"data": Replicate(C(x_size & 0xFF, char_width), 4), "k" : Replicate(0, 4)}, # Xsize[7:0] 
-        {"data": C(0x00000000, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x00000000, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x00000000, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x00000000, word_width), "k" : Replicate(0, 4)}, # Ysize[23:16]
-        {"data": C(0x8EE1DAA1, word_width), "k" : Replicate(0, 4), "eop":0}, # fake crc
-
-        {"data": Replicate(C(y_size >> 8, char_width), 4), "k" : Replicate(0, 4)}, # Ysize[15:8]
-        {"data": Replicate(C(y_size & 0xFF, char_width), 4), "k" : Replicate(0, 4)}, # Ysize[7:0]
-        {"data": C(0x00000000, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x00000000, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x08080808, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x00000000, word_width), "k" : Replicate(0, 4)}, # DsizeL[23:16] 
-        {"data": Replicate(C(l_size >> 8, char_width), 4), "k" : Replicate(0, 4)}, # DsizeL[15:8] 
-        {"data": Replicate(C(l_size & 0xFF, char_width), 4), "k" : Replicate(0, 4)}, # DsizeL[7:0] 
-        {"data": Replicate(C(pix_fmt[pix_size] >> 8, char_width), 4), "k" : Replicate(0, 4)}, # PixelF[15:8]
-        {"data": Replicate(C(pix_fmt[pix_size] & 0xFF, char_width), 4), "k" : Replicate(0, 4)}, # PixelF[7:0]
-        {"data": C(0x00000000, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x00000000, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x00000000, word_width), "k" : Replicate(0, 4)}, 
-        {"data": C(0x51C243EA, word_width), "k" : Replicate(0, 4), "eop":0}, # fake crc
-    ]
-
-    # pixel data
-    base = 0
-    for _ in range(y_size):
-        pix = []
-        for _ in range(x_size):
-            base += 1
-            pix.append(base)
-        print(pix)
-
-        packed = 0
-        for i, p in enumerate(pix):
-            packed += p << i*pix_size
-        # print(f"{packed:08X}")
-        
-        # new line indicator
-        paks += [
-            {"data": C(0x7C7C7C7C, word_width), "k" : Replicate(1, 4)}, 
-            {"data": C(0x02020202, word_width), "k" : Replicate(0, 4)}, 
-        ]
-        for i in range(l_size):
-            serialized = (packed & (0xFFFF_FFFF << i*word_width)) >> i*word_width
-            print(f"{serialized:08X}")
-            paks.append({"data": C(serialized, word_width), "k" : Replicate(0, 4)})
-
-    paks.append({"data": C(0xCB5DCDD6, word_width), "k" : Replicate(0, 4), "eop": 0}) # fake crc
-    
-    yield from packet_sim(paks)
-
-run_simulation(dut, testbench_fake_data(), vcd_name="sim-cxp.vcd")

sim_stream.py

@@ -1,154 +0,0 @@
-from migen import *
-from misoc.interconnect import stream
-
-from sim_pipeline import *
-from sim_generator import StreamData_Generator
-
-from src.gateware.cxp_pipeline import *
-
-class CXP_Links(Module):
-    def __init__(self):
-        # TODO: select the correct buffer to read from
-        # NOTE: although there are double buffer in each connect, the reading must be faster than writing to avoid data loss
-
-        self.downconn_sources = []
-        self.stream_sinks = []
-        for i in range(2):
-            downconn = Pipeline()
-            setattr(self.submodules, "cxp_conn"+str(i), downconn)
-            self.downconn_sources.append(downconn)
-
-            stream_pipeline = Stream_Pipeline()
-            setattr(self.submodules, "stream_pipeline"+str(i), stream_pipeline)
-            self.stream_sinks.append(stream_pipeline)
-
-        self.submodules.crossbar = Streams_Crossbar(self.downconn_sources, self.stream_sinks)
-        
-class Pipeline(Module):
-    def __init__(self):
-        self.submodules.generator = generator = StreamData_Generator()
-        self.submodules.dchar_decoder = dchar_decoder = Duplicated_Char_Decoder()
-        self.submodules.data_decoder = data_decoder = Control_Packet_Reader()
-        self.submodules.eop_marker = eop_marker = EOP_Marker()
-
-        # # #
-
-        pipeline = [generator, dchar_decoder, data_decoder, eop_marker]
-        for s, d in zip(pipeline, pipeline[1:]):
-            self.comb += s.source.connect(d.sink)
-        self.sink = pipeline[0].sink
-        self.source = pipeline[-1].source
-
-        # self.comb += self.source.ack.eq(1)
-
-
-dut = CXP_Links()
-
-def check_case(packet=[]):
-    print("=================TEST========================")
-
-    downconns = dut.downconn_sources
-    stream_buffers = dut.stream_sinks
-    ch = 0
-    
-    for i, p in enumerate(packet):
-        for x in range(len(downconns)):
-            if x == ch:
-                yield downconns[x].sink.data.eq(p["data"])
-                yield downconns[x].sink.k.eq(p["k"])
-                yield downconns[x].sink.stb.eq(1)
-            else:
-                yield downconns[x].sink.data.eq(0)
-                yield downconns[x].sink.k.eq(0)
-                yield downconns[x].sink.stb.eq(0)
-                yield downconns[x].sink.eop.eq(0)
-        if "eop" in p:
-            yield downconns[ch].sink.eop.eq(1)
-            # compensate for delay
-            # yield
-            # yield downconns[ch].sink.data.eq(0)
-            # yield downconns[ch].sink.k.eq(0)
-            # yield downconns[ch].sink.stb.eq(0)
-            # yield downconns[ch].sink.eop.eq(0)
-            # yield
-            # yield
-            # yield
-            ch = (ch + 1) % len(downconns)
-        else:
-            yield downconns[ch].sink.eop.eq(0)
-
-        # check cycle result
-        yield
-        # source = dut.stream_pipeline_sinks[0].source
-        source = dut.stream_sinks[0].double_buffer.source
-        print(
-            f"\nCYCLE#{i} : source char = {yield source.data:#X} k = {yield source.k:#X} stb = {yield source.stb} ack = {yield source.ack} eop = {yield source.eop}"
-            # f" source dchar = {yield source.dchar:#X} dchar_k = {yield source.dchar_k:#X}"
-            f"\nCYCLE#{i} : read mask = {yield dut.crossbar.mux.sel}"
-            # f"\nCYCLE#{i} : stream id = {yield decoder.stream_id:#X} pak_tag = {yield decoder.pak_tag:#X}"
-            # f" stream_pak_size = {yield decoder.stream_pak_size:#X}"
-        )
-        # crc = downconns[1].generator.crc_inserter.crc
-        # crc = dut.double_buffer.crc
-        # print(
-        #     f"CYCLE#{i} : crc error = {yield crc.error:#X} crc value = {yield crc.value:#X}"
-        #     f" crc data = {yield crc.data:#X} engine next = {yield crc.engine.next:#X} ce = {yield crc.ce}"
-        # )
-
-            
-    # extra clk cycles
-    cyc = i + 1
-    for i in range(cyc, cyc + 30):
-        for x in range(len(downconns)):
-            # yield won't reset every cycle
-            yield downconns[x].sink.data.eq(0)
-            yield downconns[x].sink.k.eq(0)
-            yield downconns[x].sink.stb.eq(0)
-            yield downconns[x].sink.eop.eq(0)
-        yield
-        print(
-            f"\nCYCLE#{i} : source char = {yield source.data:#X} k = {yield source.k:#X} stb = {yield source.stb} ack = {yield source.ack} eop = {yield source.eop}"
-            # f" source dchar = {yield source.dchar:#X} dchar_k = {yield source.dchar_k:#X}"
-            f"\nCYCLE#{i} : read mask = {yield dut.crossbar .mux.sel}"
-            # f"\nCYCLE#{i} : stream id = {yield decoder.stream_id:#X} pak_tag = {yield decoder.pak_tag:#X}"
-            # f" stream_pak_size = {yield decoder.stream_pak_size:#X}"
-        )
-    assert True
-
-
-def testbench():
-    # stream_id = 0x01
-    streams = [
-        [
-            {"data": 0x11111111, "k": Replicate(0, 4)},
-            {"data": 0xB105F00D, "k": Replicate(0, 4)},
-        ],
-        [
-            {"data": 0x22222222, "k": Replicate(0, 4)},
-            {"data": 0xC001BEA0, "k": Replicate(0, 4)},
-        ],
-        [
-            {"data": 0x33333333, "k": Replicate(0, 4)},
-            {"data": 0xC0A79AE5, "k": Replicate(0, 4)},
-        ],
-    ]
-
-    packet = []
-    for i, s in enumerate(streams):
-        s[-1]["eop"] = 0
-        packet += [
-            {"data": Replicate(C(i % 2, char_width), 4), "k": Replicate(0, 4)},
-            {"data": Replicate(C(i, char_width), 4), "k": Replicate(0, 4)},
-            {
-                "data": Replicate(C(len(s) >> 8 & 0xFF, char_width), 4),
-                "k": Replicate(0, 4),
-            },
-            {"data": Replicate(C(len(s) & 0xFF, char_width), 4), "k": Replicate(0, 4)},
-            *s,
-        ]
-
-
-    yield from check_case(packet)
-
-
-run_simulation(dut, testbench(), vcd_name="sim-cxp.vcd")

sim_test.py

@@ -1,34 +0,0 @@
-from migen import *
-from misoc.interconnect.csr import *
-from misoc.interconnect import stream
-
-class test(Module):
-    def __init__(self):
-
-        self.test_cnt = Signal(32, reset=0x03020100)
-
-        self.sync += [
-            self.test_cnt[:8].eq(self.test_cnt[:8] + 4),
-            self.test_cnt[8:16].eq(self.test_cnt[8:16] + 4),
-            self.test_cnt[16:24].eq(self.test_cnt[16:24] + 4),
-            self.test_cnt[24:].eq(self.test_cnt[24:] + 4),
-        ]
-
-
-
-dut = test()
-
-
-def packet_sim(packets=[]):
-
-    for _ in range(0x100):
-        yield
-    
-    assert True
-
-
-def testbench():
-    yield from packet_sim()
-
-
-run_simulation(dut, testbench(), vcd_name="sim-cxp.vcd")

src/.cargo/config

@@ -1,7 +1,6 @@
 [target.armv7-none-eabihf]
 rustflags = [
   "-C", "link-arg=-Tlink.x",
-  "-C", "target-feature=a9,armv7-a,neon",
   "-C", "target-cpu=cortex-a9",
 ]
 

src/Cargo.lock

@@ -82,9 +82,9 @@ checksum = "baf1de4339761588bc0619e3cbc0120ee582ebb74b53b4efbf79117bd2da40fd"
 
 [[package]]
 name = "compiler_builtins"
-version = "0.1.49"
+version = "0.1.70"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "20b1438ef42c655665a8ab2c1c6d605a305f031d38d9be689ddfef41a20f3aa2"
+checksum = "80873f979f0a344a4ade87c2f70d9ccf5720b83b10c97ec7cd745895d021e85a"
 
 [[package]]
 name = "core_io"
@@ -273,7 +273,6 @@ name = "libboard_artiq"
 version = "0.0.0"
 dependencies = [
  "build_zynq",
- "byteorder",
  "core_io",
  "crc",
  "embedded-hal",
@@ -547,7 +546,9 @@ name = "satman"
 version = "0.0.0"
 dependencies = [
  "build_zynq",
+ "byteorder",
  "core_io",
+ "crc",
  "cslice",
  "embedded-hal",
  "io",

src/armv7-none-eabihf.json

@@ -4,7 +4,7 @@
   "emit-debug-gdb-scripts": false,
   "env": "",
   "executables": true,
-  "features": "+v7,+vfp3,-d32,+thumb2,-neon",
+  "features": "+v7,+vfp3,-d32,+thumb2,+neon,+a9,+armv7-a",
   "is-builtin": false,
   "linker": "rust-lld",
   "linker-flavor": "ld.lld",

src/gateware/cxp.py

@@ -1,117 +0,0 @@
-from migen import *
-from migen.genlib.cdc import MultiReg, PulseSynchronizer
-from misoc.interconnect.csr import *
-from misoc.cores.coaxpress.common import word_width
-from misoc.cores.coaxpress.core import HostTXCore, HostRXCore
-from misoc.cores.coaxpress.phy.high_speed_gtx import HostRXPHYs
-from misoc.cores.coaxpress.phy.low_speed_serdes import HostTXPHYs
-
-from artiq.gateware.rtio import rtlink
-from artiq.gateware.rtio.phy.grabber import Serializer
-
-from cxp_frame_pipeline import Stream_Decoder, ROI
-
-class CXP_Core(Module, AutoCSR):
-    def __init__(self, tx_phy, rx_phy, command_buffer_depth=32, nrxslot=4):
-        # control buffer is only 32 words (128 bytes) for compatibility with version1.x compliant Devices
-        # Section 12.1.6 (CXP-001-2021)
-        self.buffer_depth, self.nslots = command_buffer_depth, nrxslot
-        
-        self.submodules.tx = HostTXCore(tx_phy, command_buffer_depth, False)
-        self.submodules.rx = HostRXCore(rx_phy, command_buffer_depth, nrxslot, False)
-
-    def get_tx_port(self):
-        return self.tx.writer.mem.get_port(write_capable=True)
-
-    def get_rx_port(self):
-        return self.rx.command_reader.mem.get_port(write_capable=False)
-
-    def get_mem_size(self):
-        return word_width * self.buffer_depth * self.nslots // 8
-
-
-class CXP_Grabber(Module, AutoCSR):
-    def __init__(
-        self,
-        refclk,
-        tx_pads,
-        rx_pads,
-        sys_clk_freq,
-        roi_engine_count=8,
-        res_width=16,
-        count_width=31,
-    ):
-        assert count_width <= 31
-
-        # Trigger rtio
-        nbit_trigdelay = 8
-        nbit_linktrig = 1
-        self.trigger = rtlink.Interface(rtlink.OInterface(nbit_trigdelay + nbit_linktrig))
-
-        
-        # ROI rtio
-         
-        # 4 configs (x0, y0, x1, y1) per roi_engine
-        self.config = rtlink.Interface(rtlink.OInterface(res_width, bits_for(4*roi_engine_count-1)))
-
-        # select which roi engine can output rtio_input signal
-        self.gate_data = rtlink.Interface(
-            rtlink.OInterface(roi_engine_count),
-            # the extra MSB bits is for sentinel
-            rtlink.IInterface(count_width+1, timestamped=False),
-        )
-
-        # # #
-
-        self.submodules.phy_tx = tx = HostTXPHYs(tx_pads, sys_clk_freq)
-        self.submodules.phy_rx = rx = HostRXPHYs(refclk, rx_pads, sys_clk_freq)
-        self.submodules.core = core = CXP_Core(tx.phys[0], rx.phys[0])
-        self.sync.rio += [
-            If(self.trigger.o.stb,
-                core.tx.trig_delay.eq(self.trigger.o.data[nbit_linktrig:]),
-                core.tx.trig_linktrigger_mode.eq(self.trigger.o.data[:nbit_linktrig]),
-            ),
-            core.tx.trig_stb.eq(self.trigger.o.stb),
-        ]
-
-        self.submodules.stream_decoder = stream_decoder = Stream_Decoder(res_width)
-        self.comb += core.rx.source.connect(stream_decoder.sink)
-
-        # ROI engines configuration and count gating
-        cdr = ClockDomainsRenamer("cxp_gt_rx")
-        roi_engines = [
-            cdr(ROI(stream_decoder.source_pixel4x, count_width))
-            for _ in range(roi_engine_count)
-        ]
-        self.submodules += roi_engines
-
-        for n, roi in enumerate(roi_engines):
-            cfg = roi.cfg
-            for offset, target in enumerate([cfg.x0, cfg.y0, cfg.x1, cfg.y1]):
-                roi_boundary = Signal.like(target)
-                self.sync.rio += If(self.config.o.stb & (self.config.o.address == 4*n+offset),
-                                roi_boundary.eq(self.config.o.data))
-                self.specials += MultiReg(roi_boundary, target, "cxp_gt_rx")
-
-        self.submodules.synchronizer = synchronizer = CXP_Synchronizer(roi_engines)
-        self.submodules.serializer = serializer = Serializer(synchronizer.update, synchronizer.counts, self.gate_data.i)
-        
-        self.sync.rio += If(self.gate_data.o.stb, serializer.gate.eq(self.gate_data.o.data))
-
-class CXP_Synchronizer(Module):
-    def __init__(self, roi_engines):
-        counts_in = [roi_engine.out.count for roi_engine in roi_engines]
-
-        # This assumes all ROI engines update at the same time.
-        self.update = Signal()
-        # stays valid until the next frame after self.update is pulsed.
-        self.counts = [Signal.like(count) for count in counts_in]
-
-        # # #
-
-        for i, o in zip(counts_in, self.counts):
-            self.specials += MultiReg(i, o)
-
-        self.submodules.ps = ps = PulseSynchronizer("cxp_gt_rx", "sys")
-        self.sync.cxp_gt_rx += ps.i.eq(roi_engines[0].out.update)
-        self.sync += self.update.eq(ps.o)

src/gateware/cxp_4r_fmc.py

@@ -1,82 +0,0 @@
-from migen.build.generic_platform import *
-
-fmc_adapter_io = [
-    # CoaXPress high speed link
-    ("CXP_HS", 0,
-        Subsignal("txp", Pins("HPC:DP0_C2M_P")),
-        Subsignal("txn", Pins("HPC:DP0_C2M_N")),
-        Subsignal("rxp", Pins("HPC:DP0_M2C_P")),
-        Subsignal("rxn", Pins("HPC:DP0_M2C_N")),
-    ),
-    ("CXP_HS", 1,
-        Subsignal("txp", Pins("HPC:DP1_C2M_P")),
-        Subsignal("txn", Pins("HPC:DP1_C2M_N")),
-        Subsignal("rxp", Pins("HPC:DP1_M2C_P")),
-        Subsignal("rxn", Pins("HPC:DP1_M2C_N")),
-    ),
-    ("CXP_HS", 2,
-        Subsignal("txp", Pins("HPC:DP2_C2M_P")),
-        Subsignal("txn", Pins("HPC:DP2_C2M_N")),
-        Subsignal("rxp", Pins("HPC:DP2_M2C_P")),
-        Subsignal("rxn", Pins("HPC:DP2_M2C_N")),
-    ),
-    ("CXP_HS", 3,
-        Subsignal("txp", Pins("HPC:DP3_C2M_P")),
-        Subsignal("txn", Pins("HPC:DP3_C2M_N")),
-        Subsignal("rxp", Pins("HPC:DP3_M2C_P")),
-        Subsignal("rxn", Pins("HPC:DP3_M2C_N")),
-    ),
-
-    # CoaXPress low speed link
-    ("CXP_LS", 0, Pins("HPC:LA00_CC_P"), IOStandard("LVCMOS33")),
-    ("CXP_LS", 1, Pins("HPC:LA01_CC_N"), IOStandard("LVCMOS33")),
-    ("CXP_LS", 2, Pins("HPC:LA01_CC_P"), IOStandard("LVCMOS33")),
-    ("CXP_LS", 3, Pins("HPC:LA02_N"), IOStandard("LVCMOS33")),
-
-    # CoaXPress green and red LED
-    ("CXP_LED", 0,
-        Subsignal("green", Pins("HPC:LA11_P"), IOStandard("LVCMOS33")),
-        Subsignal("red", Pins("HPC:LA11_N"), IOStandard("LVCMOS33")),
-    ),
-    ("CXP_LED", 1,
-        Subsignal("green", Pins("HPC:LA12_P"), IOStandard("LVCMOS33")),
-        Subsignal("red", Pins("HPC:LA12_N"), IOStandard("LVCMOS33")),
-    ),
-    ("CXP_LED", 2,
-        Subsignal("green", Pins("HPC:LA13_P"), IOStandard("LVCMOS33")),
-        Subsignal("red", Pins("HPC:LA13_N"), IOStandard("LVCMOS33")),
-    ),
-    ("CXP_LED", 3,
-        Subsignal("green", Pins("HPC:LA14_P"), IOStandard("LVCMOS33")),
-        Subsignal("red", Pins("HPC:LA14_N"), IOStandard("LVCMOS33")),
-    ),
-
-    # Power over CoaXPress 
-    ("PoCXP", 0,
-        Subsignal("enable", Pins("HPC:LA21_N"), IOStandard("LVCMOS33")),
-        Subsignal("alert", Pins("HPC:LA18_CC_P"), IOStandard("LVCMOS33")),
-    ),
-    ("PoCXP", 1,
-        Subsignal("enable", Pins("HPC:LA21_P"), IOStandard("LVCMOS33")),
-        Subsignal("alert", Pins("HPC:LA19_N"), IOStandard("LVCMOS33")),
-    ),
-    ("PoCXP", 2,
-        Subsignal("enable", Pins("HPC:LA22_N"), IOStandard("LVCMOS33")),
-        Subsignal("alert", Pins("HPC:LA19_P"), IOStandard("LVCMOS33")),
-    ),
-    ("PoCXP", 3,
-        Subsignal("enable", Pins("HPC:LA22_P"), IOStandard("LVCMOS33")),
-        Subsignal("alert", Pins("HPC:LA20_N"), IOStandard("LVCMOS33")),
-    ),
-    ("i2c", 0,
-        Subsignal("scl", Pins("HPC:IIC_SCL")),
-        Subsignal("sda", Pins("HPC:IIC_SDA")),
-        IOStandard("LVCMOS33")
-    ),
-
-    # On board 125MHz reference 
-    ("clk125", 0,
-        Subsignal("p", Pins("HPC:GBTCLK0_M2C_P")),
-        Subsignal("n", Pins("HPC:GBTCLK0_M2C_N")),
-    ),
-]

src/gateware/cxp_frame_pipeline.py

@@ -1,205 +0,0 @@
-from migen import *
-from migen.genlib.cdc import MultiReg, PulseSynchronizer
-from misoc.interconnect.csr import *
-from misoc.interconnect.stream import Buffer, SyncFIFO
-from misoc.cores.coaxpress.common import char_width, word_layout_dchar
-
-from operator import or_, add
-
-from stream import (
-    CXPCRC32_Checker,
-    End_of_line_Marker,
-    Frame_Header_Reader,
-    Pixel_Parser,
-    pixelword_layout,
-    Stream_Arbiter,
-)
-
-class ROI(Module):
-    """
-    ROI Engine. For each frame, accumulates pixels values within a
-    rectangular region of interest, and reports the total.
-    """
-    def __init__(self, pixel_4x, count_width):
-        assert len(pixel_4x) == 4
-
-        self.cfg = Record([
-            ("x0", len(pixel_4x[0].x)),
-            ("y0", len(pixel_4x[0].y)),
-            ("x1", len(pixel_4x[0].x)),
-            ("y1", len(pixel_4x[0].y)),
-        ])
-
-        self.out = Record([
-            ("update", 1),
-            # registered output - can be used as CDC input
-            ("count", count_width),
-        ])
-
-        # # #
-
-        roi_4x = [
-            Record([
-                ("x_good", 1),
-                ("y_good", 1),
-                ("gray", len(pixel_4x[0].gray)),
-                ("stb", 1),
-                ("count", count_width),
-            ]) for _ in range(4)
-            
-        ]
-
-        for pix, roi in zip(pixel_4x, roi_4x):
-            self.sync += [
-                # stage 1 - generate "good" (in-ROI) signals
-                roi.x_good.eq(0),
-                If((self.cfg.x0 <= pix.x) & (pix.x < self.cfg.x1),
-                    roi.x_good.eq(1)
-                ),
-
-                # the 4 pixels are on the same y level, no need for extra calculation
-                If(pix.y == self.cfg.y0,
-                    roi.y_good.eq(1)
-                ),
-                If(pix.y == self.cfg.y1,
-                    roi.y_good.eq(0)
-                ),
-                If(pix.eof,
-                    roi.x_good.eq(0),
-                    roi.y_good.eq(0)
-                ),
-                roi.gray.eq(pix.gray),
-                roi.stb.eq(pix.stb),
-
-                # stage 2 - accumulate
-                If((roi.stb & roi.x_good & roi.y_good),
-                    roi.count.eq(roi.count + roi.gray)
-                )
-            ]
-
-        eof = Signal()
-        eof_buf = Signal()
-        count_buf = [Signal(count_width), Signal(count_width)]
-        
-        # stage 3 - update
-        self.sync += [
-            eof.eq(reduce(or_, [pix.eof for pix in pixel_4x])),
-            eof_buf.eq(eof),
-            count_buf[0].eq(roi_4x[0].count + roi_4x[1].count),
-            count_buf[1].eq(roi_4x[2].count + roi_4x[3].count),
-
-            self.out.update.eq(0),
-            If(eof_buf,
-                [roi.count.eq(0) for roi in roi_4x],
-                self.out.update.eq(1),
-                self.out.count.eq(reduce(add, count_buf))
-            ),
-        ]
-
-
-class Stream_Decoder(Module, AutoCSR):
-    """
-    Convert the raw frame data into pixel data
-
-    Currently only support:
-    - Pixel format: mono8, mono10, mono12, mono14, mono16
-    - Tap geometry: 1X-1Y
-    - Scaning mode: area scanning
-
-    """
-    def __init__(self, res_width):
-        self.crc_error = CSR()
-        self.stream_type_error = CSR()
-
-        self.new_frame = CSR()
-        self.x_size = CSRStatus(3*char_width)
-        self.y_size = CSRStatus(3*char_width)
-        self.pixel_format = CSRStatus(2*char_width)
-
-        # # #
-         
-        cdr = ClockDomainsRenamer("cxp_gt_rx")
-        # 
-        #      32+8(dchar)                                                             32 
-        # sink ────/────> stream ────> buffer ────> crc checker ─────> frame header ───/───> end of line ─────> skid buffer ─────> pixel parser ─────> 4x pixel with
-        #                 arbiter                   reader                                   marker                                                    xy coordinate
-        # 
-         
-        
-        # Drops the packet header & K29.7 and mark eop on the crc word
-        self.submodules.arbiter = arbiter = cdr(Stream_Arbiter())
-        
-        # Buffer to improve timing
-        self.submodules.buffer = buffer = cdr(Buffer(word_layout_dchar))
-
-        # CRC 
-        self.submodules.crc_checker = crc_checker = cdr(CXPCRC32_Checker())
-        self.submodules.crc_error_ps = crc_error_ps = PulseSynchronizer("cxp_gt_rx", "sys")
-        self.sync.cxp_gt_rx += crc_error_ps.i.eq(crc_checker.error)
-        self.sync += [
-            If(crc_error_ps.o,
-                self.crc_error.w.eq(1),
-            ).Elif(self.crc_error.re,
-                self.crc_error.w.eq(0),
-            ),
-        ]
-
-        # Frame header extraction
-        self.submodules.header_reader = header_reader = cdr(Frame_Header_Reader())
-        # New frame and stream type error notification
-        self.submodules.new_frame_ps = new_frame_ps = PulseSynchronizer("cxp_gt_rx", "sys")
-        self.submodules.stream_type_err_ps = stream_type_err_ps = PulseSynchronizer("cxp_gt_rx", "sys")
-        self.sync.cxp_gt_rx += [
-            new_frame_ps.i.eq(header_reader.new_frame),
-            stream_type_err_ps.i.eq(header_reader.decode_err),
-        ]
-        self.sync += [
-            If(new_frame_ps.o,
-                self.new_frame.w.eq(1),
-            ).Elif(self.new_frame.re,
-                self.new_frame.w.eq(0),
-            ),
-            If(stream_type_err_ps.o,
-                self.stream_type_error.w.eq(1),
-            ).Elif(self.stream_type_error.re,
-                self.stream_type_error.w.eq(0),
-            )
-        ]
-
-        frame_header = header_reader.header
-        self.specials += [
-            MultiReg(frame_header.x_size, self.x_size.status),
-            MultiReg(frame_header.y_size, self.y_size.status),
-            MultiReg(frame_header.pixel_format, self.pixel_format.status),
-        ]
-
-
-        # Mark end of line for pixel parser
-        self.submodules.eol_marker = eol_marker = cdr(End_of_line_Marker())
-        self.sync.cxp_gt_rx += eol_marker.l_size.eq(header_reader.header.l_size)
-
-        # Skid buffer to prevent pipeline stalling
-        # At each linebreak, `Pixel_Parser.sink.ack` will fall for 1-2 cycle.
-        # Without the skid buffer , the whole pipleline will stall during that 1-2 cycle.
-        # 
-        # Due to the backpressure, 2 words line marker (4x K28.3 + 4x 0x02) will arrive as the linebreak indicator and will be consumed by `frame_header_reader`
-        # Thus, the buffer won't experience any data buildup.
-        self.submodules.skid_buf = skid_buf = cdr(SyncFIFO(pixelword_layout, 2))
-
-        self.submodules.parser = parser = cdr(Pixel_Parser(res_width))
-        self.sync.cxp_gt_rx += [
-            parser.x_size.eq(frame_header.x_size),
-            parser.y_size.eq(frame_header.y_size),
-            parser.pixel_format.eq(frame_header.pixel_format),
-        ]
-
-        # Connecting the pipeline
-        self.sink = arbiter.sink
-        self.comb += arbiter.sources[0].connect(buffer.sink)
-        self.pipeline = [buffer, crc_checker, header_reader, eol_marker, skid_buf, parser]
-        for s, d in zip(self.pipeline, self.pipeline[1:]):
-            self.comb += s.source.connect(d.sink)
-        
-
-        # For downstream ROI engine
-        self.source_pixel4x = parser.source_pixel4x

src/gateware/cxp_router.py

@@ -1,297 +0,0 @@
-from migen import *
-from misoc.interconnect.csr import *
-from misoc.interconnect.stream import Endpoint
-
-from cxp_pipeline import *
-# from src.gateware.cxp_pipeline import * # for sim only
-
-from types import SimpleNamespace
-from math import lcm
-from operator import or_, add
-
-word_layout_dchar_4x = [
-    ("data", 4*word_width),
-    ("k", 4*word_width//8), 
-    ("dchar", 4*char_width), 
-    ("dchar_k", 4*char_width//8),
-    ("valid", 4),
-]
-
-class Stream_Router(Module):
-    """
-    Match the id and route stream packet to the correct downstream and strip the packet header   
-    """
-    def __init__(self, routing_ids=[0]):
-        n_id = len(routing_ids)
-        assert n_id > 0
-
-        self.sources = [stream.Endpoint(word_layout_dchar) for _ in range(n_id)]
-        self.sink = stream.Endpoint(word_layout_dchar)
-
-        # # #
-
-        
-        stream_id = Signal(char_width)
-        pak_tag = Signal(char_width)
-        stream_pak_size = Signal(char_width * 2)
-
-        self.submodules.fsm = fsm = FSM(reset_state="WAIT_HEADER")
-
-        fsm.act(
-            "WAIT_HEADER",
-            self.sink.ack.eq(1),
-            If(
-                self.sink.stb,
-                NextValue(stream_id, self.sink.dchar),
-                NextState("GET_PAK_TAG"),
-            ),
-        )
-
-        fsm.act(
-            "GET_PAK_TAG",
-            self.sink.ack.eq(1),
-            If(
-                self.sink.stb,
-                NextValue(pak_tag, self.sink.dchar),
-                NextState("GET_PAK_SIZE_0"),
-            ),
-        )
-
-        fsm.act(
-            "GET_PAK_SIZE_0",
-            self.sink.ack.eq(1),
-            If(
-                self.sink.stb,
-                NextValue(stream_pak_size[8:], self.sink.dchar),
-                NextState("GET_PAK_SIZE_1"),
-            ),
-        )
-
-        routing_case = {"default": NextState("DISCARD")}
-        for id in (routing_ids):
-            routing_case[id] = [NextState(f"COPY_TO_BUFFER_{id}")]
-
-        fsm.act(
-            "GET_PAK_SIZE_1",
-            self.sink.ack.eq(1),
-            If(
-                self.sink.stb,
-                NextValue(stream_pak_size[:8], self.sink.dchar),
-                Case(stream_id, routing_case),
-            ),
-        )
-
-        for key in routing_case:
-            if key == "default":
-                fsm.act(
-                    "DISCARD",
-                    self.sink.ack.eq(1),
-                    If(self.sink.stb,
-                        NextValue(stream_pak_size, stream_pak_size - 1),
-                        If(stream_pak_size == 0,
-                            NextValue(stream_id, stream_id.reset),
-                            NextValue(pak_tag, pak_tag.reset),
-                            NextValue(stream_pak_size, stream_pak_size.reset),
-                            NextState("WAIT_HEADER"),
-                        )
-                    ),
-                )
-            else:
-                fsm.act(
-                    f"COPY_TO_BUFFER_{key}",
-                    self.sink.connect(self.sources[key]),
-
-                    # assume downstream is not blocked
-                    If(self.sink.stb,
-                        NextValue(stream_pak_size, stream_pak_size - 1),
-                        If(stream_pak_size == 0,
-                            NextValue(stream_id, stream_id.reset),
-                            NextValue(pak_tag, pak_tag.reset),
-                            NextValue(stream_pak_size, stream_pak_size.reset),
-                            NextState("WAIT_HEADER"),
-                        )
-                    ),
-                
-                )
-
-class Stream_Packet_Gearbox(Module):
-    """
-
-    1:4 gearbox
-
-    """
-    def __init__(self):
-        self.sink = Endpoint(word_layout_dchar)
-        self.source = Endpoint(word_layout_dchar_4x)
-
-        # # #
-
-        # TODO: take into account of stbs
-        sink_bits = len(self.sink.payload.raw_bits())
-        source_bits = len(self.source.payload.raw_bits()) - 4 # 4 extra "valid" bits
-        print(sink_bits, source_bits)
-        assert source_bits/sink_bits == 4
-
-        self.submodules.fsm = fsm = FSM(reset_state="0")
-
-
-        ring_buf_size = lcm(sink_bits, source_bits)
-        # ensure the shift register is at least twice the size of sink/source dw
-        if (ring_buf_size//sink_bits) < 2:
-            ring_buf_size = ring_buf_size * 2
-        if (ring_buf_size//source_bits) < 2:
-            ring_buf_size = ring_buf_size * 2
-
-        ring_buffer_layout = []
-        for name, width in word_layout_dchar:
-            ring_buffer_layout.append(
-                (name, width*ring_buf_size)
-            )
-        ring_buffer = Record(ring_buffer_layout)
-
-
-        # Control interface
-
-        reset_reg = Signal()
-        we = Signal()
-        re = Signal()
-        level = Signal(max=ring_buf_size)
-        w_cnt = Signal(max=ring_buf_size//sink_bits)
-        r_cnt = Signal(max=ring_buf_size//source_bits)
-
-        self.sync += [
-            If(reset_reg,
-                level.eq(level.reset),
-            ).Else(
-                If(we & ~re, level.eq(level + sink_bits)),
-                If(~we & re, level.eq(level - source_bits)),
-                If(we & re, level.eq(level + sink_bits - source_bits)),
-            ),
-
-            If(reset_reg,
-                w_cnt.eq(w_cnt.reset),
-                r_cnt.eq(r_cnt.reset),
-            ).Else(
-                If(we, 
-                    If(w_cnt == ((ring_buf_size//sink_bits) - 1),
-                        w_cnt.eq(w_cnt.reset),
-                    ).Else(
-                        w_cnt.eq(w_cnt + 1),
-                    )
-                ),
-                If(re, 
-                    If(r_cnt == ((ring_buf_size//source_bits) - 1),
-                        r_cnt.eq(r_cnt.reset),
-                    ).Else(
-                        r_cnt.eq(r_cnt + 1),
-                    )
-                ),
-            )
-        ]
-
-        # IO
-        sink_cases = {}
-        for i in range(ring_buf_size//sink_bits):
-            sink_cases[i] = []
-            for name, width in word_layout_dchar:
-                src = getattr(self.sink, name)
-                dst = getattr(ring_buffer, name)[width*i: width*(i+1)]
-                sink_cases[i].append(dst.eq(src))
-        self.sync += If(self.sink.stb, Case(w_cnt, sink_cases))
-
-        source_cases = {}
-        for i in range(ring_buf_size//source_dw):
-            source_cases[i] = []
-            for name, width in word_layout_dchar_4x:
-                src = getattr(ring_buffer, name)[width*i: width*(i+1)]
-                dst = getattr(self.source, name)
-                source_cases[i].append(dst.eq(src))
-        
-
-        
-class CXPCRC32_Checker(Module):
-    """
-    Verify crc in stream data packet and stream crc less output
-    """
-    def __init__(self):
-        self.error = Signal()
-
-        # TODO: change to fifo style like in LiteEthMACCRCChecker to improve timinig?
-        self.sink = stream.Endpoint(word_layout_dchar)
-        self.submodules.buf = buf = Buffer(word_layout_dchar)
-        self.source = buf.source
-
-        # # #
-
-        self.submodules.crc = crc = CXPCRC32(word_width)
-        self.comb += crc.data.eq(self.sink.data),
-
-        self.submodules.fsm = fsm = FSM(reset_state="INIT")
-        fsm.act("INIT",
-            crc.reset.eq(1),
-            NextState("CHECKING"),
-        )
-
-        fsm.act("RESET",
-            crc.reset.eq(1),
-            self.error.eq(crc.error),
-            NextState("CHECKING"),
-        )
-
-        fsm.act("CHECKING",
-            If(self.sink.stb & self.sink.eop,
-                # discard the crc
-                self.sink.ack.eq(1),
-                buf.source.eop.eq(1),
-                NextState("RESET"),
-            ).Else(
-                self.sink.connect(buf.sink),
-            ),
-            crc.ce.eq(self.sink.stb),
-        )
-    
-
-
-
-#
-# 4x word pipeline
-# 
-
-class Stream_Merger(Module):
-    """
-    Merge n channels stream packet into one sequentially 
-    """
-    def __init__(self, layout, n_channels):
-        assert n_channels > 1 # don't need a arbiter if there is only one channel
-
-        self.active_channels = Signal(n_channels) 
-
-        self.sinks = [stream.Endpoint(layout) for _ in range(n_channels)]
-        self.source = stream.Endpoint(layout)
-        # # #
-
-        self.submodules.fsm = fsm = FSM(reset_state="0")
-
-        # Section 9.5.5 (CXP-001-2021)
-        # When Multiple connections are active, stream packets are transmitted in
-        # ascending order of Connection ID
-        # Support ch0->1->2->4 topology only
-        for n, sink in enumerate(self.sinks):
-            if n < n_channels - 1:
-                fsm.act(str(n),
-                    sink.connect(self.source),
-                    If(sink.stb & sink.eop & self.source.ack,
-                        If(self.active_channels[n+1],
-                            NextState(str(n+1)),
-                        ). Else(
-                            NextState(str(0)),
-                        ),
-                    )
-                )
-            else:
-                fsm.act(str(n),
-                    sink.connect(self.source),
-                    If(sink.stb & sink.eop & self.source.ack,
-                       NextState(str(0))
-                    ),
-                )

src/gateware/zc706.py

@@ -13,7 +13,7 @@ from misoc.interconnect.csr import *
 from misoc.cores import gpio
 
 from artiq.gateware import rtio, nist_clock, nist_qc2
-from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, dds, spi2, edge_counter, cxp_grabber
+from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, dds, spi2, edge_counter
 from artiq.gateware.rtio.xilinx_clocking import fix_serdes_timing_path
 from artiq.gateware.drtio.transceiver import gtx_7series
 from artiq.gateware.drtio.siphaser import SiPhaser7Series
@@ -25,7 +25,6 @@ import analyzer
 import acpki
 import drtio_aux_controller
 import zynq_clocking
-import cxp_4r_fmc
 from config import generate_ident, write_csr_file, write_mem_file, write_rustc_cfg_file
 
 class SMAClkinForward(Module):
@@ -139,7 +138,7 @@ class ZC706(SoCCore):
         platform.add_extension(si5324_fmc33)
         self.comb += platform.request("si5324_33").rst_n.eq(1)
 
-        self.cdr_clk = Signal()
+        cdr_clk = Signal()
         cdr_clk_buf = Signal()
         si5324_out = platform.request("si5324_clkout")
         platform.add_period_constraint(si5324_out.p, 8.0)
@@ -147,11 +146,11 @@ class ZC706(SoCCore):
             Instance("IBUFDS_GTE2",
                 i_CEB=0,
                 i_I=si5324_out.p, i_IB=si5324_out.n,
-                o_O=self.cdr_clk,
+                o_O=cdr_clk,
                 p_CLKCM_CFG="TRUE",
                 p_CLKRCV_TRST="TRUE",
                 p_CLKSWING_CFG=3),
-            Instance("BUFG", i_I=self.cdr_clk, o_O=cdr_clk_buf)
+            Instance("BUFG", i_I=cdr_clk, o_O=cdr_clk_buf)
         ]
         self.config["HAS_SI5324"] = None
         self.config["SI5324_AS_SYNTHESIZER"] = None
@@ -653,85 +652,6 @@ class _NIST_QC2_RTIO:
         self.add_rtio(rtio_channels)
 
 
-class _CXP_FMC():
-    """
-    CoaXpress FMC with 4 CXP channel and 1 SMA trigger
-    """
-    def __init__(self):
-        platform = self.platform
-        platform.add_extension(cxp_4r_fmc.fmc_adapter_io)
-        platform.add_extension(leds_fmc33)
-
-        debug_sma = [
-            ("user_sma_clock_33", 0,
-                Subsignal("p_tx", Pins("AD18"), IOStandard("LVCMOS33")),
-                Subsignal("n_rx", Pins("AD19"), IOStandard("LVCMOS33")),
-            ),
-        ]
-
-        pmod1_33 = [
-            ("pmod1_33", 0, Pins("AJ21"), IOStandard("LVCMOS33")),
-            ("pmod1_33", 1, Pins("AK21"), IOStandard("LVCMOS33")),
-            ("pmod1_33", 2, Pins("AB21"), IOStandard("LVCMOS33")),
-            ("pmod1_33", 3, Pins("AB16"), IOStandard("LVCMOS33")),
-            ("pmod1_33", 4, Pins("Y20"), IOStandard("LVCMOS33")),
-            ("pmod1_33", 5, Pins("AA20"), IOStandard("LVCMOS33")),
-            ("pmod1_33", 6, Pins("AC18"), IOStandard("LVCMOS33")),
-            ("pmod1_33", 7, Pins("AC19"), IOStandard("LVCMOS33")),
-        ]
-
-        platform.add_extension(debug_sma)
-        platform.add_extension(pmod1_33)
-        debug_sma_pad = platform.request("user_sma_clock_33") 
-        pmod_pads = [platform.request("pmod1_33", i) for i in range(8)]
-
-        clk_freq = 125e6
-
-        links = 1
-        cxp_rx_pads = [platform.request("CXP_HS", i) for i in range(links)]
-        cxp_tx_pads = [platform.request("CXP_LS", i) for i in range(links)]
-
-        rtio_channels = []
-        self.submodules.cxp_grabber = cxp_grabber.CXP_Grabber(
-            refclk=self.cdr_clk,
-            tx_pads=cxp_tx_pads,
-            rx_pads=cxp_rx_pads,
-            sys_clk_freq=clk_freq,
-        )
-        mem_size = self.cxp_grabber.core.get_mem_size()
-        # upper half is tx while lower half is rx
-        memory_address = self.axi2csr.register_port(self.cxp_grabber.core.get_tx_port(), mem_size)
-        self.axi2csr.register_port(self.cxp_grabber.core.get_rx_port(), mem_size)
-        self.add_memory_region("cxp_mem", self.mem_map["csr"] + memory_address, mem_size * 2)
-        self.csr_devices.append("cxp_grabber")
-
-        print("CoaXPress at RTIO channel 0x{:06x}".format(len(rtio_channels)))
-        rtio_channels += [
-            rtio.Channel(self.cxp_grabber.trigger),
-            rtio.Channel(self.cxp_grabber.config),
-            rtio.Channel(self.cxp_grabber.gate_data),
-        ]
-        # max freq of cxp_gt_rx = linerate/internal_datawidth = 12.5Gbps/40 = 312.5MHz
-        # zc706 use speed grade 2 which only support up to 10.3125Gbps (~4ns)
-        # pushing to 12.5Gbps (3.2ns) will result in Pulse width violation but setup/hold times will still meet
-        rx = self.cxp_grabber.phy_rx.phys[0]
-        platform.add_period_constraint(rx.gtx.cd_cxp_gt_rx.clk, 3.2)
-        # constraint the clk path 
-        platform.add_false_path_constraints(self.sys_crg.cd_sys.clk, rx.gtx.cd_cxp_gt_rx.clk)
-
-        # FIXME remove this placeholder RTIO channel
-        # There are too few RTIO channels and cannot be compiled (adr width issue of the lane distributor)
-        # see https://github.com/m-labs/artiq/pull/2158 for similar issue
-        print("USER LED at RTIO channel 0x{:06x}".format(len(rtio_channels)))
-        phy = ttl_simple.Output(self.platform.request("user_led_33", 0))
-        self.submodules += phy
-        rtio_channels.append(rtio.Channel.from_phy(phy))
-        self.config["HAS_RTIO_LOG"] = None
-        rtio_channels.append(rtio.LogChannel())
-
-        self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
-        self.add_rtio(rtio_channels)
-
 class NIST_CLOCK(ZC706, _NIST_CLOCK_RTIO):
     def __init__(self, acpki, drtio100mhz):
         ZC706.__init__(self, acpki)
@@ -764,13 +684,8 @@ class NIST_QC2_Satellite(_SatelliteBase, _NIST_QC2_RTIO):
         _SatelliteBase.__init__(self, acpki, drtio100mhz)
         _NIST_QC2_RTIO.__init__(self)
 
-class CXP_Grabber(ZC706, _CXP_FMC):
-    def __init__(self, acpki, drtio100mhz):
-        ZC706.__init__(self, acpki)
-        _CXP_FMC.__init__(self)
-
 VARIANTS = {cls.__name__.lower(): cls for cls in [NIST_CLOCK, NIST_CLOCK_Master, NIST_CLOCK_Satellite,
-                                                  NIST_QC2, NIST_QC2_Master, NIST_QC2_Satellite, CXP_Grabber]}
+                                                  NIST_QC2, NIST_QC2_Master, NIST_QC2_Satellite]}
 
 def main():
     parser = argparse.ArgumentParser(

src/libboard_artiq/Cargo.toml.tpl

@@ -24,7 +24,6 @@ core_io = { git = "https://git.m-labs.hk/M-Labs/rs-core_io.git", rev = "e9d3edf0
 embedded-hal = "0.2"
 nb = "1.0"
 void = { version = "1", default-features = false }
-byteorder = { version = "1.3", default-features = false }
 
 io = { path = "../libio", features = ["byteorder"] }
 libboard_zynq = { path = "@@ZYNQ_RS@@/libboard_zynq" }

src/libboard_artiq/src/cxp.rs

@@ -1,387 +0,0 @@
-use core::{fmt, result::Result};
-
-use embedded_hal::blocking::delay::DelayMs;
-use libboard_zynq::{time::Milliseconds, timer::GlobalTimer};
-use libcortex_a9::mutex::Mutex;
-use log::{error, info};
-
-use crate::{cxp_ctrl::{read_u32, read_u64, reset_tag, send_test_packet, write_bytes_no_ack, write_u32, write_u64},
-            cxp_phys::{rx, tx, CXP_SPEED},
-            cxp_proto::Error as ProtoError,
-            pl::csr};
-
-// Bootstrap registers address
-const REVISION: u32 = 0x0004;
-const CONNECTION_RESET: u32 = 0x4000;
-const DEVICE_CONNECTION_ID: u32 = 0x4004;
-const MASTER_HOST_CONNECTION_ID: u32 = 0x4008;
-
-const STREAM_PACKET_SIZE_MAX: u32 = 0x4010;
-const CONNECTION_CFG: u32 = 0x4014;
-const CONNECTION_CFG_DEFAULT: u32 = 0x4018;
-
-const TESTMODE: u32 = 0x401C;
-const TEST_ERROR_COUNT_SELECTOR: u32 = 0x4020;
-const TEST_ERROR_COUNT: u32 = 0x4024;
-const TEST_PACKET_COUNT_TX: u32 = 0x4028;
-const TEST_PACKET_COUNT_RX: u32 = 0x4030;
-
-const VERSION_SUPPORTED: u32 = 0x4044;
-const VERSION_USED: u32 = 0x4048;
-
-// Setup const
-const CHANNEL_LEN: u8 = 1;
-const HOST_CONNECTION_ID: u32 = 0xC001C0DE; // TODO: rename this to CXP grabber sinara number
-// The MAX_STREAM_PAK_SIZE should be set as large as possible - Section 9.5.2 (CXP-001-2021)
-// Since the ROI pipeline just consume all pixel data without buffering, any big number will do.
-const MAX_STREAM_PAK_SIZE: u32 = 16384; // 16 KiB
-const TX_TEST_CNT: u8 = 10;
-// From DS191 (v1.18.1), max CDR time lock is 37*10^6 UI,
-// 37*10^6 UI at lowest CXP linerate of 1.25Gbps = 29.6 ms, double it to account for overhead
-const MONITOR_TIMEOUT_MS: u64 = 60;
-
-#[derive(Debug)]
-pub enum Error {
-    CameraNotDetected,
-    ConnectionLost,
-    UnstableRX,
-    UnstableTX,
-    UnsupportedSpeed(u32),
-    UnsupportedTopology,
-    UnsupportedVersion,
-    Protocol(ProtoError),
-}
-
-impl From<ProtoError> for Error {
-    fn from(value: ProtoError) -> Error {
-        Error::Protocol(value)
-    }
-}
-
-impl fmt::Display for Error {
-    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
-        match self {
-            &Error::CameraNotDetected => write!(f, "CameraNotDetected"),
-            &Error::ConnectionLost => write!(f, "ConnectionLost channel #0 cannot be detected"),
-            &Error::UnstableRX => write!(f, "UnstableRX RX connection test failed"),
-            &Error::UnstableTX => write!(f, "UnstableTX TX connection test failed"),
-            &Error::UnsupportedSpeed(linerate_code) => write!(
-                f,
-                "UnsupportedSpeed {:#X} linerate code is not supported",
-                linerate_code
-            ),
-            &Error::UnsupportedTopology => {
-                write!(
-                    f,
-                    "UnsupportedTopology channel #0 should be connected to the master channel"
-                )
-            }
-            &Error::UnsupportedVersion => write!(
-                f,
-                "UnsupportedVersion cannot find a compatible protocol version between the cxp grabber & camera"
-            ),
-            &Error::Protocol(ref err) => write!(f, "ProtocolError {}", err),
-        }
-    }
-}
-
-fn master_channel_ready() -> bool {
-    unsafe { csr::cxp_grabber::core_rx_ready_read() == 1 }
-}
-
-fn monitor_channel_status_timeout(timer: GlobalTimer) -> Result<(), Error> {
-    let limit = timer.get_time() + Milliseconds(MONITOR_TIMEOUT_MS);
-    while timer.get_time() < limit {
-        if master_channel_ready() {
-            return Ok(());
-        }
-    }
-    Err(Error::ConnectionLost)
-}
-
-fn discover_camera(mut timer: GlobalTimer) -> Result<(), Error> {
-    // Section 7.6 (CXP-001-2021)
-    // 1.25Gbps (CXP_1) and 3.125Gbps (CXP_3) are the discovery rate
-    // both linerate need to be checked as camera only support ONE of discovery rates
-    for speed in [CXP_SPEED::CXP_1, CXP_SPEED::CXP_3].iter() {
-        // Section 12.1.2 (CXP-001-2021)
-        // set tx linerate -> send ConnectionReset -> wait 200ms -> set rx linerate -> monitor connection status with a timeout
-        tx::change_linerate(*speed);
-        write_bytes_no_ack(CONNECTION_RESET, &1_u32.to_be_bytes(), false)?;
-        timer.delay_ms(200);
-        rx::change_linerate(*speed);
-
-        if monitor_channel_status_timeout(timer).is_ok() {
-            info!("camera detected at linerate {:}", speed);
-            return Ok(());
-        }
-    }
-    Err(Error::CameraNotDetected)
-}
-
-fn check_master_channel() -> Result<(), Error> {
-    if read_u32(DEVICE_CONNECTION_ID, false)? == 0 {
-        Ok(())
-    } else {
-        Err(Error::UnsupportedTopology)
-    }
-}
-
-fn disable_excess_channels(timer: GlobalTimer) -> Result<(), Error> {
-    let current_cfg = read_u32(CONNECTION_CFG, false)?;
-    let active_camera_chs = current_cfg >> 16;
-    // After camera receive ConnectionReset, only the master connection should be active while
-    // the extension connections shall not be active - Section 12.3.33 (CXP-001-2021)
-    // In case some camera didn't follow the spec properly (e.g. Basler boA2448-250cm),
-    // the grabber need to manually disable the excess channels
-    if active_camera_chs > CHANNEL_LEN as u32 {
-        info!(
-            "only {} channel(s) is avaiable on cxp grabber, disabling excess channels on camera",
-            CHANNEL_LEN
-        );
-        // disable excess channels and preserve the discovery linerate
-        write_u32(CONNECTION_CFG, current_cfg & 0xFFFF | (CHANNEL_LEN as u32) << 16, false)?;
-
-        // check if the master channel is down after the cfg change
-        monitor_channel_status_timeout(timer)
-    } else {
-        Ok(())
-    }
-}
-
-fn set_host_connection_id() -> Result<(), Error> {
-    info!("set host connection id to = {:#X}", HOST_CONNECTION_ID);
-    write_u32(MASTER_HOST_CONNECTION_ID, HOST_CONNECTION_ID, false)?;
-    Ok(())
-}
-
-fn negotiate_cxp_version() -> Result<bool, Error> {
-    let rev = read_u32(REVISION, false)?;
-
-    let mut major_rev: u32 = rev >> 16;
-    let mut minor_rev: u32 = rev & 0xFF;
-    info!("camera's CoaXPress revision is {}.{}", major_rev, minor_rev);
-
-    // Section 12.1.4 (CXP-001-2021)
-    // For CXP 2.0 and onward, Host need to check the VersionSupported register to determine
-    // the highest common version that supported by both device & host
-    if major_rev >= 2 {
-        let reg = read_u32(VERSION_SUPPORTED, false)?;
-
-        // grabber support CXP 2.1, 2.0 and 1.1 only
-        if ((reg >> 3) & 1) == 1 {
-            major_rev = 2;
-            minor_rev = 1;
-        } else if ((reg >> 2) & 1) == 1 {
-            major_rev = 2;
-            minor_rev = 0;
-        } else if ((reg >> 1) & 1) == 1 {
-            major_rev = 1;
-            minor_rev = 1;
-        } else {
-            return Err(Error::UnsupportedVersion);
-        }
-
-        write_u32(VERSION_USED, major_rev << 16 | minor_rev, false)?;
-    }
-    info!(
-        "both camera and cxp grabber support CoaXPress {}.{}, switch to CoaXPress {}.{} protcol now",
-        major_rev, minor_rev, major_rev, minor_rev
-    );
-
-    Ok(major_rev >= 2)
-}
-
-fn negotiate_pak_max_size(with_tag: bool) -> Result<(), Error> {
-    write_u32(STREAM_PACKET_SIZE_MAX, MAX_STREAM_PAK_SIZE, with_tag)?;
-    Ok(())
-}
-
-fn decode_cxp_speed(linerate_code: u32) -> Option<CXP_SPEED> {
-    match linerate_code {
-        0x28 => Some(CXP_SPEED::CXP_1),
-        0x30 => Some(CXP_SPEED::CXP_2),
-        0x38 => Some(CXP_SPEED::CXP_3),
-        0x40 => Some(CXP_SPEED::CXP_5),
-        0x48 => Some(CXP_SPEED::CXP_6),
-        0x50 => Some(CXP_SPEED::CXP_10),
-        0x58 => Some(CXP_SPEED::CXP_12),
-        _ => None,
-    }
-}
-
-fn set_operation_linerate(with_tag: bool, timer: GlobalTimer) -> Result<(), Error> {
-    let recommended_linerate_code = read_u32(CONNECTION_CFG_DEFAULT, with_tag)? & 0xFFFF;
-
-    if let Some(speed) = decode_cxp_speed(recommended_linerate_code) {
-        info!("changing linerate to {}", speed);
-
-        // preserve the number of active channels
-        let current_cfg = read_u32(CONNECTION_CFG, with_tag)?;
-        write_u32(
-            CONNECTION_CFG,
-            current_cfg & 0xFFFF0000 | recommended_linerate_code,
-            with_tag,
-        )?;
-
-        tx::change_linerate(speed);
-        rx::change_linerate(speed);
-        monitor_channel_status_timeout(timer)
-    } else {
-        Err(Error::UnsupportedSpeed(recommended_linerate_code))
-    }
-}
-
-fn test_counter_reset(with_tag: bool) -> Result<(), Error> {
-    unsafe { csr::cxp_grabber::core_rx_test_counts_reset_write(1) };
-    write_u32(TEST_ERROR_COUNT_SELECTOR, 0, with_tag)?;
-    write_u32(TEST_ERROR_COUNT, 0, with_tag)?;
-    write_u64(TEST_PACKET_COUNT_TX, 0, with_tag)?;
-    write_u64(TEST_PACKET_COUNT_RX, 0, with_tag)?;
-    Ok(())
-}
-
-fn verify_test_result(with_tag: bool) -> Result<(), Error> {
-    write_u32(TEST_ERROR_COUNT_SELECTOR, 0, with_tag)?;
-
-    // Section 9.9.3 (CXP-001-2021)
-    // verify grabber -> camera connection test result
-    if read_u64(TEST_PACKET_COUNT_RX, with_tag)? != TX_TEST_CNT as u64 {
-        return Err(Error::UnstableTX);
-    };
-    if read_u32(TEST_ERROR_COUNT, with_tag)? > 0 {
-        return Err(Error::UnstableTX);
-    };
-
-    // Section 9.9.4 (CXP-001-2021)
-    // verify camera -> grabber connection test result
-    let camera_test_pak_cnt = read_u64(TEST_PACKET_COUNT_TX, true)?;
-    unsafe {
-        if csr::cxp_grabber::core_rx_test_packet_counter_read() != camera_test_pak_cnt as u16 {
-            return Err(Error::UnstableRX);
-        };
-        if csr::cxp_grabber::core_rx_test_error_counter_read() > 0 {
-            return Err(Error::UnstableRX);
-        };
-    };
-    info!("channel #0 passed connection test");
-    Ok(())
-}
-
-fn test_channel_stability(with_tag: bool, mut timer: GlobalTimer) -> Result<(), Error> {
-    test_counter_reset(with_tag)?;
-
-    // cxp grabber -> camera connection test
-    for _ in 0..TX_TEST_CNT {
-        send_test_packet()?;
-        // sending the whole test sequence @ 20.833Mbps will take a minimum of 1.972ms
-        // and leave some room to send IDLE word
-        timer.delay_ms(2);
-    }
-
-    // camera -> grabber connection test
-    // enabling the TESTMODE on master channel will send test packets on all channels
-    // and ctrl packet write overhead is used as a delay
-    write_u32(TESTMODE, 1, with_tag)?;
-    write_u32(TESTMODE, 0, with_tag)?;
-
-    verify_test_result(with_tag)?;
-
-    Ok(())
-}
-
-fn camera_setup(timer: GlobalTimer) -> Result<bool, Error> {
-    reset_tag();
-    check_master_channel()?;
-
-    disable_excess_channels(timer)?;
-    set_host_connection_id()?;
-    let with_tag = negotiate_cxp_version()?;
-
-    negotiate_pak_max_size(with_tag)?;
-    set_operation_linerate(with_tag, timer)?;
-
-    test_channel_stability(with_tag, timer)?;
-
-    Ok(with_tag)
-}
-
-#[derive(Clone, Copy, Debug, PartialEq)]
-enum State {
-    Connected,
-    Detected,
-    Disconnected,
-}
-
-static mut STATE: Mutex<State> = Mutex::new(State::Disconnected);
-static mut WITH_TAG: Mutex<bool> = Mutex::new(false);
-
-// access by core1
-pub fn camera_connected() -> bool {
-    unsafe { *STATE.lock() == State::Connected }
-}
-
-pub fn with_tag() -> bool {
-    unsafe { *WITH_TAG.lock() }
-}
-
-pub fn tick(timer: GlobalTimer) {
-    let mut state_guard = unsafe { STATE.lock() };
-    let mut with_tag_guard = unsafe { WITH_TAG.lock() };
-    *state_guard = match *state_guard {
-        State::Disconnected => match discover_camera(timer) {
-            Ok(_) => State::Detected,
-            Err(_) => State::Disconnected,
-        },
-        State::Detected => match camera_setup(timer) {
-            Ok(with_tag) => {
-                *with_tag_guard = with_tag;
-                State::Connected
-            }
-            Err(e) => {
-                error!("camera setup failure: {}", e);
-                *with_tag_guard = false;
-                State::Disconnected
-            }
-        },
-        State::Connected => {
-            if master_channel_ready() {
-                unsafe {
-                    if csr::cxp_grabber::stream_decoder_crc_error_read() == 1 {
-                        error!("frame packet has CRC error");
-                        csr::cxp_grabber::stream_decoder_crc_error_write(1);
-                    };
-
-                    if csr::cxp_grabber::stream_decoder_stream_type_error_read() == 1 {
-                        error!("Non CoaXPress stream type detected, the CXP grabber doesn't support GenDC stream type");
-                        csr::cxp_grabber::stream_decoder_stream_type_error_write(1);
-                    };
-
-                    if csr::cxp_grabber::core_rx_trigger_ack_read() == 1 {
-                        info!("received trigger ack");
-                        csr::cxp_grabber::core_rx_trigger_ack_write(1);
-                    };
-
-                    if csr::cxp_grabber::stream_decoder_new_frame_read() == 1 {
-                        let width = csr::cxp_grabber::stream_decoder_x_size_read();
-                        let height = csr::cxp_grabber::stream_decoder_y_size_read();
-                        match csr::cxp_grabber::stream_decoder_pixel_format_code_read() {
-                            0x0101 => info!("received frame: {}x{} with MONO8 format", width, height),
-                            0x0102 => info!("received frame: {}x{} with MONO10 format", width, height),
-                            0x0103 => info!("received frame: {}x{} with MONO12 format", width, height),
-                            0x0104 => info!("received frame: {}x{} with MONO14 format", width, height),
-                            0x0105 => info!("received frame: {}x{} with MONO16 format", width, height),
-                            _ => info!("received frame: {}x{} with Unsupported pixel format", width, height),
-                        };
-                        csr::cxp_grabber::stream_decoder_new_frame_write(1);
-                    };
-                }
-                State::Connected
-            } else {
-                *with_tag_guard = false;
-                info!("camera disconnected");
-                State::Disconnected
-            }
-        }
-    };
-}

src/libboard_artiq/src/cxp_ctrl.rs

@@ -1,204 +0,0 @@
-use core::slice;
-
-use byteorder::{ByteOrder, NetworkEndian};
-use io::Cursor;
-use libboard_zynq::{time::Milliseconds, timer::GlobalTimer};
-
-use crate::{cxp_proto::{Error, RXPacket, TXPacket, CTRL_PACKET_MAXSIZE, DATA_MAXSIZE},
-            mem::mem,
-            pl::csr};
-
-const TRANSMISSION_TIMEOUT: u64 = 200;
-
-fn receive() -> Result<Option<RXPacket>, Error> {
-    if unsafe { csr::cxp_grabber::core_rx_pending_packet_read() == 1 } {
-        unsafe {
-            let read_buffer_ptr = csr::cxp_grabber::core_rx_read_ptr_read() as usize;
-            let ptr = (mem::CXP_MEM_BASE + mem::CXP_MEM_SIZE / 2 + read_buffer_ptr * CTRL_PACKET_MAXSIZE) as *mut u32;
-
-            let mut reader = Cursor::new(slice::from_raw_parts_mut(ptr as *mut u8, CTRL_PACKET_MAXSIZE));
-            let packet = RXPacket::read_from(&mut reader);
-
-            csr::cxp_grabber::core_rx_pending_packet_write(1);
-            Ok(Some(packet?))
-        }
-    } else {
-        Ok(None)
-    }
-}
-
-fn receive_timeout(timeout_ms: u64) -> Result<RXPacket, Error> {
-    // assume timer was initialized successfully
-    let timer = unsafe { GlobalTimer::get() };
-    let limit = timer.get_time() + Milliseconds(timeout_ms);
-    while timer.get_time() < limit {
-        match receive()? {
-            None => (),
-            Some(packet) => return Ok(packet),
-        }
-    }
-    Err(Error::TimedOut)
-}
-
-fn send_data_packet(packet: &TXPacket) -> Result<(), Error> {
-    // assume tx is enabled
-    unsafe {
-        while csr::cxp_grabber::core_tx_writer_busy_read() == 1 {}
-        let ptr = mem::CXP_MEM_BASE as *mut u32;
-        let mut writer = Cursor::new(slice::from_raw_parts_mut(ptr as *mut u8, CTRL_PACKET_MAXSIZE));
-
-        packet.write_to(&mut writer)?;
-
-        csr::cxp_grabber::core_tx_writer_word_len_write((writer.position() / 4) as u8);
-        csr::cxp_grabber::core_tx_writer_stb_write(1);
-    }
-
-    Ok(())
-}
-
-pub fn send_test_packet() -> Result<(), Error> {
-    // assume tx is enabled
-    unsafe {
-        while csr::cxp_grabber::core_tx_writer_busy_read() == 1 {}
-        csr::cxp_grabber::core_tx_writer_stb_testseq_write(1);
-    }
-    Ok(())
-}
-
-// Section 9.6.1.2 (CXP-001-2021)
-// CTRL packet need to be tagged for CXP 2.0 or greater
-static mut TAG: u8 = 0;
-
-pub fn reset_tag() {
-    unsafe { TAG = 0 }
-}
-
-fn increment_tag() {
-    unsafe { TAG = TAG.wrapping_add(1) };
-}
-
-fn check_tag(tag: Option<u8>) -> Result<(), Error> {
-    unsafe {
-        if tag.is_some() && tag != Some(TAG) {
-            Err(Error::TagMismatch)
-        } else {
-            Ok(())
-        }
-    }
-}
-
-fn check_length(length: u32) -> Result<(), Error> {
-    if length > DATA_MAXSIZE as u32 || length == 0 {
-        Err(Error::LengthOutOfRange)
-    } else {
-        Ok(())
-    }
-}
-
-fn process_ack_packet(timeout: u64) -> Result<(), Error> {
-    match receive_timeout(timeout) {
-        Ok(RXPacket::CtrlAck { tag }) => {
-            check_tag(tag)?;
-            Ok(())
-        }
-        Ok(RXPacket::CtrlDelay { tag, time }) => {
-            check_tag(tag)?;
-
-            // info!("delaying by {} ms ....", time);
-            process_ack_packet(time as u64)
-        }
-        Ok(_) => Err(Error::UnexpectedReply),
-        Err(e) => Err(e),
-    }
-}
-
-fn process_reply_packet(timeout: u64, expected_length: u32) -> Result<[u8; DATA_MAXSIZE], Error> {
-    match receive_timeout(timeout) {
-        Ok(RXPacket::CtrlReply { tag, length, data }) => {
-            check_tag(tag)?;
-
-            if length != expected_length {
-                return Err(Error::UnexpectedReply);
-            };
-
-            Ok(data)
-        }
-        Ok(RXPacket::CtrlDelay { tag, time }) => {
-            check_tag(tag)?;
-
-            // info!("delaying by {} ms ....", time);
-            process_reply_packet(time as u64, expected_length)
-        }
-        Ok(_) => Err(Error::UnexpectedReply),
-        Err(e) => Err(e),
-    }
-}
-
-pub fn write_bytes_no_ack(addr: u32, val: &[u8], with_tag: bool) -> Result<(), Error> {
-    let length = val.len() as u32;
-    check_length(length)?;
-
-    let mut data: [u8; DATA_MAXSIZE] = [0; DATA_MAXSIZE];
-    data[..length as usize].clone_from_slice(val);
-
-    let tag: Option<u8> = if with_tag { Some(unsafe { TAG }) } else { None };
-    send_data_packet(&TXPacket::CtrlWrite {
-        tag,
-        addr,
-        length,
-        data,
-    })
-}
-
-pub fn write_bytes(addr: u32, val: &[u8], with_tag: bool) -> Result<(), Error> {
-    write_bytes_no_ack(addr, val, with_tag)?;
-    process_ack_packet(TRANSMISSION_TIMEOUT)?;
-
-    if with_tag {
-        increment_tag();
-    };
-    Ok(())
-}
-
-pub fn write_u32(addr: u32, val: u32, with_tag: bool) -> Result<(), Error> {
-    write_bytes(addr, &val.to_be_bytes(), with_tag)
-}
-
-pub fn write_u64(addr: u32, val: u64, with_tag: bool) -> Result<(), Error> {
-    write_bytes(addr, &val.to_be_bytes(), with_tag)
-}
-
-fn read(addr: u32, length: u32, with_tag: bool) -> Result<(), Error> {
-    check_length(length)?;
-    let tag: Option<u8> = if with_tag { Some(unsafe { TAG }) } else { None };
-    send_data_packet(&TXPacket::CtrlRead { tag, addr, length })
-}
-
-pub fn read_bytes(addr: u32, bytes: &mut [u8], with_tag: bool) -> Result<(), Error> {
-    let length = bytes.len() as u32;
-    read(addr, length, with_tag)?;
-
-    let data = process_reply_packet(TRANSMISSION_TIMEOUT, length)?;
-    bytes.clone_from_slice(&data[..length as usize]);
-
-    if with_tag {
-        increment_tag();
-    };
-    Ok(())
-}
-
-pub fn read_u32(addr: u32, with_tag: bool) -> Result<u32, Error> {
-    let mut bytes: [u8; 4] = [0; 4];
-    read_bytes(addr, &mut bytes, with_tag)?;
-    let val = NetworkEndian::read_u32(&bytes);
-
-    Ok(val)
-}
-
-pub fn read_u64(addr: u32, with_tag: bool) -> Result<u64, Error> {
-    let mut bytes: [u8; 8] = [0; 8];
-    read_bytes(addr, &mut bytes, with_tag)?;
-    let val = NetworkEndian::read_u64(&bytes);
-
-    Ok(val)
-}

src/libboard_artiq/src/cxp_phys.rs

@@ -1,205 +0,0 @@
-use core::fmt;
-
-use log::info;
-
-use crate::pl::csr;
-
-#[derive(Clone, Copy, Debug)]
-#[allow(non_camel_case_types)]
-pub enum CXP_SPEED {
-    CXP_1,
-    CXP_2,
-    CXP_3,
-    CXP_5,
-    CXP_6,
-    CXP_10,
-    CXP_12,
-}
-
-impl fmt::Display for CXP_SPEED {
-    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
-        match self {
-            &CXP_SPEED::CXP_1 => write!(f, "1.25 Gbps"),
-            &CXP_SPEED::CXP_2 => write!(f, "2.5 Gbps"),
-            &CXP_SPEED::CXP_3 => write!(f, "3.125 Gbps"),
-            &CXP_SPEED::CXP_5 => write!(f, "5 Gbps"),
-            &CXP_SPEED::CXP_6 => write!(f, "6.25 Gbps"),
-            &CXP_SPEED::CXP_10 => write!(f, "10 Gbps"),
-            &CXP_SPEED::CXP_12 => write!(f, "12.5 Gbps"),
-        }
-    }
-}
-
-pub fn setup() {
-    let init_speed = CXP_SPEED::CXP_1;
-    info!("Setting up CXP phy and set linerate to {}", init_speed);
-    tx::setup();
-    tx::change_linerate(init_speed);
-    rx::setup();
-    rx::change_linerate(init_speed);
-}
-
-pub mod tx {
-    use super::*;
-
-    pub fn setup() {
-        unsafe {
-            csr::cxp_grabber::phy_tx_enable_write(1);
-        }
-    }
-
-    pub fn change_linerate(speed: CXP_SPEED) {
-        unsafe {
-            match speed {
-                CXP_SPEED::CXP_1 | CXP_SPEED::CXP_2 | CXP_SPEED::CXP_3 | CXP_SPEED::CXP_5 | CXP_SPEED::CXP_6 => {
-                    csr::cxp_grabber::phy_tx_bitrate2x_enable_write(0);
-                }
-                CXP_SPEED::CXP_10 | CXP_SPEED::CXP_12 => {
-                    csr::cxp_grabber::phy_tx_bitrate2x_enable_write(1);
-                }
-            };
-            csr::cxp_grabber::phy_tx_clk_reset_write(1);
-        }
-    }
-}
-
-pub mod rx {
-    use super::*;
-
-    pub fn setup() {
-        unsafe {
-            csr::cxp_grabber::phy_rx_gtx_refclk_stable_write(1);
-        }
-    }
-
-    pub fn change_linerate(speed: CXP_SPEED) {
-        change_qpll_fb_divider(speed);
-        change_gtx_divider(speed);
-        change_cdr_cfg(speed);
-
-        unsafe {
-            csr::cxp_grabber::phy_rx_qpll_reset_write(1);
-            while csr::cxp_grabber::phy_rx_qpll_locked_read() != 1 {}
-            // Changing RXOUT_DIV via DRP requires a manual reset
-            // https://adaptivesupport.amd.com/s/question/0D52E00006hplwnSAA/re-gtx-line-rate-change
-            csr::cxp_grabber::phy_rx_gtx_restart_write(1);
-        }
-    }
-
-    fn change_qpll_fb_divider(speed: CXP_SPEED) {
-        let qpll_div_reg = match speed {
-            CXP_SPEED::CXP_1 | CXP_SPEED::CXP_2 | CXP_SPEED::CXP_5 | CXP_SPEED::CXP_10 => 0x0120, // FB_Divider = 80, QPLL VCO @ 10GHz
-            CXP_SPEED::CXP_3 | CXP_SPEED::CXP_6 | CXP_SPEED::CXP_12 => 0x0170, // FB_Divider = 100, QPLL VCO @ 12.5GHz
-        };
-
-        // DEBUG:
-        // println!("QPLL DRP:");
-        // println!("0x36 = {:#06x}", qpll_read(0x36));
-        qpll_write(0x36, qpll_div_reg);
-        // println!("0x36 = {:#06x}", qpll_read(0x36));
-    }
-
-    fn change_gtx_divider(speed: CXP_SPEED) {
-        let div_reg = match speed {
-            CXP_SPEED::CXP_1 => 0x33,                      // RXOUT_DIV = 8
-            CXP_SPEED::CXP_2 | CXP_SPEED::CXP_3 => 0x22,   // RXOUT_DIV = 4
-            CXP_SPEED::CXP_5 | CXP_SPEED::CXP_6 => 0x11,   // RXOUT_DIV = 2
-            CXP_SPEED::CXP_10 | CXP_SPEED::CXP_12 => 0x00, // RXOUT_DIV = 1
-        };
-
-        // DEBUG:
-        // println!("RX GTX DRP:");
-        // println!("channel {}, 0x88 = {:#06x}", channel, gtx_read(channel, 0x88));
-        gtx_write(0x88, div_reg);
-        // println!("channel {}, 0x88 = {:#06x}", channel, gtx_read(channel, 0x88));
-    }
-
-    fn change_cdr_cfg(speed: CXP_SPEED) {
-        struct CdrConfig {
-            pub cfg_reg0: u16, // addr = 0xA8
-            pub cfg_reg1: u16, // addr = 0xA9
-            pub cfg_reg2: u16, // addr = 0xAA
-            pub cfg_reg3: u16, // addr = 0xAB
-            pub cfg_reg4: u16, // addr = 0xAC
-        }
-
-        let cdr_cfg = match speed {
-            // when RXOUT_DIV = 8
-            CXP_SPEED::CXP_1 => CdrConfig {
-                cfg_reg0: 0x0020,
-                cfg_reg1: 0x1008,
-                cfg_reg2: 0x23FF,
-                cfg_reg3: 0x0000,
-                cfg_reg4: 0x0003,
-            },
-            // when RXOUT_DIV = 4
-            CXP_SPEED::CXP_2 | CXP_SPEED::CXP_5 => CdrConfig {
-                cfg_reg0: 0x0020,
-                cfg_reg1: 0x1010,
-                cfg_reg2: 0x23FF,
-                cfg_reg3: 0x0000,
-                cfg_reg4: 0x0003,
-            },
-            // when RXOUT_DIV= 2
-            CXP_SPEED::CXP_3 | CXP_SPEED::CXP_6 => CdrConfig {
-                cfg_reg0: 0x0020,
-                cfg_reg1: 0x1020,
-                cfg_reg2: 0x23FF,
-                cfg_reg3: 0x0000,
-                cfg_reg4: 0x0003,
-            },
-            // when RXOUT_DIV= 1
-            CXP_SPEED::CXP_10 | CXP_SPEED::CXP_12 => CdrConfig {
-                cfg_reg0: 0x0020,
-                cfg_reg1: 0x1040,
-                cfg_reg2: 0x23FF,
-                cfg_reg3: 0x0000,
-                cfg_reg4: 0x000B,
-            },
-        };
-
-        gtx_write(0x0A8, cdr_cfg.cfg_reg0);
-        gtx_write(0x0A9, cdr_cfg.cfg_reg1);
-        gtx_write(0x0AA, cdr_cfg.cfg_reg2);
-        gtx_write(0x0AB, cdr_cfg.cfg_reg3);
-        gtx_write(0x0AC, cdr_cfg.cfg_reg4);
-    }
-
-    #[allow(dead_code)]
-    fn gtx_read(address: u16) -> u16 {
-        unsafe {
-            csr::cxp_grabber::phy_rx_gtx_daddr_write(address);
-            csr::cxp_grabber::phy_rx_gtx_dread_write(1);
-            while csr::cxp_grabber::phy_rx_gtx_dready_read() != 1 {}
-            csr::cxp_grabber::phy_rx_gtx_dout_read()
-        }
-    }
-
-    fn gtx_write(address: u16, value: u16) {
-        unsafe {
-            csr::cxp_grabber::phy_rx_gtx_daddr_write(address);
-            csr::cxp_grabber::phy_rx_gtx_din_write(value);
-            csr::cxp_grabber::phy_rx_gtx_din_stb_write(1);
-            while csr::cxp_grabber::phy_rx_gtx_dready_read() != 1 {}
-        }
-    }
-
-    #[allow(dead_code)]
-    fn qpll_read(address: u8) -> u16 {
-        unsafe {
-            csr::cxp_grabber::phy_rx_qpll_daddr_write(address);
-            csr::cxp_grabber::phy_rx_qpll_dread_write(1);
-            while csr::cxp_grabber::phy_rx_qpll_dready_read() != 1 {}
-            csr::cxp_grabber::phy_rx_qpll_dout_read()
-        }
-    }
-
-    fn qpll_write(address: u8, value: u16) {
-        unsafe {
-            csr::cxp_grabber::phy_rx_qpll_daddr_write(address);
-            csr::cxp_grabber::phy_rx_qpll_din_write(value);
-            csr::cxp_grabber::phy_rx_qpll_din_stb_write(1);
-            while csr::cxp_grabber::phy_rx_qpll_dready_read() != 1 {}
-        }
-    }
-}

src/libboard_artiq/src/cxp_proto.rs

@@ -1,346 +0,0 @@
-use core::fmt;
-
-use byteorder::{ByteOrder, NetworkEndian};
-use core_io::{Error as IoError, Read, Write};
-use crc::crc32::checksum_ieee;
-use io::Cursor;
-
-pub const CTRL_PACKET_MAXSIZE: usize = 128; // for compatibility with version1.x compliant Devices - Section 12.1.6 (CXP-001-2021)
-pub const DATA_MAXSIZE: usize =
-    CTRL_PACKET_MAXSIZE - /*packet start KCodes, data packet types, CMD, Tag, Addr, CRC, packet end KCode*/4*7;
-
-#[derive(Debug)]
-pub enum Error {
-    CorruptedPacket,
-    CtrlAckError(u8),
-    Io(IoError),
-    LengthOutOfRange,
-    TagMismatch,
-    TimedOut,
-    UnexpectedReply,
-    UnknownPacket(u8),
-}
-
-impl fmt::Display for Error {
-    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
-        match self {
-            &Error::CorruptedPacket => write!(f, "CorruptedPacket Received packet fail CRC test"),
-            &Error::CtrlAckError(ref ack_code) => match ack_code {
-                0x40 => write!(f, "CtrlAckError Invalid Address"),
-                0x41 => write!(f, "CtrlAckError Invalid data for the address"),
-                0x42 => write!(f, "CtrlAckError Invalid operation code"),
-                0x43 => write!(f, "CtrlAckError Write attempted to a read-only address"),
-                0x44 => write!(f, "CtrlAckError Read attempted from a write-only address"),
-                0x45 => write!(f, "CtrlAckError Size field too large, exceed packet size limit"),
-                0x46 => write!(f, "CtrlAckError Message size is inconsistent with size field"),
-                0x47 => write!(f, "CtrlAckError Malformed packet"),
-                0x80 => write!(f, "CtrlAckError Failed CRC test in last received command"),
-                _ => write!(f, "CtrlAckError Unknown ack code {:#X}", ack_code),
-            },
-            &Error::Io(ref err) => write!(f, "IoError {:?}", err),
-            &Error::LengthOutOfRange => write!(f, "LengthOutOfRange Message Length is too long"),
-            &Error::TagMismatch => write!(f, "TagMismatch Received tag is different from the transmitted tag"),
-            &Error::TimedOut => write!(f, "MessageTimedOut"),
-            &Error::UnexpectedReply => write!(f, "UnexpectedReply"),
-            &Error::UnknownPacket(packet_type) => write!(f, "UnknownPacket with type id {:#X} ", packet_type),
-        }
-    }
-}
-
-impl From<IoError> for Error {
-    fn from(value: IoError) -> Error {
-        Error::Io(value)
-    }
-}
-
-fn get_cxp_crc(bytes: &[u8]) -> u32 {
-    // Section 9.2.2.2 (CXP-001-2021)
-    // Only Control packet need CRC32 appended in the end of the packet
-    // CoaXpress use the polynomial of IEEE-802.3 (Ethernet) CRC but the checksum calculation is different
-    (!checksum_ieee(bytes)).swap_bytes()
-}
-
-trait CxpRead {
-    fn read_u8(&mut self) -> Result<u8, Error>;
-
-    fn read_u16(&mut self) -> Result<u16, Error>;
-
-    fn read_u32(&mut self) -> Result<u32, Error>;
-
-    fn read_u64(&mut self) -> Result<u64, Error>;
-
-    fn read_exact_4x(&mut self, buf: &mut [u8]) -> Result<(), Error>;
-
-    fn read_4x_u8(&mut self) -> Result<u8, Error>;
-
-    fn read_4x_u16(&mut self) -> Result<u16, Error>;
-
-    fn read_4x_u32(&mut self) -> Result<u32, Error>;
-}
-impl<Cursor: Read> CxpRead for Cursor {
-    fn read_u8(&mut self) -> Result<u8, Error> {
-        let mut bytes = [0; 1];
-        self.read_exact(&mut bytes)?;
-        Ok(bytes[0])
-    }
-
-    fn read_u16(&mut self) -> Result<u16, Error> {
-        let mut bytes = [0; 2];
-        self.read_exact(&mut bytes)?;
-        Ok(NetworkEndian::read_u16(&bytes))
-    }
-
-    fn read_u32(&mut self) -> Result<u32, Error> {
-        let mut bytes = [0; 4];
-        self.read_exact(&mut bytes)?;
-        Ok(NetworkEndian::read_u32(&bytes))
-    }
-
-    fn read_u64(&mut self) -> Result<u64, Error> {
-        let mut bytes = [0; 8];
-        self.read_exact(&mut bytes)?;
-        Ok(NetworkEndian::read_u64(&bytes))
-    }
-
-    fn read_exact_4x(&mut self, buf: &mut [u8]) -> Result<(), Error> {
-        for byte in buf {
-            // Section 9.2.2.1 (CXP-001-2021)
-            // decoder should immune to single bit errors when handling 4x duplicated characters
-            let a = self.read_u8()?;
-            let b = self.read_u8()?;
-            let c = self.read_u8()?;
-            let d = self.read_u8()?;
-            // vote and return majority
-            *byte = a & b & c | a & b & d | a & c & d | b & c & d;
-        }
-        Ok(())
-    }
-
-    fn read_4x_u8(&mut self) -> Result<u8, Error> {
-        let mut bytes = [0; 1];
-        self.read_exact_4x(&mut bytes)?;
-        Ok(bytes[0])
-    }
-
-    fn read_4x_u16(&mut self) -> Result<u16, Error> {
-        let mut bytes = [0; 2];
-        self.read_exact_4x(&mut bytes)?;
-        Ok(NetworkEndian::read_u16(&bytes))
-    }
-
-    fn read_4x_u32(&mut self) -> Result<u32, Error> {
-        let mut bytes = [0; 4];
-        self.read_exact_4x(&mut bytes)?;
-        Ok(NetworkEndian::read_u32(&bytes))
-    }
-}
-
-#[derive(Debug)]
-pub enum NameSpace {
-    GenICam,
-    DeviceSpecific,
-}
-
-#[derive(Debug)]
-pub enum RXPacket {
-    CtrlReply {
-        tag: Option<u8>,
-        length: u32,
-        data: [u8; DATA_MAXSIZE],
-    },
-    CtrlDelay {
-        tag: Option<u8>,
-        time: u32,
-    },
-    CtrlAck {
-        tag: Option<u8>,
-    },
-}
-
-impl RXPacket {
-    pub fn read_from(reader: &mut Cursor<&mut [u8]>) -> Result<Self, Error> {
-        match reader.read_4x_u8()? {
-            0x03 => RXPacket::get_ctrl_packet(reader, false),
-            0x06 => RXPacket::get_ctrl_packet(reader, true),
-            ty => Err(Error::UnknownPacket(ty)),
-        }
-    }
-
-    fn get_ctrl_packet(reader: &mut Cursor<&mut [u8]>, with_tag: bool) -> Result<Self, Error> {
-        let mut tag: Option<u8> = None;
-        if with_tag {
-            tag = Some(reader.read_4x_u8()?);
-        }
-
-        let ackcode = reader.read_4x_u8()?;
-
-        match ackcode {
-            0x00 | 0x04 => {
-                let length = reader.read_u32()?;
-                let mut data: [u8; DATA_MAXSIZE] = [0; DATA_MAXSIZE];
-                reader.read(&mut data[0..length as usize])?;
-
-                // Section 9.6.3 (CXP-001-2021)
-                // when length is not multiple of 4, dummy bits are padded to align to the word boundary
-                // set position to next word boundary for CRC calculation
-                let padding = (4 - (reader.position() % 4)) % 4;
-                reader.set_position(reader.position() + padding);
-
-                // Section 9.6.3 (CXP-001-2021)
-                // only bytes after the first 4 are used in calculating the checksum
-                let checksum = get_cxp_crc(&reader.get_ref()[4..reader.position()]);
-                if reader.read_u32()? != checksum {
-                    return Err(Error::CorruptedPacket);
-                }
-
-                if ackcode == 0x00 {
-                    return Ok(RXPacket::CtrlReply { tag, length, data });
-                } else {
-                    return Ok(RXPacket::CtrlDelay {
-                        tag,
-                        time: NetworkEndian::read_u32(&data[..4]),
-                    });
-                }
-            }
-            0x01 => return Ok(RXPacket::CtrlAck { tag }),
-            _ => return Err(Error::CtrlAckError(ackcode)),
-        }
-    }
-}
-
-trait CxpWrite {
-    fn write_u8(&mut self, value: u8) -> Result<(), Error>;
-
-    fn write_u32(&mut self, value: u32) -> Result<(), Error>;
-
-    fn write_all_4x(&mut self, buf: &[u8]) -> Result<(), Error>;
-
-    fn write_4x_u8(&mut self, value: u8) -> Result<(), Error>;
-
-    fn write_4x_u16(&mut self, value: u16) -> Result<(), Error>;
-
-    fn write_4x_u32(&mut self, value: u32) -> Result<(), Error>;
-}
-impl<Cursor: Write> CxpWrite for Cursor {
-    fn write_u8(&mut self, value: u8) -> Result<(), Error> {
-        self.write_all(&[value])?;
-        Ok(())
-    }
-
-    fn write_u32(&mut self, value: u32) -> Result<(), Error> {
-        let mut bytes = [0; 4];
-        NetworkEndian::write_u32(&mut bytes, value);
-        self.write_all(&bytes)?;
-        Ok(())
-    }
-
-    fn write_all_4x(&mut self, buf: &[u8]) -> Result<(), Error> {
-        for byte in buf {
-            self.write_all(&[*byte; 4])?;
-        }
-        Ok(())
-    }
-
-    fn write_4x_u8(&mut self, value: u8) -> Result<(), Error> {
-        self.write_all_4x(&[value])
-    }
-
-    fn write_4x_u16(&mut self, value: u16) -> Result<(), Error> {
-        let mut bytes = [0; 2];
-        NetworkEndian::write_u16(&mut bytes, value);
-        self.write_all_4x(&bytes)
-    }
-
-    fn write_4x_u32(&mut self, value: u32) -> Result<(), Error> {
-        let mut bytes = [0; 4];
-        NetworkEndian::write_u32(&mut bytes, value);
-        self.write_all_4x(&bytes)
-    }
-}
-
-#[derive(Debug)]
-pub enum TXPacket {
-    CtrlRead {
-        tag: Option<u8>,
-        addr: u32,
-        length: u32,
-    },
-    CtrlWrite {
-        tag: Option<u8>,
-        addr: u32,
-        length: u32,
-        data: [u8; DATA_MAXSIZE],
-    },
-    EventAck {
-        packet_tag: u8,
-    },
-}
-
-impl TXPacket {
-    pub fn write_to(&self, writer: &mut Cursor<&mut [u8]>) -> Result<(), Error> {
-        match *self {
-            TXPacket::CtrlRead { tag, addr, length } => {
-                match tag {
-                    Some(t) => {
-                        writer.write_4x_u8(0x05)?;
-                        writer.write_4x_u8(t)?;
-                    }
-                    None => {
-                        writer.write_4x_u8(0x02)?;
-                    }
-                }
-
-                let mut bytes = [0; 3];
-                NetworkEndian::write_u24(&mut bytes, length);
-                writer.write_all(&[0x00, bytes[0], bytes[1], bytes[2]])?;
-
-                writer.write_u32(addr)?;
-
-                // Section 9.6.2 (CXP-001-2021)
-                // only bytes after the first 4 are used in calculating the checksum
-                let checksum = get_cxp_crc(&writer.get_ref()[4..writer.position()]);
-                writer.write_u32(checksum)?;
-            }
-            TXPacket::CtrlWrite {
-                tag,
-                addr,
-                length,
-                data,
-            } => {
-                match tag {
-                    Some(t) => {
-                        writer.write_4x_u8(0x05)?;
-                        writer.write_4x_u8(t)?;
-                    }
-                    None => {
-                        writer.write_4x_u8(0x02)?;
-                    }
-                }
-
-                let mut bytes = [0; 3];
-                NetworkEndian::write_u24(&mut bytes, length);
-                writer.write_all(&[0x01, bytes[0], bytes[1], bytes[2]])?;
-
-                writer.write_u32(addr)?;
-                writer.write_all(&data[0..length as usize])?;
-
-                // Section 9.6.2 (CXP-001-2021)
-                // when length is not multiple of 4, dummy bites are padded to align to the word boundary
-                let padding = (4 - (writer.position() % 4)) % 4;
-                for _ in 0..padding {
-                    writer.write_u8(0)?;
-                }
-
-                // Section 9.6.2 (CXP-001-2021)
-                // only bytes after the first 4 are used in calculating the checksum
-                let checksum = get_cxp_crc(&writer.get_ref()[4..writer.position()]);
-                writer.write_u32(checksum)?;
-            }
-            TXPacket::EventAck { packet_tag } => {
-                writer.write_4x_u8(0x08)?;
-                writer.write_4x_u8(packet_tag)?;
-            }
-        }
-        Ok(())
-    }
-}

src/libboard_artiq/src/drtioaux.rs

@@ -1,4 +1,4 @@
-use core::slice;
+use core::{arch::asm, slice};
 
 use core_io::{Error as IoError, ErrorKind as IoErrorKind};
 use crc;
@@ -39,6 +39,7 @@ pub fn copy_work_buffer(src: *mut u32, dst: *mut u32, len: isize) {
     // fix for artiq-zynq#344
     unsafe {
         for i in 0..(len / 4) {
+            asm!("", options(preserves_flags, nostack, readonly));
             *dst.offset(i) = *src.offset(i);
         }
     }

src/libboard_artiq/src/fiq.rs

@@ -1,3 +1,5 @@
+use core::arch::asm;
+
 use libboard_zynq::{println, stdio};
 use libcortex_a9::{interrupt_handler, regs::MPIDR};
 use libregister::RegisterR;

src/libboard_artiq/src/lib.rs

@@ -1,9 +1,7 @@
 #![no_std]
 #![feature(never_type)]
 #![feature(naked_functions)]
-#![feature(asm)]
 
-extern crate byteorder;
 extern crate core_io;
 extern crate crc;
 extern crate embedded_hal;
@@ -26,7 +24,7 @@ pub mod fiq;
 #[cfg(feature = "target_kasli_soc")]
 pub mod io_expander;
 pub mod logger;
-#[cfg(any(has_drtio, has_cxp_grabber))]
+#[cfg(has_drtio)]
 #[rustfmt::skip]
 #[path = "../../../build/mem.rs"]
 pub mod mem;
@@ -43,15 +41,6 @@ pub mod si5324;
 pub mod si549;
 use core::{cmp, str};
 
-#[cfg(has_cxp_grabber)]
-pub mod cxp;
-#[cfg(has_cxp_grabber)]
-pub mod cxp_ctrl;
-#[cfg(has_cxp_grabber)]
-pub mod cxp_phys;
-#[cfg(has_cxp_grabber)]
-pub mod cxp_proto;
-
 pub fn identifier_read(buf: &mut [u8]) -> &str {
     unsafe {
         pl::csr::identifier::address_write(0);

src/libdwarf/src/eh.rs

@@ -85,7 +85,7 @@ unsafe fn get_ttype_entry(
         encoding | DW_EH_PE_pcrel,
         ttype_base,
     )
-    .map(|v| (v != ttype_base).then(|| v as *const u8))
+    .map(|v| (v != 0).then(|| v as *const u8))
 }
 
 pub unsafe fn find_eh_action(
@@ -275,6 +275,11 @@ unsafe fn read_encoded_pointer_with_base(reader: &mut DwarfReader, encoding: u8,
         _ => return Err(()),
     };
 
+    if result == 0 {
+        // null is just encoded as 0, even if a relative encoding is used for the table.
+        return Ok(0);
+    }
+
     result += if (encoding & 0x70) == DW_EH_PE_pcrel {
         original_ptr as usize
     } else {

src/libio/lib.rs

@@ -1,6 +1,5 @@
 #![no_std]
 #![feature(never_type)]
-#![feature(asm)]
 
 #[cfg(feature = "alloc")]
 extern crate alloc;

src/libksupport/src/cxp.rs

@@ -1,131 +0,0 @@
-use cslice::CMutSlice;
-use libboard_artiq::{cxp::{camera_connected, with_tag},
-                     cxp_ctrl,
-                     cxp_proto::DATA_MAXSIZE};
-use libc::c_char;
-use log::error;
-
-use crate::artiq_raise;
-
-// for downloading the XML files
-pub extern "C" fn cxp_read_chars(addr: i32, mut val: CMutSlice<c_char>) {
-    if camera_connected() {
-        let mut bytes: [u8; DATA_MAXSIZE] = [0; DATA_MAXSIZE];
-        match cxp_ctrl::read_bytes(addr as u32, &mut bytes[..val.len()], with_tag()) {
-            Ok(_) => {}
-            Err(e) => {
-                error!("{}", e);
-                // TODO: add cxp error?
-                artiq_raise!("UnwrapNoneError", "CXP error");
-            }
-        }
-
-        for i in 0..val.len() {
-            val.as_mut_slice()[i] = bytes[i] as c_char;
-        }
-    } else {
-        artiq_raise!("UnwrapNoneError", "Camera is not connected");
-    }
-}
-
-pub extern "C" fn cxp_readu32(addr: i32) -> i32 {
-    // TODO: add cxp error?
-    if camera_connected() {
-        match cxp_ctrl::read_u32(addr as u32, with_tag()) {
-            Ok(result) => result as i32,
-            Err(e) => {
-                error!("{}", e);
-                artiq_raise!("UnwrapNoneError", "CXP error");
-            }
-        }
-    } else {
-        artiq_raise!("UnwrapNoneError", "Camera is not connected");
-    }
-}
-
-pub extern "C" fn cxp_readu64(addr: i32) -> i64 {
-    // TODO: add cxp error?
-    if camera_connected() {
-        match cxp_ctrl::read_u64(addr as u32, with_tag()) {
-            Ok(result) => result as i64,
-            Err(e) => {
-                error!("{}", e);
-                artiq_raise!("UnwrapNoneError", "CXP error");
-            }
-        }
-    } else {
-        artiq_raise!("UnwrapNoneError", "Camera is not connected");
-    }
-}
-
-pub extern "C" fn cxp_writeu32(addr: i32, val: i32) {
-    // TODO: add cxp error?
-    if camera_connected() {
-        match cxp_ctrl::write_u32(addr as u32, val as u32, with_tag()) {
-            Ok(_) => {}
-            Err(e) => {
-                error!("{}", e);
-                artiq_raise!("UnwrapNoneError", "CXP error");
-            }
-        }
-    } else {
-        artiq_raise!("UnwrapNoneError", "Camera is not connected");
-    }
-}
-
-pub extern "C" fn cxp_writeu64(addr: i32, val: i64) {
-    // TODO: add cxp error?
-    if camera_connected() {
-        match cxp_ctrl::write_u64(addr as u32, val as u64, with_tag()) {
-            Ok(_) => {}
-            Err(e) => {
-                error!("{}", e);
-                artiq_raise!("UnwrapNoneError", "CXP error");
-            }
-        }
-    } else {
-        artiq_raise!("UnwrapNoneError", "Camera is not connected");
-    }
-}
-
-// DEBUG: ONLY
-pub extern "C" fn cxp_debug_frame_print() {
-    use libboard_zynq::println;
-
-    use crate::pl::csr;
-    unsafe {
-        // use crate::pl::csr::cxp_frame_pipeline;
-        if csr::cxp_grabber::stream_decoder_crc_error_read() == 1 {
-            println!("CRC error and clear");
-            csr::cxp_grabber::stream_decoder_crc_error_write(1);
-        } else {
-            println!("NO CRC error");
-        }
-        println!(
-            "grabber frame pixel format = {} | x_size = {} | y_size = {}",
-            csr::cxp_grabber::stream_decoder_pixel_format_code_read(),
-            csr::cxp_grabber::stream_decoder_x_size_read(),
-            csr::cxp_grabber::stream_decoder_y_size_read(),
-        );
-
-        if csr::cxp_grabber::core_rx_heartbeat_read() == 1 {
-            println!(
-                "host id = {:#X} | heartbeat = {:#X}",
-                csr::cxp_grabber::core_rx_host_id_read(),
-                csr::cxp_grabber::core_rx_device_time_read(),
-            );
-            csr::cxp_grabber::core_rx_heartbeat_write(1);
-        };
-
-        if csr::cxp_grabber::core_rx_trigger_ack_read() == 1 {
-            println!("Trigger ack recv and clear");
-            csr::cxp_grabber::core_rx_trigger_ack_write(1);
-        } else {
-            println!("NO Trigger ack");
-        }
-        println!(
-            "CH#0 Decode error = {}",
-            csr::cxp_grabber::core_rx_reader_decode_err_read()
-        );
-    }
-}

src/libksupport/src/irq.rs

@@ -1,4 +1,5 @@
-use core::sync::atomic::{AtomicBool, Ordering};
+use core::{arch::asm,
+           sync::atomic::{AtomicBool, Ordering}};
 
 use libboard_zynq::{gic, mpcore, println, stdio};
 use libcortex_a9::{asm, interrupt_handler, notify_spin_lock, regs::MPIDR, spin_lock_yield};

src/libksupport/src/kernel/api.rs

@@ -11,8 +11,6 @@ use super::{cache,
             core1::rtio_get_destination_status,
             dma, linalg,
             rpc::{rpc_recv, rpc_send, rpc_send_async}};
-#[cfg(has_cxp_grabber)]
-use crate::cxp;
 use crate::{eh_artiq, i2c, rtio};
 
 extern "C" {
@@ -128,20 +126,6 @@ pub fn resolve(required: &[u8]) -> Option<u32> {
         #[cfg(has_drtio)]
         api!(subkernel_await_message = subkernel::await_message),
 
-        // CoaXPress
-        #[cfg(has_cxp_grabber)]
-        api!(cxp_read_chars = cxp::cxp_read_chars),
-        #[cfg(has_cxp_grabber)]
-        api!(cxp_readu32 = cxp::cxp_readu32),
-        #[cfg(has_cxp_grabber)]
-        api!(cxp_readu64 = cxp::cxp_readu64),
-        #[cfg(has_cxp_grabber)]
-        api!(cxp_writeu32 = cxp::cxp_writeu32),
-        #[cfg(has_cxp_grabber)]
-        api!(cxp_writeu64 = cxp::cxp_writeu64),
-        #[cfg(has_cxp_grabber)]
-        api!(cxp_debug_frame_print = cxp::cxp_debug_frame_print),
-
         // Double-precision floating-point arithmetic helper functions
         // RTABI chapter 4.1.2, Table 2
         api!(__aeabi_dadd),

src/libksupport/src/kernel/core1.rs

@@ -8,7 +8,7 @@ use dyld::{self, elf::EXIDX_Entry, Library};
 use libboard_zynq::{gic, mpcore};
 use libcortex_a9::{asm::{dsb, isb},
                    cache::{bpiall, dcci_slice, iciallu},
-                   enable_fpu, sync_channel};
+                   sync_channel};
 use libsupport_zynq::ram;
 use log::{debug, error, info};
 
@@ -25,12 +25,14 @@ extern "C" {
 }
 
 unsafe fn attribute_writeback(typeinfo: *const ()) {
+    #[repr(C)]
     struct Attr {
         offset: usize,
         tag: CSlice<'static, u8>,
         name: CSlice<'static, u8>,
     }
 
+    #[repr(C)]
     struct Type {
         attributes: *const *const Attr,
         objects: *const *const (),
@@ -126,7 +128,6 @@ impl KernelImage {
 
 #[no_mangle]
 pub extern "C" fn main_core1() {
-    enable_fpu();
     debug!("Core1 started");
 
     ram::init_alloc_core1();

src/libksupport/src/lib.rs

@@ -1,10 +1,8 @@
 #![no_std]
-#![allow(incomplete_features)]
 #![feature(c_variadic)]
 #![feature(const_btree_new)]
 #![feature(inline_const)]
 #![feature(naked_functions)]
-#![feature(asm)]
 
 #[macro_use]
 extern crate alloc;
@@ -36,8 +34,6 @@ pub mod rtio;
 #[path = "../../../build/pl.rs"]
 pub mod pl;
 
-#[cfg(has_cxp_grabber)]
-pub mod cxp;
 
 #[derive(Debug, Clone)]
 pub struct RPCException {

src/libunwind/build.rs

@@ -23,7 +23,6 @@ mod llvm_libunwind {
         cfg.flag("--target=armv7-none-eabihf");
         cfg.flag("-O2");
         cfg.flag("-flto");
-        cfg.flag("-Wno-everything");
 
         cfg.flag("-std=c99");
         cfg.flag("-fstrict-aliasing");

src/runtime/src/main.rs

@@ -4,6 +4,7 @@
 #![feature(alloc_error_handler)]
 #![feature(const_btree_new)]
 #![feature(panic_info_message)]
+#![feature(lang_items)]
 
 #[macro_use]
 extern crate alloc;
@@ -13,8 +14,6 @@ use core::cell::RefCell;
 
 use ksupport;
 use libasync::task;
-#[cfg(has_cxp_grabber)]
-use libboard_artiq::cxp_phys;
 #[cfg(has_drtio_eem)]
 use libboard_artiq::drtio_eem;
 #[cfg(feature = "target_kasli_soc")]
@@ -80,23 +79,6 @@ mod grabber {
     }
 }
 
-#[cfg(has_cxp_grabber)]
-mod cxp {
-    use libasync::delay;
-    use libboard_artiq::cxp;
-    use libboard_zynq::time::Milliseconds;
-
-    use crate::GlobalTimer;
-
-    pub async fn grabber_thread(timer: GlobalTimer) {
-        let mut countdown = timer.countdown();
-        loop {
-            cxp::tick(timer);
-            delay(&mut countdown, Milliseconds(200)).await;
-        }
-    }
-}
-
 static mut LOG_BUFFER: [u8; 1 << 17] = [0; 1 << 17];
 
 #[no_mangle]
@@ -169,11 +151,5 @@ pub fn main_core0() {
 
     task::spawn(ksupport::report_async_rtio_errors());
 
-    #[cfg(has_cxp_grabber)]
-    {
-        cxp_phys::setup();
-        task::spawn(cxp::grabber_thread(timer));
-    }
-
     comms::main(timer, cfg);
 }

src/runtime/src/panic.rs

@@ -71,3 +71,7 @@ fn soft_panic(info: &core::panic::PanicInfo) -> ! {
     };
     soft_panic_main(timer, cfg);
 }
+
+#[lang = "eh_personality"]
+#[no_mangle]
+pub extern "C" fn rust_eh_personality() {}

src/rustfmt.toml

@@ -19,7 +19,7 @@ fn_single_line = false
 where_single_line = true
 imports_indent = "Visual"
 imports_layout = "Mixed"
-merge_imports = true
+imports_granularity = "Crate"
 group_imports = "StdExternalCrate"
 reorder_imports = true
 reorder_modules = true
@@ -54,7 +54,7 @@ use_field_init_shorthand = false
 force_explicit_abi = true
 condense_wildcard_suffixes = false
 color = "Auto"
-required_version = "1.4.37"
+required_version = "1.4.38"
 unstable_features = false
 disable_all_formatting = false
 skip_children = false

src/satman/src/main.rs

@@ -1,6 +1,7 @@
 #![no_std]
 #![no_main]
 #![feature(alloc_error_handler, never_type, panic_info_message)]
+#![feature(lang_items)]
 
 #[macro_use]
 extern crate log;
@@ -1810,3 +1811,7 @@ pub fn panic_fmt(info: &core::panic::PanicInfo) -> ! {
 
     loop {}
 }
+
+#[lang = "eh_personality"]
+#[no_mangle]
+pub extern "C" fn rust_eh_personality() {}

test.py

@@ -1,30 +0,0 @@
-from math import lcm
-
-word_dw = 32
-size = 8
-
-
-sink_dw, source_dw = word_dw, size * 4
-shift_reg_size = lcm(sink_dw, source_dw)
-if (shift_reg_size // sink_dw) < 2:
-    shift_reg_size = shift_reg_size * 2
-if (shift_reg_size // source_dw) < 2:
-    shift_reg_size = shift_reg_size * 2
-
-
-sink_aligned_bound = sink_dw
-result = []
-for i in range(4, shift_reg_size // size):
-    if i % 4 == 0:
-        while not (sink_aligned_bound + sink_dw >= i * size >= sink_aligned_bound):
-            sink_aligned_bound += word_dw
-    else:
-        if sink_aligned_bound + sink_dw >= i * size >= sink_aligned_bound:
-            result.append(i)
-
-    # print(i * size, sink_aligned_bound, sink_aligned_bound + sink_dw)
-
-print(source_dw % sink_dw)
-
-
-