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b48fc06fa3
...
925237face
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@ -6,9 +6,6 @@ from cxp_downconn import CXP_DownConn_PHY
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from cxp_upconn import CXP_UpConn_PHY
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from cxp_pipeline import *
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buffer_depth = 128
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@FullMemoryWE()
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class CXP(Module, AutoCSR):
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def __init__(self, refclk, downconn_pads, upconn_pads, sys_clk_freq, debug_sma, pmod_pads):
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self.submodules.upconn = UpConn_Interface(upconn_pads, sys_clk_freq, debug_sma, pmod_pads)
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@ -16,76 +13,11 @@ class CXP(Module, AutoCSR):
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self.submodules.downconn = DownConn_Interface(refclk, downconn_pads, sys_clk_freq, debug_sma, pmod_pads)
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# TODO: support the option high speed upconn
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self.submodules.transmitter = Transmitter()
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# TODO: add link layer
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def get_tx_port(self):
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return self.transmitter.mem.get_port(write_capable=True)
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def get_mem_size(self):
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return buffer_depth*downconn_dw
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@FullMemoryWE()
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class Transmitter(Module, AutoCSR):
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def __init__(self):
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self.cxp_tx_word_len = CSRStorage(bits_for(buffer_depth))
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self.cxp_tx = CSR()
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# # #
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self.specials.mem = mem = Memory(downconn_dw, buffer_depth)
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self.specials.mem_port = mem_port = mem.get_port()
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self.source = stream.Endpoint(downconn_layout)
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tx_done = Signal()
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addr_next = Signal(bits_for(buffer_depth))
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addr = Signal.like(addr_next)
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addr_rst = Signal()
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addr_inc = Signal()
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# increment addr in the same cycle the moment addr_inc is rise
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# since memory takes one cycle to shift to the correct addr
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self.sync += [
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addr.eq(addr_next),
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If(self.cxp_tx.re, self.cxp_tx.w.eq(1)),
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If(tx_done, self.cxp_tx.w.eq(0)),
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]
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self.comb += [
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addr_next.eq(addr),
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If(addr_rst,
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addr_next.eq(addr_next.reset),
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).Elif(addr_inc,
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addr_next.eq(addr + 1),
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),
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mem_port.adr.eq(addr_next),
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self.source.data.eq(mem_port.dat_r)
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]
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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addr_rst.eq(1),
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If(self.cxp_tx.re, NextState("TRANSMIT"))
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)
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fsm.act("TRANSMIT",
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self.source.stb.eq(1),
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If(self.source.ack,
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addr_inc.eq(1),
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),
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If(addr_next == self.cxp_tx_word_len.storage,
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tx_done.eq(1),
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NextState("IDLE")
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)
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)
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self.submodules.debug_out = debug_out = RX_Debug_Buffer()
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self.comb += self.source.connect(debug_out.sink)
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class DownConn_Interface(Module, AutoCSR):
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def __init__(self, refclk, downconn_pads, sys_clk_freq, debug_sma, pmod_pads):
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# # #
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self.submodules.phy = phy = CXP_DownConn_PHY(refclk, downconn_pads, sys_clk_freq, debug_sma, pmod_pads)
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@ -94,18 +26,16 @@ class DownConn_Interface(Module, AutoCSR):
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# DEBUG: TX pipeline
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self.submodules.debug_src = debug_src = TX_Command_Packet()
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self.submodules.trig_ack = trig_ack = Trigger_ACK()
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self.submodules.testseq = testseq = TX_Test_Packet()
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self.submodules.mux = mux = stream.Multiplexer(upconn_layout, 3)
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self.submodules.conv = conv = stream.StrideConverter(upconn_layout, downconn_layout)
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self.submodules.mux = mux = stream.Multiplexer(upconn_layout, 2)
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self.submodules.conv = conv = stream.StrideConverter(upconn_layout, downconn_layout, reverse=True)
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self.ack = CSR()
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self.mux_sel = CSRStorage(4)
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self.mux_sel = CSRStorage()
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self.sync += trig_ack.ack.eq(self.ack.re),
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self.comb += [
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debug_src.source.connect(mux.sink0),
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trig_ack.source.connect(mux.sink1),
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testseq.source.connect(mux.sink2),
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mux.sel.eq(self.mux_sel.storage)
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]
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@ -121,16 +51,6 @@ class DownConn_Interface(Module, AutoCSR):
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for s, d in zip(rx_pipeline, rx_pipeline[1:]):
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self.comb += s.source.connect(d.sink)
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self.packet_type = CSRStatus(8)
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self.decoder_error = CSRStatus()
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self.test_error = CSRStatus()
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self.comb += [
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self.packet_type.status.eq(recv_path.packet_type),
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self.decoder_error.status.eq(recv_path.decoder_err),
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self.test_error.status.eq(recv_path.test_err),
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]
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# DEBUG: CSR
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self.trig_ack = CSRStatus()
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self.trig_clr = CSR()
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@ -139,24 +59,6 @@ class DownConn_Interface(Module, AutoCSR):
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recv_path.trig_clr.eq(self.trig_clr.re),
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]
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pak_start = Signal()
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self.sync += [
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pak_start.eq(recv_path.packet_decoder.sink.data == 0xFBFBFBFB),
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]
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self.specials += [
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# # pmod 0-7 pin
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Instance("OBUF", i_I=recv_path.packet_decoder.test_err, o_O=pmod_pads[0]),
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Instance("OBUF", i_I=pak_start, o_O=pmod_pads[1]),
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# Instance("OBUF", i_I=fifo_in.source.ack, o_O=pmod_pads[2]),
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# Instance("OBUF", i_I=gtx.comma_checker.aligner_en, o_O=pmod_pads[3]),
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# Instance("OBUF", i_I=gtx.comma_checker.check_reset, o_O=pmod_pads[4]),
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# Instance("OBUF", i_I=gtx.comma_checker.has_comma, o_O=pmod_pads[5]),
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# Instance("OBUF", i_I=gtx.comma_checker.has_error, o_O=pmod_pads[6]),
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# Instance("OBUF", i_I=gtx.comma_checker.ready_sys, o_O=pmod_pads[7]),
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]
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class UpConn_Interface(Module, AutoCSR):
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def __init__(self, upconn_pads, sys_clk_freq, debug_sma, pmod_pads):
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@ -179,15 +81,6 @@ class UpConn_Interface(Module, AutoCSR):
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]
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# TODO: rewrite the transmite path into pipeline
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#
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# test pak ----+
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# from gw | 32 32 8
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# |---/---> mux -----> trig ack -----> idle word ---/--> conv ---/---> trig -----> PHY
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# | inserter inserter inserter
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# data pak ----+
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# from fw
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# Packet FIFOs with transmission priority
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# 0: Trigger packet
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self.submodules.trig = trig = TX_Trigger()
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@ -106,7 +106,7 @@ class CXP_DownConn_PHY(Module, AutoCSR):
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# DEBUG: remove cdc fifo
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# gtx rx -> fifo out -> cdc out
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fifo_out = stream.AsyncFIFO(downconn_layout, 512)
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fifo_out = stream.AsyncFIFO(downconn_layout, 128)
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self.submodules += ClockDomainsRenamer({"write": "cxp_gtx_rx", "read": "sys"})(fifo_out)
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self.sources.append(fifo_out)
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@ -114,7 +114,7 @@ class CXP_DownConn_PHY(Module, AutoCSR):
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self.sync.cxp_gtx_rx += [
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fifo_out.sink.stb.eq(0),
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# don't store idle word in fifo
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If((gtx.rx_ready & fifo_out.sink.ack & ~((gtx.decoders[0].d == 0xBC) & (gtx.decoders[0].k == 1))),
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If(gtx.rx_ready & fifo_out.sink.ack & (gtx.decoders[0].d != 0xBC),
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fifo_out.sink.stb.eq(1),
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fifo_out.sink.data[i*8:(i*8)+8].eq(gtx.decoders[i].d),
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fifo_out.sink.k[i].eq(gtx.decoders[i].k),
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@ -165,7 +165,7 @@ class CXP_DownConn_PHY(Module, AutoCSR):
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# DEBUG: datain
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# fw -> fifo (sys) -> cdc fifo -> gtx tx
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fifo_in = stream.AsyncFIFO(downconn_layout, 512)
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fifo_in = stream.AsyncFIFO(downconn_layout, 128)
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self.submodules += ClockDomainsRenamer({"write": "sys", "read": "cxp_gtx_tx"})(fifo_in)
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self.sinks.append(fifo_in)
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@ -173,28 +173,16 @@ class CXP_DownConn_PHY(Module, AutoCSR):
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txstb = Signal()
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self.specials += MultiReg(self.tx_stb.storage, txstb, odomain="cxp_gtx_tx")
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word_count = Signal(max=100)
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# JANK: fix the every 98th word got eaten
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# cnt 97 98 99 0
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# out fifo[97] IDLE IDLE fifo[99]
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# ack 1 0 0 1
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self.sync.cxp_gtx_tx += [
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fifo_in.source.ack.eq(0),
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If(word_count == 99,
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word_count.eq(word_count.reset),
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).Else(
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If(fifo_in.source.stb & txstb,
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If(word_count != 98, fifo_in.source.ack.eq(1)),
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word_count.eq(word_count + 1),
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)
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fifo_in.source.ack.eq(1),
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)
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]
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# NOTE: prevent the first word send twice due to stream stb delay
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self.comb += [
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If((fifo_in.source.stb & fifo_in.source.ack & (word_count != 99)),
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If(fifo_in.source.stb & fifo_in.source.ack,
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gtx.encoder.d[0].eq(fifo_in.source.data[:8]),
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gtx.encoder.d[1].eq(fifo_in.source.data[8:16]),
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gtx.encoder.d[2].eq(fifo_in.source.data[16:24]),
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@ -223,9 +211,9 @@ class CXP_DownConn_PHY(Module, AutoCSR):
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# Instance("OBUF", i_I=gtx.cd_cxp_gtx_tx.clk, o_O=debug_sma.n_rx),
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# # pmod 0-7 pin
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# Instance("OBUF", i_I=txstb, o_O=pmod_pads[0]),
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# Instance("OBUF", i_I=fifo_in.source.stb, o_O=pmod_pads[1]),
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# Instance("OBUF", i_I=fifo_in.source.ack, o_O=pmod_pads[2]),
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Instance("OBUF", i_I=txstb, o_O=pmod_pads[0]),
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Instance("OBUF", i_I=fifo_in.source.stb, o_O=pmod_pads[1]),
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Instance("OBUF", i_I=fifo_in.source.ack, o_O=pmod_pads[2]),
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# Instance("OBUF", i_I=gtx.comma_checker.aligner_en, o_O=pmod_pads[3]),
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# Instance("OBUF", i_I=gtx.comma_checker.check_reset, o_O=pmod_pads[4]),
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# Instance("OBUF", i_I=gtx.comma_checker.has_comma, o_O=pmod_pads[5]),
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@ -3,9 +3,6 @@ from misoc.interconnect.csr import *
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from misoc.interconnect import stream
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from misoc.cores.liteeth_mini.mac.crc import LiteEthMACCRCEngine, LiteEthMACCRCChecker
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import struct
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upconn_dw = 8
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upconn_layout = [("data", upconn_dw), ("k", upconn_dw//8)]
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@ -16,32 +13,24 @@ downconn_layout = [("data", downconn_dw), ("k", downconn_dw//8)]
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def K(x, y):
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return ((y << 5) | x)
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KCode = {
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"pak_start" : K(27, 7),
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"io_ack" : K(28, 6),
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"trig_indic_28_2" : K(28, 2),
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"trig_indic_28_4" : K(28, 4),
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"pak_end" : K(29, 7),
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}
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def _bytes2word(bytes, big_endian=True):
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if big_endian:
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return struct.unpack(">I", struct.pack(">4B", *bytes))[0]
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else:
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return struct.unpack("<I", struct.pack(">4B", *bytes))[0]
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def bytes2word(arr):
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assert len(arr) == 4
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sum = 0
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for i, val in enumerate(arr):
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sum += (val & 0xFF) << i*8
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return sum
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class Code_Source(Module):
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def __init__(self, layout, data, k):
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def __init__(self, layout, counts=4):
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self.source = stream.Endpoint(layout)
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self.stb = Signal()
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self.data = Signal.like(self.source.data)
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self.k = Signal.like(self.source.k)
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# # #
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assert len(data) == len(k) > 0
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counts = len(data)
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cnt = Signal() if counts == 1 else Signal(max=counts)
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cnt = Signal(max=counts)
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clr_cnt = Signal()
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inc_cnt = Signal()
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@ -64,8 +53,8 @@ class Code_Source(Module):
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fsm.act("WRITE",
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self.source.stb.eq(1),
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self.source.data.eq(Array(data)[cnt]),
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self.source.k.eq(Array(k)[cnt]),
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self.source.data.eq(self.data),
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self.source.k.eq(self.k),
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If(cnt == counts - 1,
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self.source.eop.eq(1),
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If(self.source.ack, NextState("IDLE"))
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@ -76,7 +65,7 @@ class Code_Source(Module):
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class Code_Inserter(Module):
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def __init__(self, layout, data, k, insert_infront=True):
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def __init__(self, layout, insert_infront=True, counts=4):
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self.sink = stream.Endpoint(layout)
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self.source = stream.Endpoint(layout)
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@ -84,8 +73,7 @@ class Code_Inserter(Module):
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self.k = Signal.like(self.sink.k)
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# # #
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assert len(data) == len(k) > 0
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counts = len(data)
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assert counts > 0
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cnt = Signal() if counts == 1 else Signal(max=counts)
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clr_cnt = Signal()
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@ -100,27 +88,24 @@ class Code_Inserter(Module):
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]
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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remove_sink_oep = 0 if insert_infront else 1
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# add code in front: IDLE -> INSERT -> COPY
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# add code at end: IDLE -> COPY -> INSERT
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if insert_infront:
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fsm.act("IDLE",
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self.sink.ack.eq(1),
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clr_cnt.eq(1),
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If(self.sink.stb,
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self.sink.ack.eq(0),
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NextState("INSERT" if insert_infront else "COPY"),
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NextState("INSERT"),
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)
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)
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fsm.act("INSERT",
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self.sink.ack.eq(0),
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self.source.stb.eq(1),
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self.source.data.eq(Array(data)[cnt]),
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self.source.k.eq(Array(k)[cnt]),
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self.source.data.eq(self.data),
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self.source.k.eq(self.k),
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If(cnt == counts - 1,
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If(remove_sink_oep, self.source.eop.eq(1)),
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If(self.source.ack, NextState("COPY" if insert_infront else "IDLE"))
|
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If(self.source.ack, NextState("COPY"))
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).Else(
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inc_cnt.eq(self.source.ack)
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)
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@ -128,22 +113,60 @@ class Code_Inserter(Module):
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fsm.act("COPY",
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self.sink.connect(self.source),
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If(remove_sink_oep, self.source.eop.eq(0)),
|
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If(self.sink.stb & self.sink.eop & self.source.ack,
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NextState("IDLE" if insert_infront else "INSERT"),
|
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NextState("IDLE"),
|
||||
)
|
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)
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|
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else:
|
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fsm.act("IDLE",
|
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self.sink.ack.eq(1),
|
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clr_cnt.eq(1),
|
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If(self.sink.stb,
|
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self.sink.ack.eq(0),
|
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NextState("COPY"),
|
||||
)
|
||||
)
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|
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fsm.act("COPY",
|
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self.sink.connect(self.source),
|
||||
self.source.eop.eq(0),
|
||||
If(self.sink.stb & self.sink.eop & self.source.ack,
|
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NextState("INSERT"),
|
||||
)
|
||||
)
|
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|
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fsm.act("INSERT",
|
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self.sink.ack.eq(0),
|
||||
self.source.stb.eq(1),
|
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self.source.data.eq(self.data),
|
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self.source.k.eq(self.k),
|
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If(cnt == counts - 1,
|
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self.source.eop.eq(1),
|
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If(self.source.ack, NextState("IDLE"))
|
||||
).Else(
|
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inc_cnt.eq(self.source.ack)
|
||||
),
|
||||
)
|
||||
|
||||
|
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class Packet_Wrapper(Module):
|
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def __init__(self, layout):
|
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self.submodules.pak_start = pak_start = Code_Inserter(layout, [KCode["pak_start"]]*4, [1]*4)
|
||||
self.submodules.pak_end = pak_end = Code_Inserter(layout, [KCode["pak_end"]]*4, [1]*4, insert_infront=False)
|
||||
self.submodules.pak_start = pak_start = Code_Inserter(layout)
|
||||
self.submodules.pak_end = pak_end = Code_Inserter(layout, insert_infront=False)
|
||||
|
||||
self.comb += pak_start.source.connect(pak_end.sink),
|
||||
self.sink = pak_start.sink
|
||||
self.source = pak_end.source
|
||||
|
||||
self.comb += [
|
||||
pak_start.data.eq(K(27, 7)),
|
||||
pak_start.k.eq(1),
|
||||
pak_end.data.eq(K(29, 7)),
|
||||
pak_end.k.eq(1),
|
||||
|
||||
pak_start.source.connect(pak_end.sink),
|
||||
]
|
||||
|
||||
@ResetInserter()
|
||||
@CEInserter()
|
||||
class CXPCRC32(Module):
|
||||
|
|
@ -182,28 +205,33 @@ class TX_Trigger(Module, AutoCSR):
|
|||
|
||||
# # #
|
||||
|
||||
# Table 15 & 16 (CXP-001-2021)
|
||||
# Send [K28.2, K28.4, K28.4] or [K28.4, K28.2, K28.2] and 3x delay as trigger packet
|
||||
self.submodules.code_src = code_src = Code_Source(upconn_layout, counts=3)
|
||||
self.comb += [
|
||||
code_src.stb.eq(self.trig_stb),
|
||||
code_src.data.eq(self.delay),
|
||||
code_src.k.eq(0)
|
||||
]
|
||||
|
||||
self.submodules.code_src = code_src = Code_Source(upconn_layout, [self.delay]*3, [0]*3)
|
||||
self.comb += code_src.stb.eq(self.trig_stb),
|
||||
|
||||
header = [Signal(8) for _ in range(3)]
|
||||
self.comb += \
|
||||
self.submodules.inserter_once = inserter_once = Code_Inserter(upconn_layout, counts=1)
|
||||
self.submodules.inserter_twice = inserter_twice = Code_Inserter(upconn_layout, counts=2)
|
||||
self.comb += [
|
||||
inserter_once.k.eq(1),
|
||||
inserter_twice.k.eq(1),
|
||||
If((self.linktrig_mode == 0) | (self.linktrig_mode == 2),
|
||||
header[0].eq(KCode["trig_indic_28_2"]),
|
||||
header[1].eq(KCode["trig_indic_28_4"]),
|
||||
header[2].eq(KCode["trig_indic_28_4"]),
|
||||
inserter_once.data.eq(K(28, 2)),
|
||||
inserter_twice.data.eq(K(28, 4)),
|
||||
).Else(
|
||||
header[0].eq(KCode["trig_indic_28_4"]),
|
||||
header[1].eq(KCode["trig_indic_28_2"]),
|
||||
header[2].eq(KCode["trig_indic_28_2"]),
|
||||
inserter_once.data.eq(K(28, 4)),
|
||||
inserter_twice.data.eq(K(28, 2)),
|
||||
)
|
||||
]
|
||||
|
||||
self.submodules.inserter = inserter = Code_Inserter(upconn_layout, header, [1]*3)
|
||||
tx_pipeline = [ code_src, inserter_twice, inserter_once]
|
||||
|
||||
self.comb += code_src.source.connect(inserter.sink)
|
||||
self.source = inserter.source
|
||||
for s, d in zip(tx_pipeline, tx_pipeline[1:]):
|
||||
self.comb += s.source.connect(d.sink)
|
||||
|
||||
self.source = tx_pipeline[-1].source
|
||||
|
||||
class Trigger_ACK(Module):
|
||||
def __init__(self):
|
||||
|
|
@ -213,14 +241,19 @@ class Trigger_ACK(Module):
|
|||
|
||||
# Section 9.3.2 (CXP-001-2021)
|
||||
# Send 4x K28.6 and 4x 0x01 as trigger packet ack
|
||||
self.submodules.code_src = code_src = Code_Source(upconn_layout, [0x01]*4, [0]*4)
|
||||
self.submodules.inserter = inserter = Code_Inserter(upconn_layout, [KCode["io_ack"]]*4, [1]*4)
|
||||
self.submodules.code_src = code_src = Code_Source(upconn_layout)
|
||||
self.submodules.k_code_inserter = k_code_inserter = Code_Inserter(upconn_layout)
|
||||
self.comb += [
|
||||
code_src.stb.eq(self.ack),
|
||||
code_src.source.connect(inserter.sink)
|
||||
code_src.data.eq(0x01),
|
||||
code_src.k.eq(0),
|
||||
k_code_inserter.data.eq(K(28, 6)),
|
||||
k_code_inserter.k.eq(1),
|
||||
|
||||
code_src.source.connect(k_code_inserter.sink)
|
||||
]
|
||||
|
||||
self.source = inserter.source
|
||||
self.source = k_code_inserter.source
|
||||
|
||||
class TX_Command_Packet(Module, AutoCSR):
|
||||
# Section 12.1.2 (CXP-001-2021)
|
||||
|
|
@ -265,23 +298,63 @@ class TX_Test_Packet(Module, AutoCSR):
|
|||
|
||||
# # #
|
||||
|
||||
self.submodules.test_pattern_src = test_pattern_src = Code_Source(upconn_layout, [*range(0x100)]*16, [0]*0x100*16)
|
||||
self.submodules.pak_type_inserter = pak_type_inserter = Code_Inserter(upconn_layout, [0x04]*4, [0]*4)
|
||||
testdata_src = stream.Endpoint(upconn_layout)
|
||||
|
||||
|
||||
# Section 9.9.2 (CXP-001-2021)
|
||||
# 0x00, 0x01 ... 0xFF need to be send 16 times
|
||||
# cnt[8:12] is used to count up 16 times while cnt[:8] is the data
|
||||
cnt = Signal(max=0x1000)
|
||||
clr_cnt = Signal()
|
||||
inc_cnt = Signal()
|
||||
|
||||
self.sync += [
|
||||
If(clr_cnt,
|
||||
cnt.eq(cnt.reset),
|
||||
).Elif(inc_cnt,
|
||||
cnt.eq(cnt + 1),
|
||||
),
|
||||
]
|
||||
|
||||
self.submodules.fsm = fsm = FSM(reset_state="IDLE")
|
||||
|
||||
fsm.act("IDLE",
|
||||
clr_cnt.eq(1),
|
||||
If(self.stb.re,
|
||||
NextState("WRITE")
|
||||
)
|
||||
)
|
||||
|
||||
fsm.act("WRITE",
|
||||
testdata_src.stb.eq(1),
|
||||
testdata_src.data.eq(cnt[:8]),
|
||||
testdata_src.k.eq(0),
|
||||
If(cnt == 0xFFF,
|
||||
testdata_src.eop.eq(1),
|
||||
If(testdata_src.ack, NextState("IDLE"))
|
||||
).Else(
|
||||
inc_cnt.eq(testdata_src.ack)
|
||||
)
|
||||
)
|
||||
|
||||
self.submodules.pak_type_inserter = pak_type_inserter = Code_Inserter(upconn_layout)
|
||||
self.submodules.pak_wrp = pak_wrp = Packet_Wrapper(upconn_layout)
|
||||
self.comb += [
|
||||
test_pattern_src.source.connect(pak_type_inserter.sink),
|
||||
pak_type_inserter.data.eq(0x04),
|
||||
pak_type_inserter.k.eq(0),
|
||||
|
||||
testdata_src.connect(pak_type_inserter.sink),
|
||||
pak_type_inserter.source.connect(pak_wrp.sink),
|
||||
]
|
||||
|
||||
self.source = pak_wrp.source
|
||||
self.sync += [
|
||||
test_pattern_src.stb.eq(self.stb.re),
|
||||
|
||||
self.sync += \
|
||||
If(self.stb.re,
|
||||
self.busy.status.eq(1),
|
||||
).Elif(self.source.eop & self.source.ack,
|
||||
self.busy.status.eq(0)
|
||||
)
|
||||
]
|
||||
|
||||
class RX_Debug_Buffer(Module,AutoCSR):
|
||||
def __init__(self):
|
||||
|
|
@ -306,52 +379,8 @@ class Receiver_Path(Module, AutoCSR):
|
|||
self.trig_ack = Signal()
|
||||
self.trig_clr = Signal()
|
||||
|
||||
# TODO:
|
||||
self.packet_type = Signal(8)
|
||||
self.decoder_err = Signal()
|
||||
self.decoder_err_clr = Signal()
|
||||
|
||||
self.test_err = Signal()
|
||||
self.test_err_clr = Signal()
|
||||
|
||||
# # #
|
||||
|
||||
|
||||
self.submodules.trig_ack_checker = trig_ack_checker = CXP_Trig_Ack_Checker()
|
||||
self.submodules.packet_decoder = packet_decoder = CXP_Data_Packet_Decode()
|
||||
|
||||
# Error are latched
|
||||
self.sync += [
|
||||
If(trig_ack_checker.ack,
|
||||
self.trig_ack.eq(1),
|
||||
).Elif(self.trig_clr,
|
||||
self.trig_ack.eq(0),
|
||||
),
|
||||
|
||||
If(packet_decoder.decode_err,
|
||||
self.decoder_err.eq(1),
|
||||
).Elif(self.decoder_err_clr,
|
||||
self.decoder_err.eq(0),
|
||||
),
|
||||
|
||||
If(packet_decoder.test_err,
|
||||
self.test_err.eq(1),
|
||||
).Elif(self.test_err_clr,
|
||||
self.test_err.eq(0),
|
||||
)
|
||||
]
|
||||
self.comb += [
|
||||
self.packet_type.eq(packet_decoder.packet_type),
|
||||
|
||||
]
|
||||
|
||||
pipeline = [ trig_ack_checker, packet_decoder ]
|
||||
|
||||
for s, d in zip(pipeline, pipeline[1:]):
|
||||
self.comb += s.source.connect(d.sink)
|
||||
|
||||
self.sink = pipeline[0].sink
|
||||
self.source = pipeline[-1].source
|
||||
|
||||
|
||||
|
||||
class CXP_Data_Packet_Decode(Module):
|
||||
|
|
@ -360,111 +389,9 @@ class CXP_Data_Packet_Decode(Module):
|
|||
# This is where data stream comes out
|
||||
self.source = stream.Endpoint(downconn_layout)
|
||||
|
||||
self.packet_type = Signal(8)
|
||||
self.decode_err = Signal()
|
||||
|
||||
self.buffer = Signal(40*downconn_dw)
|
||||
self.test_err = Signal()
|
||||
# # #
|
||||
|
||||
# decoder -> priorities mux(normal packet vs trigger ack) -> data packet mux (control ack, data stream, heartbeat, testmode, (optional Genlcam event))
|
||||
type = {
|
||||
"data_stream": 0x01,
|
||||
"control_ack_no_tag": 0x03,
|
||||
"test_packet": 0x04,
|
||||
"control_ack_with_tag": 0x06,
|
||||
"event_ack": 0x08,
|
||||
"heartbeat": 0x09,
|
||||
|
||||
"debug" : 0x02,
|
||||
}
|
||||
|
||||
self.submodules.fsm = fsm = FSM(reset_state="IDLE")
|
||||
|
||||
fsm.act("IDLE",
|
||||
self.sink.ack.eq(1),
|
||||
# TODO: add error correction?
|
||||
If((self.sink.stb & (self.sink.data == _bytes2word([KCode["pak_start"]]*4)) & (self.sink.k == 0b1111)),
|
||||
NextState("DECODE"),
|
||||
)
|
||||
)
|
||||
|
||||
# TODO: decode all packet type here
|
||||
|
||||
cnt = Signal(max=0x100)
|
||||
|
||||
fsm.act("DECODE",
|
||||
self.sink.ack.eq(1),
|
||||
If(self.sink.stb,
|
||||
NextValue(self.packet_type, self.sink.data[:8]),
|
||||
|
||||
Case(self.sink.data[:8],{
|
||||
type["data_stream"]: NextState("STREAMING"),
|
||||
type["debug"]: NextState("STREAMING"),
|
||||
type["test_packet"]: [
|
||||
NextValue(cnt, 0),
|
||||
NextState("VERIFY_TEST_PATTERN"),
|
||||
],
|
||||
"default": [
|
||||
self.decode_err.eq(1),
|
||||
# wait till next valid packet
|
||||
NextState("IDLE"),
|
||||
],
|
||||
}),
|
||||
)
|
||||
)
|
||||
|
||||
# Section 9.9.1 (CXP-001-2021)
|
||||
# the received test data packet (0x00, 0x01 ... 0xFF)
|
||||
# need to be compared against the local test sequence generator
|
||||
fsm.act("VERIFY_TEST_PATTERN",
|
||||
self.sink.ack.eq(1),
|
||||
If(self.sink.stb,
|
||||
If(((self.sink.data == _bytes2word([KCode["pak_end"]]*4)) & (self.sink.k == 0b1111)),
|
||||
NextState("IDLE"),
|
||||
).Else(
|
||||
If(((self.sink.data != Cat(cnt, cnt+1, cnt+2, cnt+3))),
|
||||
self.test_err.eq(1),
|
||||
),
|
||||
If(cnt == 0xFC,
|
||||
NextValue(cnt, cnt.reset),
|
||||
).Else(
|
||||
NextValue(cnt, cnt + 4)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
||||
)
|
||||
|
||||
fsm.act("STREAMING",
|
||||
If((self.sink.stb & (self.sink.data == _bytes2word([KCode["pak_end"]]*4)) & (self.sink.k == 0b1111)),
|
||||
# discard K29,7
|
||||
self.sink.ack.eq(1),
|
||||
NextState("IDLE")
|
||||
).Else(
|
||||
self.sink.connect(self.source),
|
||||
)
|
||||
)
|
||||
# # input pipeline stage - determine packet length based on type
|
||||
# self.sync += [
|
||||
# packet_start.eq((self.sink.data[0] == K(27, 7)) & (self.sink.k[0] == 1)),
|
||||
# packet_end.eq((self.sink.data[0] == K(29, 7)) & (self.sink.k[0] == 1)),
|
||||
|
||||
# If((self.sink.data[0] == K(27, 7)) & (self.sink.k[0] == 1),
|
||||
# packet_buffer_load.eq(1),
|
||||
# ),
|
||||
|
||||
|
||||
# trig_ack.eq((self.sink.data[0] == K(28, 6)) & (self.sink.k[0] == 1)),
|
||||
# If(trig_ack,
|
||||
# self.trig_ack.eq(self.sink.data[0]),
|
||||
# trig_ack.eq(0),
|
||||
# ).Elif(packet_buffer_load,
|
||||
# # TODO: add test packet counting
|
||||
# Case(buffer_count,
|
||||
# {i: buffer[i*downconn_dw:(i+1)*downconn_dw].eq(self.sink.data)
|
||||
# for i in range(40)}),
|
||||
# buffer_count.eq(buffer_count + 1),
|
||||
self.comb += self.sink.connect(self.source)
|
||||
|
||||
|
||||
class CXP_Trig_Ack_Checker(Module, AutoCSR):
|
||||
|
|
@ -487,7 +414,7 @@ class CXP_Trig_Ack_Checker(Module, AutoCSR):
|
|||
)
|
||||
|
||||
fsm.act("COPY",
|
||||
If((self.sink.stb & (self.sink.data == _bytes2word([KCode["io_ack"]]*4)) & (self.sink.k == 0b1111)),
|
||||
If((self.sink.stb & (self.sink.data == bytes2word([K(28, 6)]*4)) & (self.sink.k == 0b1111)),
|
||||
# discard K28,6
|
||||
self.sink.ack.eq(1),
|
||||
NextState("CHECK_ACK")
|
||||
|
|
@ -501,7 +428,7 @@ class CXP_Trig_Ack_Checker(Module, AutoCSR):
|
|||
NextState("IDLE"),
|
||||
# discard the word after K28,6
|
||||
self.sink.ack.eq(1),
|
||||
If(self.sink.data == _bytes2word([0x01]*4),
|
||||
If(self.sink.data == bytes2word([0x01]*4),
|
||||
self.ack.eq(1),
|
||||
)
|
||||
)
|
||||
|
|
|
|||
|
|
@ -698,15 +698,6 @@ class CXP_FMC():
|
|||
)
|
||||
self.csr_devices.append("cxp")
|
||||
|
||||
# TODO: add memory for tx & rx CXP
|
||||
memory_name = "cxp_tx"
|
||||
mem_size = self.cxp.get_mem_size()
|
||||
memory_address = self.axi2csr.register_port(self.cxp.get_tx_port(), mem_size)
|
||||
self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, mem_size)
|
||||
cxp_memory_group = [ memory_name ]
|
||||
self.add_memory_group("cxp_mem", cxp_memory_group)
|
||||
|
||||
|
||||
# max freq of cxp_gtx_rx = linerate/internal_datawidth = 12.5Gbps/40 = 312.5MHz
|
||||
# zc706 use speed grade 2 which only support up to 10.3125Gbps (4ns)
|
||||
# pushing to 12.5Gbps (3.2ns) will result in Pulse width violation but setup/hold times are met
|
||||
|
|
|
|||
|
|
@ -37,12 +37,7 @@ pub fn loopback_testing(timer: &mut GlobalTimer, speed: CXP_SPEED) {
|
|||
while csr::cxp::downconn_phy_rx_ready_read() != 1 {}
|
||||
info!("rx ready!");
|
||||
|
||||
csr::cxp::downconn_phy_tx_stb_write(1);
|
||||
cxp_proto::downconn_send_test_packet();
|
||||
timer.delay_us(20000); // wait packet has arrive at rx
|
||||
csr::cxp::downconn_phy_tx_stb_write(0);
|
||||
|
||||
// cxp_proto::downconn_debug_send_trig_ack();
|
||||
cxp_proto::downconn_debug_send_trig_ack();
|
||||
|
||||
cxp_proto::downconn_debug_send(&cxp_proto::Packet::CtrlRead {
|
||||
addr: 0x00,
|
||||
|
|
@ -58,10 +53,6 @@ pub fn loopback_testing(timer: &mut GlobalTimer, speed: CXP_SPEED) {
|
|||
csr::cxp::downconn_trig_clr_write(1);
|
||||
info!("after clr trig ack = {}", csr::cxp::downconn_trig_ack_read());
|
||||
|
||||
info!("decoder error = {}", csr::cxp::downconn_decoder_error_read());
|
||||
info!("test error = {}", csr::cxp::downconn_test_error_read());
|
||||
info!("packet type = {:#06X}", csr::cxp::downconn_packet_type_read());
|
||||
|
||||
// TODO: investigate how to make my packet appear
|
||||
// TODO: discard idle word
|
||||
|
||||
|
|
|
|||
|
|
@ -1,12 +1,10 @@
|
|||
use core::slice;
|
||||
|
||||
use core_io::{Error as IoError, Write};
|
||||
use crc::crc32;
|
||||
use embedded_hal::prelude::_embedded_hal_blocking_delay_DelayUs;
|
||||
use io::Cursor;
|
||||
use libboard_zynq::{println, timer::GlobalTimer};
|
||||
|
||||
use crate::{mem::mem::CXP_MEM, pl::csr};
|
||||
use crate::pl::csr;
|
||||
|
||||
const MAX_PACKET: usize = 128;
|
||||
const DATA_MAXSIZE: usize = /*max size*/MAX_PACKET - /*Tag*/4 - /*Op code & length*/4 - /*addr*/4 - /*CRC*/4 ;
|
||||
|
|
@ -139,6 +137,7 @@ fn send_test_packet() -> Result<(), Error> {
|
|||
unsafe {
|
||||
while csr::cxp::upconn_tx_busy_read() == 1 {}
|
||||
csr::cxp::upconn_tx_testmode_en_write(1);
|
||||
// timer.delay_us(2);
|
||||
csr::cxp::upconn_testseq_stb_write(1);
|
||||
while csr::cxp::upconn_testseq_busy_read() == 1 {}
|
||||
csr::cxp::upconn_tx_testmode_en_write(0);
|
||||
|
|
@ -196,7 +195,7 @@ pub fn print_packet(pak: &[u8]) {
|
|||
pub fn print_packetu32(pak: &[u32], k: &[u8]) {
|
||||
println!("pak = [");
|
||||
for i in 0..(pak.len()) {
|
||||
let data: [u8; 4] = pak[i].to_le_bytes();
|
||||
let data: [u8; 4] = pak[i].to_be_bytes();
|
||||
println!(
|
||||
"{:#03} {:#04X} {:#04X} {:#04X} {:#04X} | K {:04b},",
|
||||
i + 1,
|
||||
|
|
@ -237,45 +236,3 @@ pub fn downconn_debug_send_trig_ack() {
|
|||
csr::cxp::downconn_ack_write(1);
|
||||
}
|
||||
}
|
||||
|
||||
pub fn downconn_send_test_packet() {
|
||||
unsafe {
|
||||
csr::cxp::downconn_mux_sel_write(2);
|
||||
csr::cxp::downconn_testseq_stb_write(1);
|
||||
while csr::cxp::downconn_testseq_busy_read() == 1 {}
|
||||
}
|
||||
}
|
||||
|
||||
pub fn ram_writer_send(packet: &Packet) -> Result<(), Error> {
|
||||
unsafe {
|
||||
// TODO: put this in mem group
|
||||
while csr::cxp::transmitter_cxp_tx_read() == 1 {}
|
||||
let ptr = CXP_MEM[0].base as *mut u32;
|
||||
let mut writer = Cursor::new(slice::from_raw_parts_mut(ptr as *mut u8, 0x200 as usize));
|
||||
|
||||
packet.write_to(&mut writer)?;
|
||||
|
||||
csr::cxp::transmitter_cxp_tx_word_len_write(writer.position() as u8 / 4);
|
||||
csr::cxp::transmitter_cxp_tx_write(1);
|
||||
while csr::cxp::transmitter_cxp_tx_read() == 1 {}
|
||||
|
||||
// read the fifo
|
||||
const LEN: usize = 10;
|
||||
let mut pak_arr: [u32; LEN] = [0; LEN];
|
||||
let mut k_arr: [u8; LEN] = [0; LEN];
|
||||
let mut i: usize = 0;
|
||||
while csr::cxp::transmitter_debug_out_dout_valid_read() == 1 {
|
||||
pak_arr[i] = csr::cxp::transmitter_debug_out_dout_pak_read();
|
||||
k_arr[i] = csr::cxp::transmitter_debug_out_kout_pak_read();
|
||||
// println!("received {:#04X}", pak_arr[i]);
|
||||
csr::cxp::transmitter_debug_out_inc_write(1);
|
||||
i += 1;
|
||||
if i == LEN {
|
||||
break;
|
||||
}
|
||||
}
|
||||
print_packetu32(&pak_arr, &k_arr);
|
||||
}
|
||||
|
||||
Ok(())
|
||||
}
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@ use libasync::task;
|
|||
use libboard_artiq::drtio_eem;
|
||||
#[cfg(feature = "target_kasli_soc")]
|
||||
use libboard_artiq::io_expander;
|
||||
use libboard_artiq::{cxp_downconn, cxp_proto, cxp_upconn, identifier_read, logger, pl};
|
||||
use libboard_artiq::{identifier_read, logger, pl};
|
||||
use libboard_zynq::{gic, mpcore, timer::GlobalTimer};
|
||||
use libconfig::Config;
|
||||
use libcortex_a9::l2c::enable_l2_cache;
|
||||
|
|
@ -150,19 +150,16 @@ pub fn main_core0() {
|
|||
|
||||
task::spawn(ksupport::report_async_rtio_errors());
|
||||
|
||||
use libboard_artiq::{cxp_downconn, cxp_upconn};
|
||||
cxp_downconn::setup(&mut timer);
|
||||
cxp_downconn::loopback_testing(&mut timer, cxp_downconn::CXP_SPEED::CXP_1);
|
||||
// cxp_downconn::loopback_testing(&mut timer, cxp_downconn::CXP_SPEED::CXP_1);
|
||||
// cxp_downconn::loopback_testing(&mut timer, cxp_downconn::CXP_SPEED::CXP_2);
|
||||
// cxp_downconn::loopback_testing(&mut timer, cxp_downconn::CXP_SPEED::CXP_3);
|
||||
// cxp_downconn::loopback_testing(&mut timer, cxp_downconn::CXP_SPEED::CXP_5);
|
||||
// cxp_downconn::loopback_testing(&mut timer, cxp_downconn::CXP_SPEED::CXP_6);
|
||||
// cxp_downconn::loopback_testing(&mut timer, cxp_downconn::CXP_SPEED::CXP_10);
|
||||
// cxp_downconn::loopback_testing(&mut timer, cxp_downconn::CXP_SPEED::CXP_12);
|
||||
// loop {
|
||||
// use embedded_hal::prelude::_embedded_hal_blocking_delay_DelayUs;
|
||||
// cxp_upconn::tx_test(&mut timer);
|
||||
// timer.delay_us(5_000_000);
|
||||
// }
|
||||
cxp_upconn::tx_test(&mut timer);
|
||||
|
||||
comms::main(timer, cfg);
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue