cxp upconn: refactor idle into its submodule

flake.nix

@@ -341,6 +341,7 @@
       {
         inherit fastnumbers artiq-netboot ramda migen-axi binutils-arm;
       } //
+      (board-package-set { target = "zc706"; variant = "cxp_fmc"; }) //
       (board-package-set { target = "zc706"; variant = "nist_clock"; }) //
       (board-package-set { target = "zc706"; variant = "nist_clock_master"; }) //
       (board-package-set { target = "zc706"; variant = "nist_clock_master_100mhz"; }) //

src/gateware/cxp.py

@@ -0,0 +1,118 @@
+from migen import *
+
+from misoc.interconnect.csr import *
+
+from artiq.gateware.drtio.core import TransceiverInterface, ChannelInterface
+
+from cxp_downconn import CXP_DownConn
+
+class CXP(Module, AutoCSR):
+    def __init__(self, refclk, pads, sys_clk_freq, debug_sma):
+        self.nchannels = nchannels = len(pads)
+        self.rx_start_init = CSRStorage()
+        self.rx_restart = CSRStatus()
+        self.rx_bypass_clk_alignment = CSRStorage()
+
+        self.tx_start_init = CSRStorage()
+        self.tx_restart = CSRStorage()
+
+        self.loopback_mode = CSRStorage(3)
+
+        self.txinit_phaligndone = CSRStatus()
+        self.rx_ready = CSRStatus()
+
+        self.data_0 = CSRStorage(8)
+        self.data_1 = CSRStorage(8)
+        self.control_bit_0 = CSRStorage()
+        self.control_bit_1 = CSRStorage()
+        self.encoded_0 = CSRStatus(10)
+        self.encoded_1 = CSRStatus(10)
+
+        self.rxdata_0 = CSRStatus(10)
+        self.rxdata_1 = CSRStatus(10)
+        self.decoded_data_0 = CSRStatus(8)
+        self.decoded_data_1 = CSRStatus(8)
+        self.decoded_k_0 = CSRStatus()
+        self.decoded_k_1 = CSRStatus()
+
+        # # #
+
+        # single CXP 
+        self.submodules.gtx = gtx = CXP_DownConn(refclk, pads, sys_clk_freq, tx_mode="single", rx_mode="single")
+        
+        # ! loopback for debugging
+        self.sync += gtx.loopback_mode.eq(self.loopback_mode.storage) 
+
+        # ! debug sma
+        self.specials += [
+            Instance("OBUF", i_I=gtx.rxoutclk, o_O=debug_sma.p_tx),
+            Instance("OBUF", i_I=gtx.cd_cxp_gtx_tx.clk, o_O=debug_sma.n_rx)
+        ]
+
+        self.comb += [
+            self.txinit_phaligndone.status.eq(self.gtx.tx_init.Xxphaligndone),
+            self.rx_ready.status.eq(self.gtx.rx_ready),
+        ]
+
+        self.sync.cxp_gtx_tx += [
+            self.gtx.encoder.d[0].eq(self.data_0.storage),
+            self.gtx.encoder.k[0].eq(self.control_bit_0.storage),
+            self.encoded_0.status.eq(self.gtx.encoder.output[0]),
+
+            self.gtx.encoder.d[1].eq(self.data_1.storage),
+            self.gtx.encoder.k[1].eq(self.control_bit_1.storage),
+            self.encoded_1.status.eq(self.gtx.encoder.output[1]),
+        ]
+        self.sync.cxp_gtx_rx += [
+            self.rxdata_0.status.eq(self.gtx.decoders[0].input),
+            self.decoded_data_0.status.eq(self.gtx.decoders[0].d),
+            self.decoded_k_0.status.eq(self.gtx.decoders[0].k),
+
+            self.rxdata_1.status.eq(self.gtx.decoders[1].input),
+            self.decoded_data_1.status.eq(self.gtx.decoders[1].d),
+            self.decoded_k_1.status.eq(self.gtx.decoders[1].k),
+        ]
+
+        # TODO: rip encoder & rx clockalignment out of CXP_GTX 
+
+        # TODO: use expose encoder & decoder from CXP
+        # encoder.k = 1 if sending control bit, different calculation
+        # encoder.d = data 8 bit 
+
+
+
+        channel_interface = ChannelInterface(gtx.encoder, gtx.decoders)
+        self.comb += channel_interface.rx_ready.eq(gtx.rx_ready)
+        channel_interfaces = []
+        channel_interfaces.append(channel_interface)
+
+        # TransceiverInterface, just adding cxp_rx_<num>
+        self.stable_clkin = CSRStorage()
+        self.txenable = CSRStorage(len(channel_interfaces))
+        for i in range(len(channel_interfaces)):
+            name = "cxp_gtx_rx" + str(i)
+            setattr(self.clock_domains, "cd_"+name, ClockDomain(name=name))
+        self.channels = channel_interfaces
+
+
+        # TODO: add tx_phase_alignment for multi CXP
+        # The TX phase alignment will fail with a wrong TXUSRCLK frequency
+
+
+        self.comb += [
+            gtx.rx_init.clk_path_ready.eq(self.rx_start_init.storage),
+
+            gtx.tx_init.clk_path_ready.eq(self.tx_start_init.storage),
+            gtx.txenable.eq(self.txenable.storage[0]),
+            gtx.tx_restart.eq(self.tx_restart.storage),
+        ]
+
+        # TODO: Connect multilane cxp_tx 
+
+        # TODO: Connect slave i's `cxp_gtx_rx` clock to `cxp_gtx_rxi` clock
+        self.comb += [
+            getattr(self, "cd_cxp_gtx_rx" + str(0)).clk.eq(self.gtx.cd_cxp_gtx_rx.clk),
+            getattr(self, "cd_cxp_gtx_rx" + str(0)).rst.eq(self.gtx.cd_cxp_gtx_rx.rst)
+        ]
+
+        # TODO: add low speed SERDES

src/gateware/cxp_4r_fmc.py

@@ -0,0 +1,87 @@
+from migen.build.generic_platform import *
+
+fmc_adapter_io = [
+
+    # CoaXPress high speed link
+    ("CXP_HS", 0,
+        Subsignal("txp", Pins("HPC:DP0_C2M_P")),
+        Subsignal("txn", Pins("HPC:DP0_C2M_N")),
+        Subsignal("rxp", Pins("HPC:DP0_M2C_P")),
+        Subsignal("rxn", Pins("HPC:DP0_M2C_N")),
+    ),
+    ("CXP_HS", 1,
+        Subsignal("txp", Pins("HPC:DP1_C2M_P")),
+        Subsignal("txn", Pins("HPC:DP1_C2M_N")),
+        Subsignal("rxp", Pins("HPC:DP1_M2C_P")),
+        Subsignal("rxn", Pins("HPC:DP1_M2C_N")),
+    ),
+    ("CXP_HS", 2,
+        Subsignal("txp", Pins("HPC:DP2_C2M_P")),
+        Subsignal("txn", Pins("HPC:DP2_C2M_N")),
+        Subsignal("rxp", Pins("HPC:DP2_M2C_P")),
+        Subsignal("rxn", Pins("HPC:DP2_M2C_n")),
+    ),
+    ("CXP_HS", 3,
+        Subsignal("txp", Pins("HPC:DP3_C2M_P")),
+        Subsignal("txn", Pins("HPC:DP3_C2M_N")),
+        Subsignal("rxp", Pins("HPC:DP3_M2C_P")),
+        Subsignal("rxn", Pins("HPC:DP3_M2C_N")),
+    ),
+
+    # CoaXPress low speed link
+    ("CXP_LS", 0, Pins("HPC:LA00_CC_P"), IOStandard("LVCMOS25")),
+    ("CXP_LS", 1, Pins("HPC:LA01_CC_N"), IOStandard("LVCMOS25")),
+    ("CXP_LS", 2, Pins("HPC:LA01_CC_P"), IOStandard("LVCMOS25")),
+    ("CXP_LS", 3, Pins("HPC:LA02_N"), IOStandard("LVCMOS25")),
+
+    # CoaXPress green and red LED
+    ("CXP_LED", 0,
+        Subsignal("green", Pins("HPC:LA11_P"), IOStandard("LVCMOS25")),
+        Subsignal("red", Pins("HPC:LA11_N"), IOStandard("LVCMOS25")),
+    ),
+    ("CXP_LED", 1,
+        Subsignal("green", Pins("HPC:LA12_P"), IOStandard("LVCMOS25")),
+        Subsignal("red", Pins("HPC:LA12_N"), IOStandard("LVCMOS25")),
+    ),
+    ("CXP_LED", 2,
+        Subsignal("green", Pins("HPC:LA13_P"), IOStandard("LVCMOS25")),
+        Subsignal("red", Pins("HPC:LA13_N"), IOStandard("LVCMOS25")),
+    ),
+    ("CXP_LED", 3,
+        Subsignal("green", Pins("HPC:LA14_P"), IOStandard("LVCMOS25")),
+        Subsignal("red", Pins("HPC:LA14_N"), IOStandard("LVCMOS25")),
+    ),
+
+    # Power over CoaXPress 
+    ("PoCXP", 0,
+        Subsignal("enable", Pins("HPC:LA21_N"), IOStandard("LVCMOS25")),
+        Subsignal("alert", Pins("HPC:LA18_CC_P"), IOStandard("LVCMOS25")),
+    ),
+    ("PoCXP", 1,
+        Subsignal("enable", Pins("HPC:LA21_P"), IOStandard("LVCMOS25")),
+        Subsignal("alert", Pins("HPC:LA19_N"), IOStandard("LVCMOS25")),
+    ),
+    ("PoCXP", 2,
+        Subsignal("enable", Pins("HPC:LA22_N"), IOStandard("LVCMOS25")),
+        Subsignal("alert", Pins("HPC:LA19_P"), IOStandard("LVCMOS25")),
+    ),
+    ("PoCXP", 3,
+        Subsignal("enable", Pins("HPC:LA22_P"), IOStandard("LVCMOS25")),
+        Subsignal("alert", Pins("HPC:LA20_N"), IOStandard("LVCMOS25")),
+    ),
+
+    ("i2c_fmc", 0,
+        Subsignal("scl", Pins("HPC:IIC_SCL")),
+        Subsignal("sda", Pins("HPC:IIC_SDA")),
+        IOStandard("LVCMOS25")
+    ),
+
+    ("3V3", 0, Pins("HPC:PG_M2C")),
+    ("GND", 0, Pins("HPC:PRSNT_M2C_L HPC:CLK0_M2C_P")),
+    ("VADJ", 0, Pins("HPC:GBTCLK1_M2C_N CLK0_M2C_N")),
+
+    ("clk125_fmc", 0,
+        Subsignal("p", Pins("HPC:GBTCLK0_M2C_P")),
+        Subsignal("n", Pins("HPC:GBTCLK0_M2C_n")),
+    ),
+]

src/gateware/cxp_downconn.py

@@ -0,0 +1,427 @@
+from migen import *
+from migen.genlib.resetsync import AsyncResetSynchronizer
+from migen.genlib.cdc import MultiReg, PulseSynchronizer
+
+from misoc.cores.code_8b10b import Encoder, Decoder
+from misoc.interconnect.csr import *
+
+from artiq.gateware.drtio.core import TransceiverInterface, ChannelInterface
+from artiq.gateware.drtio.transceiver.gtx_7series_init import *
+
+from operator import add
+from math import ceil
+from functools import reduce
+
+# Changes the phase of the transceiver RX clock to align the comma to
+# the LSBs of RXDATA, fixing the latency.
+#
+# This is implemented by repeatedly resetting the transceiver until it
+# gives out the correct phase. Each reset gives a random phase.
+#
+# If Xilinx had designed the GTX transceiver correctly, RXSLIDE_MODE=PMA
+# would achieve this faster and in a cleaner way. But:
+#  * the phase jumps are of 2 UI at every second RXSLIDE pulse, instead
+#    of 1 UI at every pulse. It is unclear what the latency becomes.
+#  * RXSLIDE_MODE=PMA cannot be used with the RX buffer bypassed.
+# Those design flaws make RXSLIDE_MODE=PMA yet another broken and useless
+# transceiver "feature".
+#
+# Warning: Xilinx transceivers are LSB first, and comma needs to be flipped
+# compared to the usual 8b10b binary representation.
+class CXP_BruteforceClockAligner(Module):
+    def __init__(self, comma, tx_clk_freq, check_period=6e-3):
+        self.rxdata = Signal(20)
+        self.restart = Signal()
+
+        self.ready = Signal()
+
+        check_max_val = ceil(check_period*tx_clk_freq)
+        check_counter = Signal(max=check_max_val+1)
+        check = Signal()
+        reset_check_counter = Signal()
+        self.sync += [
+            check.eq(0),
+            If(reset_check_counter,
+                check_counter.eq(check_max_val)
+            ).Else(
+                If(check_counter == 0,
+                    check.eq(1),
+                    check_counter.eq(check_max_val)
+                ).Else(
+                    check_counter.eq(check_counter-1)
+                )
+            )
+        ]
+
+        checks_reset = PulseSynchronizer("sys", "cxp_gtx_rx")
+        self.submodules += checks_reset
+
+        comma_n = ~comma & 0b1111111111
+        comma_seen_rxclk = Signal()
+        comma_seen = Signal()
+        comma_seen_rxclk.attr.add("no_retiming")
+        self.specials += MultiReg(comma_seen_rxclk, comma_seen)
+        self.sync.cxp_gtx_rx += \
+            If(checks_reset.o,
+                comma_seen_rxclk.eq(0)
+            ).Elif((self.rxdata[:10] == comma) | (self.rxdata[:10] == comma_n),
+                comma_seen_rxclk.eq(1)
+            )
+
+        error_seen_rxclk = Signal()
+        error_seen = Signal()
+        error_seen_rxclk.attr.add("no_retiming")
+        self.specials += MultiReg(error_seen_rxclk, error_seen)
+        rx1cnt = Signal(max=11)
+        self.sync.cxp_gtx_rx += [
+            rx1cnt.eq(reduce(add, [self.rxdata[i] for i in range(10)])),
+            If(checks_reset.o,
+                error_seen_rxclk.eq(0)
+            ).Elif((rx1cnt != 4) & (rx1cnt != 5) & (rx1cnt != 6),
+                error_seen_rxclk.eq(1)
+            )
+        ]
+
+        fsm = FSM(reset_state="WAIT_COMMA")
+        self.submodules += fsm
+
+        fsm.act("WAIT_COMMA",
+            If(check,
+                # Errors are still OK at this stage, as the transceiver
+                # has just been reset and may output garbage data.
+                If(comma_seen,
+                    NextState("WAIT_NOERROR")
+                ).Else(
+                    self.restart.eq(1)
+                ),
+                checks_reset.i.eq(1)
+            )
+        )
+        fsm.act("WAIT_NOERROR",
+            If(check,
+                If(comma_seen & ~error_seen,
+                    NextState("READY")
+                ).Else(
+                    self.restart.eq(1),
+                    NextState("WAIT_COMMA")
+                ),
+                checks_reset.i.eq(1)
+            )
+        )
+        fsm.act("READY",
+            reset_check_counter.eq(1),
+            self.ready.eq(1),
+            If(error_seen,
+                checks_reset.i.eq(1),
+                self.restart.eq(1),
+                NextState("WAIT_COMMA")
+            )
+        )
+
+
+
+class CXP_DownConn(Module):
+    # Settings:
+    # * GTX reference clock @ 125MHz
+    # * GTX data width = 20
+    # * GTX PLL frequency @ 3.125GHz
+    # * GTX line rate (TX & RX) @ 3.125Gb/s
+    # * GTX TX/RX USRCLK @ PLL/datawidth = 156MHz
+    def __init__(self, refclk, pads, sys_clk_freq, tx_mode="single", rx_mode="single"):
+        assert tx_mode in ["single", "master", "slave"]
+        assert rx_mode in ["single", "master", "slave"]
+
+        cpll_div = 4
+        pll_div = int(40/cpll_div)
+
+        self.rx_restart = Signal()
+        self.rx_bypass_clk_alignment = Signal()
+        self.tx_restart = Signal()
+        self.loopback_mode = Signal(3)
+
+        self.txenable = Signal()
+        self.submodules.encoder = ClockDomainsRenamer("cxp_gtx_tx")(Encoder(2, True))
+        self.submodules.decoders = [ClockDomainsRenamer("cxp_gtx_rx")(
+            (Decoder(True))) for _ in range(2)]
+        self.rx_ready = Signal()
+
+        # transceiver direct clock outputs
+        # useful to specify clock constraints in a way palatable to Vivado
+        self.txoutclk = Signal()
+        self.rxoutclk = Signal()
+
+        # # #
+
+        cpllreset = Signal()
+        cplllock = Signal()
+        # TX generates cxp_tx clock, init must be in system domain
+        self.submodules.tx_init = tx_init = GTXInit(sys_clk_freq, False, mode=tx_mode)
+        # RX receives restart commands from RTIO domain
+        self.submodules.rx_init = rx_init = GTXInit(sys_clk_freq, True, mode=rx_mode)
+        self.comb += [
+            cpllreset.eq(tx_init.cpllreset),
+            tx_init.cplllock.eq(cplllock),
+            rx_init.cplllock.eq(cplllock)
+        ]
+
+        txdata = Signal(20)
+        rxdata = Signal(20)
+        # Note: the following parameters were set after consulting AR45360
+        self.specials += \
+            Instance("GTXE2_CHANNEL",
+                # PMA Attributes
+                p_PMA_RSV=0x00018480,
+                p_PMA_RSV2=0x2050,              # PMA_RSV2[5] = 0: Eye scan feature disabled
+                p_PMA_RSV3=0,
+                p_PMA_RSV4=1,                   # PMA_RSV[4],RX_CM_TRIM[2:0] = 0b1010: Common mode 800mV
+                p_RX_BIAS_CFG=0b000000000100,
+                p_RX_OS_CFG=0b0000010000000,
+                p_RX_CLK25_DIV=5,
+                p_TX_CLK25_DIV=5,
+
+                # Power-Down Attributes
+                p_PD_TRANS_TIME_FROM_P2=0x3c,
+                p_PD_TRANS_TIME_NONE_P2=0x3c,
+                p_PD_TRANS_TIME_TO_P2=0x64,
+
+                # CPLL
+                p_CPLL_CFG=0xBC07DC,
+                p_CPLL_FBDIV=cpll_div,
+                p_CPLL_FBDIV_45=5,
+                p_CPLL_REFCLK_DIV=1,
+                p_RXOUT_DIV=2,
+                p_TXOUT_DIV=2,
+                p_CPLL_INIT_CFG=0x00001E,
+                p_CPLL_LOCK_CFG=0x01E8,
+                i_CPLLRESET=cpllreset,
+                i_CPLLPD=cpllreset,
+                o_CPLLLOCK=cplllock,
+                i_CPLLLOCKEN=1,
+                i_CPLLREFCLKSEL=0b001,
+                i_TSTIN=2**20-1,
+                i_GTREFCLK0=refclk,
+
+                # TX clock
+                p_TXBUF_EN="FALSE",
+                p_TX_XCLK_SEL="TXUSR",
+                o_TXOUTCLK=self.txoutclk,
+                i_TXSYSCLKSEL=0b00,
+                i_TXOUTCLKSEL=0b11,
+
+                # TX Startup/Reset
+                i_TXPHDLYRESET=0,
+                i_TXDLYBYPASS=0,
+                i_TXPHALIGNEN=1 if tx_mode != "single" else 0,
+                i_GTTXRESET=tx_init.gtXxreset,
+                o_TXRESETDONE=tx_init.Xxresetdone,
+                i_TXDLYSRESET=tx_init.Xxdlysreset,
+                o_TXDLYSRESETDONE=tx_init.Xxdlysresetdone,
+                i_TXPHINIT=tx_init.txphinit if tx_mode != "single" else 0,
+                o_TXPHINITDONE=tx_init.txphinitdone if tx_mode != "single" else Signal(),
+                i_TXPHALIGN=tx_init.Xxphalign if tx_mode != "single" else 0,
+                i_TXDLYEN=tx_init.Xxdlyen if tx_mode != "single" else 0,
+                o_TXPHALIGNDONE=tx_init.Xxphaligndone,
+                i_TXUSERRDY=tx_init.Xxuserrdy,
+                p_TXPMARESET_TIME=1,
+                p_TXPCSRESET_TIME=1,
+                i_TXINHIBIT=~self.txenable,
+
+                # TX data
+                p_TX_DATA_WIDTH=20,
+                p_TX_INT_DATAWIDTH=0,
+                i_TXCHARDISPMODE=Cat(txdata[9], txdata[19]),
+                i_TXCHARDISPVAL=Cat(txdata[8], txdata[18]),
+                i_TXDATA=Cat(txdata[:8], txdata[10:18]),
+                i_TXUSRCLK=ClockSignal("cxp_gtx_tx"),
+                i_TXUSRCLK2=ClockSignal("cxp_gtx_tx"),
+
+                # TX electrical
+                i_TXBUFDIFFCTRL=0b100,
+                i_TXDIFFCTRL=0b1000,
+
+                # RX Startup/Reset
+                i_RXPHDLYRESET=0,
+                i_RXDLYBYPASS=0,
+                i_RXPHALIGNEN=1 if rx_mode != "single" else 0,
+                i_GTRXRESET=rx_init.gtXxreset,
+                o_RXRESETDONE=rx_init.Xxresetdone,
+                i_RXDLYSRESET=rx_init.Xxdlysreset,
+                o_RXDLYSRESETDONE=rx_init.Xxdlysresetdone,
+                i_RXPHALIGN=rx_init.Xxphalign if rx_mode != "single" else 0,
+                i_RXDLYEN=rx_init.Xxdlyen if rx_mode != "single" else 0,
+                o_RXPHALIGNDONE=rx_init.Xxphaligndone,
+                i_RXUSERRDY=rx_init.Xxuserrdy,
+                p_RXPMARESET_TIME=1,
+                p_RXPCSRESET_TIME=1,
+
+                # RX AFE
+                p_RX_DFE_XYD_CFG=0,
+                p_RX_CM_SEL=0b11,               # RX_CM_SEL = 0b11: Common mode is programmable
+                p_RX_CM_TRIM=0b010,             # PMA_RSV[4],RX_CM_TRIM[2:0] = 0b1010: Common mode 800mV
+                i_RXDFEXYDEN=1,
+                i_RXDFEXYDHOLD=0,
+                i_RXDFEXYDOVRDEN=0,
+                i_RXLPMEN=0,                    # RXLPMEN = 0: DFE mode is enabled
+                p_RX_DFE_GAIN_CFG=0x0207EA,
+                p_RX_DFE_VP_CFG=0b00011111100000011,
+                p_RX_DFE_UT_CFG=0b10001000000000000,
+                p_RX_DFE_KL_CFG=0b0000011111110,
+                p_RX_DFE_KL_CFG2=0x3788140A,
+                p_RX_DFE_H2_CFG=0b000110000000,
+                p_RX_DFE_H3_CFG=0b000110000000,
+                p_RX_DFE_H4_CFG=0b00011100000,
+                p_RX_DFE_H5_CFG=0b00011100000,
+                p_RX_DFE_LPM_CFG=0x0904,        # RX_DFE_LPM_CFG = 0x0904: linerate <= 6.6Gb/s
+                                                #                = 0x0104: linerate > 6.6Gb/s
+
+                # RX clock
+                i_RXDDIEN=1,
+                i_RXSYSCLKSEL=0b00,
+                i_RXOUTCLKSEL=0b010,
+                o_RXOUTCLK=self.rxoutclk,
+                i_RXUSRCLK=ClockSignal("cxp_gtx_rx"),
+                i_RXUSRCLK2=ClockSignal("cxp_gtx_rx"),
+
+                # RX Clock Correction Attributes
+                p_CLK_CORRECT_USE="FALSE",
+                p_CLK_COR_SEQ_1_1=0b0100000000,
+                p_CLK_COR_SEQ_2_1=0b0100000000,
+                p_CLK_COR_SEQ_1_ENABLE=0b1111,
+                p_CLK_COR_SEQ_2_ENABLE=0b1111,
+
+                # RX data
+                p_RX_DATA_WIDTH=20,
+                p_RX_INT_DATAWIDTH=0,
+                o_RXDISPERR=Cat(rxdata[9], rxdata[19]),
+                o_RXCHARISK=Cat(rxdata[8], rxdata[18]),
+                o_RXDATA=Cat(rxdata[:8], rxdata[10:18]),
+
+                # RX Byte and Word Alignment Attributes
+                p_ALIGN_COMMA_DOUBLE="FALSE",
+                p_ALIGN_COMMA_ENABLE=0b1111111111,
+                p_ALIGN_COMMA_WORD=1,
+                p_ALIGN_MCOMMA_DET="TRUE",
+                p_ALIGN_MCOMMA_VALUE=0b1010000011,
+                p_ALIGN_PCOMMA_DET="TRUE",
+                p_ALIGN_PCOMMA_VALUE=0b0101111100,
+                p_SHOW_REALIGN_COMMA="FALSE",
+                p_RXSLIDE_AUTO_WAIT=7,
+                p_RXSLIDE_MODE="PCS",
+                p_RX_SIG_VALID_DLY=10,
+
+                # RX 8B/10B Decoder Attributes
+                p_RX_DISPERR_SEQ_MATCH="FALSE",
+                p_DEC_MCOMMA_DETECT="TRUE",
+                p_DEC_PCOMMA_DETECT="TRUE",
+                p_DEC_VALID_COMMA_ONLY="FALSE",
+
+                # RX Buffer Attributes
+                p_RXBUF_ADDR_MODE="FAST",
+                p_RXBUF_EIDLE_HI_CNT=0b1000,
+                p_RXBUF_EIDLE_LO_CNT=0b0000,
+                p_RXBUF_EN="FALSE",
+                p_RX_BUFFER_CFG=0b000000,
+                p_RXBUF_RESET_ON_CB_CHANGE="TRUE",
+                p_RXBUF_RESET_ON_COMMAALIGN="FALSE",
+                p_RXBUF_RESET_ON_EIDLE="FALSE",     # RXBUF_RESET_ON_EIDLE = FALSE: OOB is disabled
+                p_RXBUF_RESET_ON_RATE_CHANGE="TRUE",
+                p_RXBUFRESET_TIME=0b00001,
+                p_RXBUF_THRESH_OVFLW=61,
+                p_RXBUF_THRESH_OVRD="FALSE",
+                p_RXBUF_THRESH_UNDFLW=4,
+                p_RXDLY_CFG=0x001F,
+                p_RXDLY_LCFG=0x030,
+                p_RXDLY_TAP_CFG=0x0000,
+                p_RXPH_CFG=0xC00002,
+                p_RXPHDLY_CFG=0x084020,
+                p_RXPH_MONITOR_SEL=0b00000,
+                p_RX_XCLK_SEL="RXUSR",
+                p_RX_DDI_SEL=0b000000,
+                p_RX_DEFER_RESET_BUF_EN="TRUE",
+
+                # CDR Attributes
+                p_RXCDR_CFG=0x03_0000_23FF_1040_0020,   # DFE @ <= 6.6Gb/s, 8B/10B encoded data, CDR setting < +/- 200ppm
+                                                    # (See UG476 (v1.12.1), p.205)
+                p_RXCDR_FR_RESET_ON_EIDLE=0b0,
+                p_RXCDR_HOLD_DURING_EIDLE=0b0,
+                p_RXCDR_PH_RESET_ON_EIDLE=0b0,
+                p_RXCDR_LOCK_CFG=0b010101,
+
+                # Pads
+                i_GTXRXP=pads.rxp,
+                i_GTXRXN=pads.rxn,
+                o_GTXTXP=pads.txp,
+                o_GTXTXN=pads.txn,
+
+                # ! loopback for debugging
+                i_LOOPBACK = self.loopback_mode,
+                p_TX_LOOPBACK_DRIVE_HIZ = "FALSE",
+                p_RXPRBS_ERR_LOOPBACK = 0b0,
+
+                # Other parameters
+                p_PCS_RSVD_ATTR=(
+                    (tx_mode != "single") << 1 |    # PCS_RSVD_ATTR[1] = 0: TX Single Lane Auto Mode
+                                                    #                  = 1: TX Manual Mode
+                    (rx_mode != "single") << 2 |    #              [2] = 0: RX Single Lane Auto Mode
+                                                    #                  = 1: RX Manual Mode
+                    0 << 8                          #              [8] = 0: OOB is disabled
+                ),
+                i_RXELECIDLEMODE=0b11,              # RXELECIDLEMODE = 0b11: OOB is disabled
+                p_RX_DFE_LPM_HOLD_DURING_EIDLE=0b0,
+                p_ES_EYE_SCAN_EN="TRUE",            # Must be TRUE for GTX
+            )
+
+
+        # TX clocking
+        # A PLL is used to generate the correct frequency for TXUSRCLK (UG476 Equation 3-1)
+        self.clock_domains.cd_cxp_gtx_tx = ClockDomain()
+        txpll_fb_clk = Signal()
+        txpll_reset = Signal()
+        txpll_locked = Signal()
+        txoutclk_buf = Signal()
+        txpll_clkout = Signal()
+        self.specials += [
+            Instance("PLLE2_ADV",
+                p_BANDWIDTH="HIGH",
+                o_LOCKED=txpll_locked,
+                i_RST=txpll_reset,
+                
+                p_CLKIN1_PERIOD=1e9/sys_clk_freq, # ns
+                i_CLKIN1=txoutclk_buf,
+
+                # VCO @ 1.25GHz 
+                p_CLKFBOUT_MULT=10, p_DIVCLK_DIVIDE=1,
+                i_CLKFBIN=txpll_fb_clk, o_CLKFBOUT=txpll_fb_clk, 
+
+                # 156.25MHz
+                p_CLKOUT0_DIVIDE=pll_div, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=txpll_clkout,
+
+                # TODO: DRP for line rate change
+            ),
+            Instance("BUFG", i_I=self.txoutclk, o_O=txoutclk_buf),
+            Instance("BUFG", i_I=txpll_clkout, o_O=self.cd_cxp_gtx_tx.clk),
+            AsyncResetSynchronizer(self.cd_cxp_gtx_tx, ~txpll_locked & ~tx_init.done)
+        ]
+
+        # RX clocking
+        # the CDR matches the required frequency for RXUSRCLK, no need for PLL 
+        self.clock_domains.cd_cxp_gtx_rx = ClockDomain()
+        self.specials += [
+            Instance("BUFG", i_I=self.rxoutclk, o_O=self.cd_cxp_gtx_rx.clk),
+            AsyncResetSynchronizer(self.cd_cxp_gtx_rx, ~rx_init.done)
+        ]
+
+        self.comb += [
+            txdata.eq(Cat(self.encoder.output[0], self.encoder.output[1])),
+            self.decoders[0].input.eq(rxdata[:10]),
+            self.decoders[1].input.eq(rxdata[10:])
+        ]
+
+        clock_aligner = CXP_BruteforceClockAligner(0b0101111100, sys_clk_freq, check_period=1e-3)
+        self.submodules += clock_aligner
+        self.comb += [
+            clock_aligner.rxdata.eq(rxdata),
+            rx_init.restart.eq(clock_aligner.restart),
+            self.rx_ready.eq(clock_aligner.ready),
+            tx_init.restart.eq(self.tx_restart)
+        ]

src/gateware/cxp_upconn.py

@@ -0,0 +1,291 @@
+from migen import *
+from migen.genlib.resetsync import AsyncResetSynchronizer
+from migen.genlib.coding import PriorityEncoder
+
+from misoc.cores.code_8b10b import SingleEncoder
+from misoc.interconnect import stream
+from misoc.interconnect.csr import *
+
+
+class CXP_UpConn(Module, AutoCSR):
+    def __init__(self, pads, sys_clk_freq, pmod, nfifos=3, fifo_depth=32):
+        self.clock_domains.cd_cxp_upconn = ClockDomain()
+        self.clk_reset = CSRStorage(reset=1)
+        self.bitrate2x_enable = CSRStorage()
+        self.tx_enable = CSRStorage()
+
+        # # #
+
+        pll_locked = Signal()
+        pll_fb_clk = Signal()
+        pll_cxpclk = Signal()
+        pll_cxpclk2x = Signal()
+
+        self.specials += [
+            Instance("PLLE2_ADV",
+                p_BANDWIDTH="HIGH",
+                o_LOCKED=pll_locked,
+                i_RST=ResetSignal("sys"),
+                
+                p_CLKIN1_PERIOD=1e9/sys_clk_freq, # ns
+                i_CLKIN1=ClockSignal("sys"),
+
+                # VCO @ 1.25GHz 
+                p_CLKFBOUT_MULT=1.25e9/sys_clk_freq, p_DIVCLK_DIVIDE=1,
+                i_CLKFBIN=pll_fb_clk, o_CLKFBOUT=pll_fb_clk, 
+
+                # 20.83MHz (48ns)
+                p_CLKOUT0_DIVIDE=60, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_cxpclk,
+
+                # 41.66MHz (24ns) for downconnection over 6.25Gpbs
+                p_CLKOUT1_DIVIDE=30, p_CLKOUT1_PHASE=0.0, o_CLKOUT1=pll_cxpclk2x,
+            ),
+            Instance("BUFGMUX",
+                i_I0=pll_cxpclk,
+                i_I1=pll_cxpclk2x,
+                i_S=self.bitrate2x_enable.storage,
+                o_O=self.cd_cxp_upconn.clk
+            ),
+            AsyncResetSynchronizer(self.cd_cxp_upconn, ~pll_locked | self.clk_reset.storage)
+        ]
+
+        self.submodules.fsm = ClockDomainsRenamer("cxp_upconn")(FSM(reset_state="WAIT_TX_ENABLE"))
+        self.submodules.tx_fifos = TxFIFOs(nfifos, fifo_depth)
+        self.submodules.tx_idle = TxIdle()
+
+        o = Signal()
+        tx_en = Signal()
+        tx_bitcount = Signal(max=10)
+        tx_wordcount = Signal()
+        tx_reg = Signal(10)
+
+        disp = Signal()
+        tx_wordcount = Signal(max=4)
+        priority = Signal(max=nfifos)
+        idling = Signal()
+
+        # startup sequence
+        self.fsm.act("WAIT_TX_ENABLE",
+            NextValue(self.tx_idle.disp_in, 0),
+            NextValue(self.tx_idle.word_idx, 0),
+
+            If(self.tx_enable.storage,
+                NextValue(tx_wordcount, 0),
+                NextValue(tx_bitcount, 0),
+                NextState("LOAD_CHAR")
+            )
+        )
+
+        self.fsm.act("LOAD_CHAR",
+            NextValue(idling, 1),
+            NextValue(self.tx_idle.source_ack, 1),
+            NextValue(tx_reg, self.tx_idle.source_data),
+            NextValue(disp, self.tx_idle.disp_out),
+            NextState("START_TX")
+        )
+
+        self.fsm.act("START_TX",
+            tx_en.eq(1),
+            If((~self.tx_enable.storage) & (tx_wordcount == 3),
+                NextState("WAIT_TX_ENABLE")
+            )
+        )
+
+
+        # CXP 2.1 section 9.2.4 
+        # Higher priority packet can be inserted into a lower priority packet during transmission
+        # Priority lv 0 can be inserted in char boundary of the packet 
+        # Priority lv 1-2 need to be inserted in word boundary of the packet
+        self.sync.cxp_upconn += [
+            self.tx_fifos.disp_in.eq(disp),
+            self.tx_idle.disp_in.eq(disp),
+
+            If(tx_en,
+                o.eq(tx_reg[0]),
+                tx_reg.eq(Cat(tx_reg[1:], 0)),
+                tx_bitcount.eq(tx_bitcount + 1),   
+
+
+                # char boundary
+                If(tx_bitcount == 9,
+                    tx_bitcount.eq(0),
+                    If((~self.tx_fifos.pe.n) & (self.tx_fifos.pe.o == 0),
+                        # trigger packet can interrupt at char level
+                        tx_reg.eq(self.tx_fifos.source_data[0]),
+                        self.tx_fifos.source_ack[0].eq(1),
+                        disp.eq(self.tx_fifos.disp_out[0]),
+                    ).Else(
+                        # priority zero doesn't contribute to word count
+                        If(tx_wordcount != 3,
+                            tx_wordcount.eq(tx_wordcount + 1),
+                        ).Else(
+                            tx_wordcount.eq(0),
+                        ),
+
+                        # new word boundary
+                        If(tx_wordcount == 3,
+                            If(~self.tx_fifos.pe.n,
+                                idling.eq(0),
+                                priority.eq(self.tx_fifos.pe.o),
+
+                                self.tx_fifos.source_ack[self.tx_fifos.pe.o].eq(1),
+                                tx_reg.eq(self.tx_fifos.source_data[self.tx_fifos.pe.o]),
+                                disp.eq(self.tx_fifos.disp_out[self.tx_fifos.pe.o]),
+                            ).Else(
+                                idling.eq(1),
+
+                                self.tx_idle.source_ack.eq(1),
+                                tx_reg.eq(self.tx_idle.source_data),    
+                                disp.eq(self.tx_idle.disp_out),
+                            )
+                        ).Else(
+                            If(~idling,
+                                self.tx_fifos.source_ack[priority].eq(1),
+                                tx_reg.eq(self.tx_fifos.source_data[priority]),
+                                disp.eq(self.tx_fifos.disp_out[priority]),
+                            ).Else(
+                                self.tx_idle.source_ack.eq(1),
+                                tx_reg.eq(self.tx_idle.source_data),    
+                                disp.eq(self.tx_idle.disp_out),
+                            )
+                        ),       
+                    )
+                )
+            ).Else(
+                o.eq(0)
+            )
+        ]
+        # DEBUG: remove pads
+        self.encoded_data = CSRStatus(10)
+        self.sync.cxp_upconn +=[
+            If(tx_bitcount == 0,
+                self.encoded_data.status.eq(tx_reg),
+            )
+        ]
+       
+        ninth_bit = Signal()
+        word_bound = Signal()
+
+        p0 = Signal()
+        p3 = Signal()
+        self.comb += [
+           ninth_bit.eq(tx_bitcount == 9),
+           word_bound.eq(tx_wordcount == 3),
+           p0.eq(self.tx_idle.word_idx == 0),
+           p3.eq(self.tx_idle.word_idx == 3),
+        ] 
+        self.specials += [
+            # debug sma
+            Instance("OBUF", i_I=o, o_O=pads.p_tx),
+            Instance("OBUF", i_I=self.cd_cxp_upconn.clk, o_O=pads.n_rx),
+
+            # pmod 0-7 pin
+            Instance("OBUF", i_I=o, o_O=pmod[0]),
+            Instance("OBUF", i_I=self.cd_cxp_upconn.clk, o_O=pmod[1]),
+            Instance("OBUF", i_I=~self.tx_fifos.pe.n, o_O=pmod[2]),
+            Instance("OBUF", i_I=ninth_bit, o_O=pmod[3]),
+            Instance("OBUF", i_I=word_bound, o_O=pmod[4]),
+            Instance("OBUF", i_I=idling, o_O=pmod[5]),
+            # Instance("OBUF", i_I=self.tx_fifos.source_ack[0], o_O=pmod[6]),
+            # Instance("OBUF", i_I=self.tx_fifos.source_ack[2], o_O=pmod[6]),
+            # Instance("OBUF", i_I=self.tx_fifos.source_ack[1], o_O=pmod[7]),
+            Instance("OBUF", i_I=p0, o_O=pmod[6]),
+            Instance("OBUF", i_I=p3, o_O=pmod[7]),
+        ]
+        self.symbol0 = CSR(9)
+        self.symbol1 = CSR(9)
+        self.symbol2 = CSR(9)
+
+        self.sync += [
+            self.tx_fifos.sink_stb[0].eq(self.symbol0.re),
+            self.tx_fifos.sink_data[0].eq(self.symbol0.r),
+            self.tx_fifos.sink_stb[1].eq(self.symbol1.re),
+            self.tx_fifos.sink_data[1].eq(self.symbol1.r),
+            self.tx_fifos.sink_stb[2].eq(self.symbol2.re),
+            self.tx_fifos.sink_data[2].eq(self.symbol2.r),
+        ]
+
+class TxFIFOs(Module):
+    def __init__(self, nfifos, fifo_depth):
+        self.disp_in = Signal()
+        self.disp_out = Array(Signal() for _ in range(nfifos))
+        
+        self.sink_stb = Signal(nfifos)
+        self.sink_ack = Signal(nfifos) 
+        self.sink_data = [Signal(9) for _ in range(nfifos)]
+        
+        self.source_ack = Array(Signal() for _ in range(nfifos))
+        self.source_data = Array(Signal(10) for _ in range(nfifos))
+
+        # # #
+
+        source_stb = Signal(nfifos)
+
+        for i in range(nfifos):
+            cdr = ClockDomainsRenamer({"write": "sys", "read": "cxp_upconn"})
+            fifo = cdr(stream.AsyncFIFO([("data", 9)], fifo_depth))
+            encoder = ClockDomainsRenamer("cxp_upconn")(SingleEncoder(True))
+            setattr(self.submodules, "tx_fifo" + str(i), fifo)
+            setattr(self.submodules, "tx_encoder" + str(i), encoder)
+            self.sync += [
+                fifo.sink.stb.eq(self.sink_stb[i]),
+                self.sink_ack[i].eq(fifo.sink.ack),
+                fifo.sink.data.eq(self.sink_data[i]),
+            ]
+            self.sync.cxp_upconn += [
+                encoder.d.eq(fifo.source.data[:8]),
+                encoder.k.eq(fifo.source.data[8]),
+                encoder.disp_in.eq(self.disp_in),
+                self.disp_out[i].eq(encoder.disp_out),
+
+                source_stb[i].eq(fifo.source.stb),
+                fifo.source.ack.eq(self.source_ack[i]),
+                self.source_data[i].eq(encoder.output),
+                # reset ack after asserted 
+                If(self.source_ack[i], self.source_ack[i].eq(0)),
+            ]
+        # FIFOs transmission priority
+        self.submodules.pe = PriorityEncoder(nfifos)
+        self.comb += self.pe.i.eq(source_stb)
+
+class TxIdle(Module):
+    def __init__(self):
+        self.disp_in = Signal()
+        self.disp_out = Signal()
+
+        self.word_idx = Signal(max=4)
+        self.source_ack = Signal()
+        self.source_data = Signal(10)
+        
+        # # #
+
+        # CXP 2.1 section 9.2.5 
+        IDLE_CHARS = Array([
+            #[data, k]
+            [0b10111100, 1], #K28.5
+            [0b00111100, 1], #K28.1
+            [0b00111100, 1], #K28.1
+            [0b10111100, 0], #D28.5
+        ])
+
+        encoder = ClockDomainsRenamer("cxp_upconn")(SingleEncoder(True))
+        self.submodules += encoder
+
+        self.sync.cxp_upconn += [
+            encoder.d.eq(IDLE_CHARS[self.word_idx][0]),
+            encoder.k.eq(IDLE_CHARS[self.word_idx][1]),
+            encoder.disp_in.eq(self.disp_in),
+            self.disp_out.eq(encoder.disp_out),
+            self.source_data.eq(encoder.output),
+
+            If(self.source_ack,
+                # reset after asserted
+                self.source_ack.eq(0),
+
+                If(self.word_idx != 3,
+                   self.word_idx.eq(self.word_idx + 1),
+                ).Else(
+                    self.word_idx.eq(0),
+                )
+            ),
+        ]

src/gateware/zc706.py

@@ -25,6 +25,7 @@ import analyzer
 import acpki
 import drtio_aux_controller
 import zynq_clocking
+import cxp_4r_fmc, cxp
 from config import write_csr_file, write_mem_file, write_rustc_cfg_file
 
 class SMAClkinForward(Module):
@@ -138,7 +139,7 @@ class ZC706(SoCCore):
         platform.add_extension(si5324_fmc33)
         self.comb += platform.request("si5324_33").rst_n.eq(1)
 
-        cdr_clk = Signal()
+        self.cdr_clk = Signal()
         cdr_clk_buf = Signal()
         si5324_out = platform.request("si5324_clkout")
         platform.add_period_constraint(si5324_out.p, 8.0)
@@ -146,11 +147,11 @@ class ZC706(SoCCore):
             Instance("IBUFDS_GTE2",
                 i_CEB=0,
                 i_I=si5324_out.p, i_IB=si5324_out.n,
-                o_O=cdr_clk,
+                o_O=self.cdr_clk,
                 p_CLKCM_CFG="TRUE",
                 p_CLKRCV_TRST="TRUE",
                 p_CLKSWING_CFG=3),
-            Instance("BUFG", i_I=cdr_clk, o_O=cdr_clk_buf)
+            Instance("BUFG", i_I=self.cdr_clk, o_O=cdr_clk_buf)
         ]
         self.config["HAS_SI5324"] = None
         self.config["SI5324_AS_SYNTHESIZER"] = None
@@ -648,6 +649,47 @@ class _NIST_QC2_RTIO:
         self.add_rtio(rtio_channels)
 
 
+class _CXP_FMC_RTIO():
+    """
+    CoaXpress FMC with 4 CXP channel and 1 SMA trigger
+    """
+    def __init__(self):
+        platform = self.platform
+        platform.add_extension(cxp_4r_fmc.fmc_adapter_io)
+        platform.add_extension(leds_fmc33)
+
+        debug_sma = [
+            ("user_sma_clock_33", 0,
+                Subsignal("p_tx", Pins("AD18"), IOStandard("LVCMOS33")),
+                Subsignal("n_rx", Pins("AD19"), IOStandard("LVCMOS33")),
+            ),
+        ]
+        platform.add_extension(debug_sma)
+
+        clk_freq = 125e6
+
+        self.submodules.cxp_gtx = cxp.CXP(
+            refclk=self.cdr_clk,
+            pads=platform.request("CXP_HS", 0),
+            sys_clk_freq=clk_freq,
+            debug_sma=platform.request("user_sma_clock_33")
+        )
+        self.csr_devices.append("cxp_gtx")
+
+        rtio_channels = []
+        # FIXME remove this placeholder RTIO channel
+        # There are too few RTIO channels and cannot be compiled (adr width issue of the lane distributor)
+        # see https://github.com/m-labs/artiq/pull/2158 for similar issue
+        print("USER LED at RTIO channel 0x{:06x}".format(len(rtio_channels)))
+        phy = ttl_simple.Output(self.platform.request("user_led_33", 0))
+        self.submodules += phy
+        rtio_channels.append(rtio.Channel.from_phy(phy))
+        self.config["HAS_RTIO_LOG"] = None
+        rtio_channels.append(rtio.LogChannel())
+
+        self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
+        self.add_rtio(rtio_channels)
+
 class NIST_CLOCK(ZC706, _NIST_CLOCK_RTIO):
     def __init__(self, acpki, drtio100mhz):
         ZC706.__init__(self, acpki)
@@ -680,8 +722,14 @@ class NIST_QC2_Satellite(_SatelliteBase, _NIST_QC2_RTIO):
         _SatelliteBase.__init__(self, acpki, drtio100mhz)
         _NIST_QC2_RTIO.__init__(self)
 
+class CXP_FMC(ZC706, _CXP_FMC_RTIO):
+    def __init__(self, acpki, drtio100mhz):
+        ZC706.__init__(self, acpki)
+        # self.submodules += SMAClkinForward(self.platform)
+        _CXP_FMC_RTIO.__init__(self)
+
 VARIANTS = {cls.__name__.lower(): cls for cls in [NIST_CLOCK, NIST_CLOCK_Master, NIST_CLOCK_Satellite,
-                                                  NIST_QC2, NIST_QC2_Master, NIST_QC2_Satellite]}
+                                                  NIST_QC2, NIST_QC2_Master, NIST_QC2_Satellite, CXP_FMC]}
 
 def main():
     parser = argparse.ArgumentParser(