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base: morgan:3da71dedd74b24b915f423f208bf979f8c68dd8c
Branches Tags
morgan:master
morgan:coax_proto
morgan:refactor_wrpll
morgan:new_filter
morgan:rtio_fix
morgan:filter
morgan:DDMTD
morgan:wrpll_mmcm_fix
morgan:deglitcher
morgan:WRPLL
morgan:vector_fix
morgan:fiq_issue
morgan:testing
morgan:release-7
morgan:release-6
M-Labs:release-7
M-Labs:release-8
M-Labs:master
M-Labs:release-6
..
compare: morgan:0e75694c6b9d97a18277bf811a528e65930248da
Branches Tags
morgan:coax_proto
morgan:master
morgan:refactor_wrpll
morgan:new_filter
morgan:rtio_fix
morgan:filter
morgan:DDMTD
morgan:wrpll_mmcm_fix
morgan:deglitcher
morgan:WRPLL
morgan:vector_fix
morgan:fiq_issue
morgan:testing
morgan:release-7
morgan:release-6
M-Labs:release-7
M-Labs:release-8
M-Labs:master
M-Labs:release-6

No commits in common. "3da71dedd74b24b915f423f208bf979f8c68dd8c" and "0e75694c6b9d97a18277bf811a528e65930248da" have entirely different histories.
3da71dedd7 ... 0e75694c6b

7 changed files with 19 additions and 26 deletions
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8
flake.lock
View File

@ -217,11 +217,11 @@
]
},
"locked": {
"lastModified": 1701572971,
"narHash": "sha256-f8IPIYenff7B8S3p/pjVxT/0HVZuJXtdg2jtMpaZEbM=",
"lastModified": 1697795161,
"narHash": "sha256-p89w9eoFJ2VFTDZ5Mrv5vsH0E1Ko9z1C6Ett281hCHg=",
"ref": "refs/heads/master",
"rev": "91bae572f913abc2f95acb899ca5afa33eeaa036",
"revCount": 634,
"rev": "be672ab662d8134ee11412a651864824f6483d4a",
"revCount": 630,
"type": "git",
"url": "https://git.m-labs.hk/m-labs/zynq-rs"
},

2
flake.nix
View File

@ -134,7 +134,7 @@
cargoLock = {
lockFile = src/Cargo.lock;
outputHashes = {
"libasync-0.0.0" = "sha256-f8IPIYenff7B8S3p/pjVxT/0HVZuJXtdg2jtMpaZEbM=";
"libasync-0.0.0" = "sha256-p89w9eoFJ2VFTDZ5Mrv5vsH0E1Ko9z1C6Ett281hCHg=";
};
};

12
src/Cargo.lock generated
View File

@ -219,7 +219,7 @@ dependencies = [
[[package]]
name = "libasync"
version = "0.0.0"
source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#91bae572f913abc2f95acb899ca5afa33eeaa036"
source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#be672ab662d8134ee11412a651864824f6483d4a"
dependencies = [
"embedded-hal",
"libcortex_a9",
@ -251,7 +251,7 @@ dependencies = [
[[package]]
name = "libboard_zynq"
version = "0.0.0"
source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#91bae572f913abc2f95acb899ca5afa33eeaa036"
source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#be672ab662d8134ee11412a651864824f6483d4a"
dependencies = [
"bit_field",
"embedded-hal",
@ -276,7 +276,7 @@ dependencies = [
[[package]]
name = "libconfig"
version = "0.1.0"
source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#91bae572f913abc2f95acb899ca5afa33eeaa036"
source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#be672ab662d8134ee11412a651864824f6483d4a"
dependencies = [
"core_io",
"fatfs",
@ -287,7 +287,7 @@ dependencies = [
[[package]]
name = "libcortex_a9"
version = "0.0.0"
source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#91bae572f913abc2f95acb899ca5afa33eeaa036"
source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#be672ab662d8134ee11412a651864824f6483d4a"
dependencies = [
"bit_field",
"libregister",
@ -303,7 +303,7 @@ checksum = "33a33a362ce288760ec6a508b94caaec573ae7d3bbbd91b87aa0bad4456839db"
[[package]]
name = "libregister"
version = "0.0.0"
source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#91bae572f913abc2f95acb899ca5afa33eeaa036"
source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#be672ab662d8134ee11412a651864824f6483d4a"
dependencies = [
"bit_field",
"vcell",
@ -313,7 +313,7 @@ dependencies = [
[[package]]
name = "libsupport_zynq"
version = "0.0.0"
source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#91bae572f913abc2f95acb899ca5afa33eeaa036"
source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#be672ab662d8134ee11412a651864824f6483d4a"
dependencies = [
"cc",
"compiler_builtins",

12
src/gateware/kasli_soc.py
View File

@ -160,9 +160,7 @@ class GenericStandalone(SoCCore):
self.rtio_channels.append(rtio.LogChannel())
self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
self.submodules.rtio_core = rtio.Core(
self.rtio_tsc, self.rtio_channels, lane_count=description["sed_lanes"]
)
self.submodules.rtio_core = rtio.Core(self.rtio_tsc, self.rtio_channels)
self.csr_devices.append("rtio_core")
if self.acpki:
@ -289,9 +287,7 @@ class GenericMaster(SoCCore):
self.add_csr_group("drtioaux", drtioaux_csr_group)
self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
self.submodules.rtio_core = rtio.Core(
self.rtio_tsc, self.rtio_channels, lane_count=description["sed_lanes"]
)
self.submodules.rtio_core = rtio.Core(self.rtio_tsc, self.rtio_channels)
self.csr_devices.append("rtio_core")
if self.acpki:
@ -448,9 +444,7 @@ class GenericSatellite(SoCCore):
self.submodules.rtio_dma = dma.DMA(self.ps7.s_axi_hp0)
self.csr_devices.append("rtio_dma")
self.submodules.local_io = SyncRTIO(
self.rtio_tsc, self.rtio_channels, lane_count=description["sed_lanes"]
)
self.submodules.local_io = SyncRTIO(self.rtio_tsc, self.rtio_channels)
self.comb += self.drtiosat.async_errors.eq(self.local_io.async_errors)
self.submodules.cri_con = rtio.CRIInterconnectShared(

1
src/gateware/zc706.py
View File

@ -451,7 +451,6 @@ class _SatelliteBase(SoCCore):
def add_rtio(self, rtio_channels):
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj")
self.rustc_cfg["has_rtio_moninj"] = None
if self.acpki:
self.rustc_cfg["ki_impl"] = "acp"

2
src/libboard_artiq/src/lib.rs
View File

@ -27,7 +27,7 @@ pub mod drtioaux_async;
#[cfg(has_drtio)]
#[path = "../../../build/mem.rs"]
pub mod mem;
#[cfg(all(feature = "target_kasli_soc", has_drtio))]
#[cfg(feature = "target_kasli_soc")]
pub mod io_expander;
#[cfg(has_grabber)]
pub mod grabber;

8
src/runtime/src/main.rs
View File

@ -11,7 +11,7 @@
extern crate alloc;
#[cfg(all(feature = "target_kasli_soc", has_drtio))]
#[cfg(feature = "target_kasli_soc")]
use core::cell::RefCell;
use log::{info, warn, error};
@ -23,7 +23,7 @@ use void::Void;
use libconfig::Config;
use libcortex_a9::l2c::enable_l2_cache;
use libboard_artiq::{logger, identifier_read, init_gateware, pl};
#[cfg(all(feature = "target_kasli_soc", has_drtio))]
#[cfg(feature = "target_kasli_soc")]
use libboard_artiq::io_expander;
const ASYNC_ERROR_COLLISION: u8 = 1 << 0;
@ -93,7 +93,7 @@ async fn report_async_rtio_errors() {
#[cfg(all(feature = "target_kasli_soc", has_drtio))]
#[cfg(feature = "target_kasli_soc")]
async fn io_expanders_service(
i2c_bus: RefCell<&mut libboard_zynq::i2c::I2c>,
io_expander0: RefCell<io_expander::IoExpander>,
@ -149,7 +149,7 @@ pub fn main_core0() {
info!("gateware ident: {}", identifier_read(&mut [0; 64]));
i2c::init();
#[cfg(all(feature = "target_kasli_soc", has_drtio))]
#[cfg(feature = "target_kasli_soc")]
{
let i2c_bus = unsafe { (i2c::I2C_BUS).as_mut().unwrap() };
let mut io_expander0 = io_expander::IoExpander::new(i2c_bus, 0).unwrap();