forked from M-Labs/artiq-zynq
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1f8ef6bf96
Author | SHA1 | Date |
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morgan | 1f8ef6bf96 | |
morgan | 0e69c5d5ba | |
morgan | dbce74d831 |
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@ -1,4 +1,6 @@
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from migen import *
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from migen.genlib.cdc import MultiReg, PulseSynchronizer
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from migen.genlib.misc import WaitTimer
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from misoc.cores.code_8b10b import Encoder, Decoder
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@ -6,8 +8,8 @@ from misoc.interconnect.csr import *
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from artiq.gateware.drtio.transceiver.gtx_7series_init import *
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from operator import add
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from functools import reduce
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from operator import add
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class CXP_DownConn(Module, AutoCSR):
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def __init__(self, refclk, pads, sys_clk_freq, debug_sma, pmod_pads):
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@ -99,13 +101,12 @@ class CXP_DownConn(Module, AutoCSR):
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Instance("OBUF", i_I=gtx.cd_cxp_gtx_tx.clk, o_O=debug_sma.n_rx),
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# pmod 0-7 pin
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Instance("OBUF", i_I=gtx.clk_aligner.rxslide, o_O=pmod_pads[0]),
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Instance("OBUF", i_I=gtx.clk_aligner.ready, o_O=pmod_pads[1]),
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# Instance("OBUF", i_I=gtx.tx_init.Xxdlysresetdone , o_O=pmod_pads[2]),
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# Instance("OBUF", i_I=gtx.tx_init.Xxphaligndone , o_O=pmod_pads[3]),
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# Instance("OBUF", i_I=, o_O=pmod_pads[4]),
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# Instance("OBUF", i_I=, o_O=pmod_pads[5]),
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# Instance("OBUF", i_I=, o_O=pmod_pads[6]),
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Instance("OBUF", i_I=gtx.comma_det.aligner_en_rxclk, o_O=pmod_pads[0]),
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Instance("OBUF", i_I=gtx.comma_det.rxinit_done, o_O=pmod_pads[1]),
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Instance("OBUF", i_I=gtx.comma_det.restart, o_O=pmod_pads[2]),
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Instance("OBUF", i_I=gtx.comma_det.comma_aligned, o_O=pmod_pads[3]),
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Instance("OBUF", i_I=gtx.comma_det.ready, o_O=pmod_pads[4]),
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Instance("OBUF", i_I=gtx.comma_det.valid_data, o_O=pmod_pads[5]),
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# Instance("OBUF", i_I=, o_O=pmod_pads[7]),
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]
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@ -131,6 +132,8 @@ class CXP_DownConn(Module, AutoCSR):
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self.decoded_k_0 = CSRStatus()
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self.decoded_k_1 = CSRStatus()
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self.shifted = CSRStatus(9)
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self.sync.cxp_gtx_tx += [
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If(counter == 0,
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@ -158,6 +161,9 @@ class CXP_DownConn(Module, AutoCSR):
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self.rxdata_1.status.eq(self.gtx.decoders[1].input),
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self.decoded_data_1.status.eq(self.gtx.decoders[1].d),
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self.decoded_k_1.status.eq(self.gtx.decoders[1].k),
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# If(self.gtx.clk_aligner.comma_det.detected,
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# self.shifted.status.eq(self.gtx.clk_aligner.comma_det.bitshift),
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# )
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]
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@ -253,77 +259,108 @@ class QPLL(Module):
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)
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]
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# Warning: Xilinx transceivers are LSB first, and comma needs to be flipped
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# compared to the usual 8b10b binary representation.
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class Manual_Aligner(Module):
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def __init__(self, comma, check_cycles=20000):
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self.rxslide = Signal()
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self.rxdata = Signal(20)
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class Comma_Detector(Module):
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def __init__(self, comma, check_period=50_000, width=20):
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self.data = Signal(width)
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self.rxinit_done = Signal()
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self.aligner_en_rxclk = Signal()
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self.ready = Signal()
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self.restart = Signal()
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# # #
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checks_reset = Signal()
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error_seen = Signal()
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comma_seen = Signal()
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rx1cnt = Signal(max=11)
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self.comma_aligned = Signal()
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self.valid_data = Signal()
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self.submodules.recheck_ps = recheck_ps = PulseSynchronizer("sys", "cxp_gtx_rx")
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aligned = Signal()
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self.specials += MultiReg(self.comma_aligned, aligned)
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valid_data = Signal()
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self.specials += MultiReg(self.valid_data, valid_data)
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comma_n = ~comma & 0b1111111111
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rx1cnt = Signal(max=11)
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self.sync.cxp_gtx_rx += [
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rx1cnt.eq(reduce(add, [self.rxdata[i] for i in range(10)])),
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If(checks_reset,
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error_seen.eq(0)
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).Elif((rx1cnt != 4) & (rx1cnt != 5) & (rx1cnt != 6),
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error_seen.eq(1)
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rx1cnt.eq(reduce(add, [self.data[i] for i in range(10)])),
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If(recheck_ps.o,
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self.comma_aligned.eq(0)
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).Elif((self.data[:10] == comma) | (self.data[:10] == comma_n),
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self.comma_aligned.eq(1)
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),
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If(checks_reset,
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comma_seen.eq(0)
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).Elif((self.rxdata[:10] == comma) | (self.rxdata[:10] == comma_n),
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comma_seen.eq(1)
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If(recheck_ps.o,
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self.valid_data.eq(0)
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).Elif((rx1cnt == 4) | (rx1cnt == 5) | (rx1cnt == 6),
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self.valid_data.eq(1)
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),
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]
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check_counter = Signal(reset=check_period-1, max=check_period)
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check = Signal()
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aligner_en_sys = Signal()
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self.specials += MultiReg(aligner_en_sys, self.aligner_en_rxclk, odomain="cxp_gtx_rx")
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self.sync += [
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check.eq(0),
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If(check_counter == 0,
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check_counter.eq(check_counter.reset),
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check.eq(1),
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).Else(
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check_counter.eq(check_counter - 1),
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)
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]
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# minimum of 32 RXUSRCLK2 cycles are required between two RXSLIDE pulses
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slide_timer = ClockDomainsRenamer("cxp_gtx_rx")(WaitTimer(64))
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self.submodules += slide_timer
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counter = Signal(reset=check_cycles-1, max=check_cycles)
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fsm = ClockDomainsRenamer("cxp_gtx_rx")(FSM(reset_state="IDLE"))
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self.submodules += fsm
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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slide_timer.wait.eq(1),
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If(slide_timer.done,
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If(comma_seen,
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NextState("READY"),
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aligner_en_sys.eq(1),
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If(check,
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recheck_ps.i.eq(1),
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If(aligned,
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NextState("WAIT_NO_ERROR"),
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).Else(
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NextState("SLIDING")
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self.restart.eq(1),
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)
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)
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)
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fsm.act("SLIDING",
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self.rxslide.eq(1),
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checks_reset.eq(1),
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NextState("IDLE")
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fsm.act("WAIT_NO_ERROR",
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aligner_en_sys.eq(1),
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If(check,
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recheck_ps.i.eq(1),
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If(aligned & valid_data,
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NextState("READY"),
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).Else(
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self.restart.eq(1),
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NextState("IDLE"),
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)
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)
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)
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fsm.act("READY",
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self.ready.eq(1),
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If(counter == 0,
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NextValue(counter, check_cycles - 1),
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If(error_seen,
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If(check,
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recheck_ps.i.eq(1),
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If(~(aligned & valid_data),
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self.restart.eq(1),
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NextState("IDLE"),
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)
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).Else(
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NextValue(counter, counter - 1),
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)
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)
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class GTX(Module):
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# Settings:
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# * GTX reference clock @ 125MHz
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@ -364,7 +401,7 @@ class GTX(Module):
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# TX generates cxp_tx clock, init must be in system domain
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# FIXME: 500e6 is used to fix Xx reset by holding gtxXxreset for a couple cycle more
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self.submodules.tx_init = tx_init = GTXInit(500e6, False, mode=tx_mode)
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self.submodules.rx_init = rx_init = GTXInit(500e6, True, mode=rx_mode)
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self.submodules.rx_init = rx_init = GTXInit(sys_clk_freq, True, mode=rx_mode)
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# RX receives restart commands from txusrclk domain
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# self.submodules.rx_init = rx_init = ClockDomainsRenamer("cxp_gtx_tx")(GTXInit(500e6, True, mode=rx_mode))
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@ -377,7 +414,7 @@ class GTX(Module):
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txdata = Signal(20)
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rxdata = Signal(20)
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rxslide = Signal()
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comma_align_en = Signal()
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# Note: the following parameters were set after consulting AR45360
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self.specials += \
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Instance("GTXE2_CHANNEL",
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@ -469,7 +506,7 @@ class GTX(Module):
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i_RXDFEXYDEN=1,
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i_RXDFEXYDHOLD=0,
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i_RXDFEXYDOVRDEN=0,
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i_RXLPMEN=0, # RXLPMEN = 0: DFE mode is enabled
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i_RXLPMEN=0, # RXLPMEN = 0: DFE mode is enabled for non scramble data
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p_RX_DFE_GAIN_CFG=0x0207EA,
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p_RX_DFE_VP_CFG=0b00011111100000011,
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p_RX_DFE_UT_CFG=0b10001000000000000,
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@ -507,21 +544,18 @@ class GTX(Module):
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# RX Byte and Word Alignment Attributes
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p_ALIGN_COMMA_DOUBLE="FALSE",
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p_ALIGN_COMMA_ENABLE=0b1111111111,
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p_ALIGN_COMMA_WORD=2,
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p_ALIGN_MCOMMA_DET="FALSE",
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p_ALIGN_COMMA_WORD=2, # allow rxslide to shift 20 times
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p_ALIGN_MCOMMA_DET="TRUE",
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p_ALIGN_MCOMMA_VALUE=0b1010000011,
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p_ALIGN_PCOMMA_DET="FALSE",
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p_ALIGN_PCOMMA_DET="TRUE",
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p_ALIGN_PCOMMA_VALUE=0b0101111100,
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p_SHOW_REALIGN_COMMA="FALSE",
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p_RXSLIDE_AUTO_WAIT=7,
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p_RXSLIDE_MODE="PCS",
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p_RXSLIDE_MODE="OFF",
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p_RX_SIG_VALID_DLY=10,
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# Manual Word Alignment
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i_RXPCOMMAALIGNEN=0,
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i_RXMCOMMAALIGNEN=0,
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i_RXCOMMADETEN=1, # enable word alignment, but breaks rxrestart if gtxXxreset hold too short
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i_RXSLIDE=rxslide,
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i_RXPCOMMAALIGNEN=comma_align_en,
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i_RXMCOMMAALIGNEN=comma_align_en,
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i_RXCOMMADETEN=1, # enable auto word alignment
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# RX 8B/10B Decoder Attributes
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p_RX_DISPERR_SEQ_MATCH="FALSE",
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@ -648,12 +682,13 @@ class GTX(Module):
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]
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self.submodules.clk_aligner = clk_aligner = Manual_Aligner(0b0101111100)
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self.submodules.comma_det = comma_det = Comma_Detector(0b0101111100)
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self.comb += [
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clk_aligner.rxdata.eq(rxdata),
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rxslide.eq(clk_aligner.rxslide),
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self.rx_ready.eq(clk_aligner.ready),
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comma_det.data.eq(rxdata),
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comma_det.rxinit_done.eq(rx_init.done),
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comma_align_en.eq(comma_det.aligner_en_rxclk),
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self.rx_ready.eq(comma_det.ready),
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rx_init.restart.eq(self.rx_restart),
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rx_init.restart.eq(self.rx_restart | comma_det.restart),
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tx_init.restart.eq(self.tx_restart),
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]
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