src/gateware/kasli_soc.py

@@ -85,6 +85,9 @@ class GTP125BootstrapClock(Module):
 class GenericStandalone(SoCCore):
     def __init__(self, description, acpki=False):
         self.acpki = acpki
+        self.rustc_cfg = dict()
+
+        self.rustc_cfg["hw_rev"] = description["hw_rev"]
 
         platform = kasli_soc.Platform()
         platform.toolchain.bitstream_commands.extend([
@@ -95,12 +98,10 @@ class GenericStandalone(SoCCore):
             ident = "acpki_" + ident
         SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
 
-        self.config["HW_REV"] = description["hw_rev"]
-
         self.submodules += SMAClkinForward(self.platform)
 
-        self.config["HAS_SI5324"] = None
+        self.rustc_cfg["has_si5324"] = None
-        self.config["SI5324_SOFT_RESET"] = None
+        self.rustc_cfg["si5324_soft_reset"] = None
 
         clk_synth = platform.request("cdr_clk_clean_fabric")
         clk_synth_se = Signal()
@@ -139,14 +140,14 @@ class GenericStandalone(SoCCore):
         self.csr_devices.append("rtio_core")
 
         if self.acpki:
-            self.config["KI_IMPL"] = "acp"
+            self.rustc_cfg["ki_impl"] = "acp"
             self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
                                                          bus=self.ps7.s_axi_acp,
                                                          user=self.ps7.s_axi_acp_user,
                                                          evento=self.ps7.event.o)
             self.csr_devices.append("rtio")
         else:
-            self.config["KI_IMPL"] = "csr"
+            self.rustc_cfg["ki_impl"] = "csr"
             self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
             self.csr_devices.append("rtio")
 
@@ -166,7 +167,7 @@ class GenericStandalone(SoCCore):
         self.csr_devices.append("rtio_analyzer")
 
         if has_grabber:
-            self.config["HAS_GRABBER"] = None
+            self.rustc_cfg["has_grabber"] = None
             self.add_csr_group("grabber", self.grabber_csr_group)
             for grabber in self.grabber_csr_group:
                 self.platform.add_false_path_constraints(
@@ -178,6 +179,9 @@ class GenericMaster(SoCCore):
         clk_freq = description["rtio_frequency"]
 
         self.acpki = acpki
+        self.rustc_cfg = dict()
+
+        self.rustc_cfg["hw_rev"] = description["hw_rev"]
 
         platform = kasli_soc.Platform()
         platform.toolchain.bitstream_commands.extend([
@@ -188,8 +192,6 @@ class GenericMaster(SoCCore):
             ident = "acpki_" + ident
         SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
 
-        self.config["HW_REV"] = description["hw_rev"]
-
         self.submodules += SMAClkinForward(self.platform)
 
         data_pads = [platform.request("sfp", i) for i in range(4)]
@@ -217,8 +219,8 @@ class GenericMaster(SoCCore):
             self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk)
         fix_serdes_timing_path(platform)
 
-        self.config["HAS_SI5324"] = None
+        self.rustc_cfg["has_si5324"] = None
-        self.config["SI5324_SOFT_RESET"] = None
+        self.rustc_cfg["si5324_soft_reset"] = None
 
         self.rtio_channels = []
         has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"])
@@ -263,8 +265,8 @@ class GenericMaster(SoCCore):
             memory_address = self.axi2csr.register_port(coreaux.get_tx_port(), size)
             self.axi2csr.register_port(coreaux.get_rx_port(), size)
             self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, size * 2)
-        self.config["HAS_DRTIO"] = None
+        self.rustc_cfg["has_drtio"] = None
-        self.config["HAS_DRTIO_ROUTING"] = None
+        self.rustc_cfg["has_drtio_routing"] = None
         self.add_csr_group("drtio", drtio_csr_group)
         self.add_csr_group("drtioaux", drtioaux_csr_group)
         self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
@@ -273,14 +275,14 @@ class GenericMaster(SoCCore):
         self.csr_devices.append("rtio_core")
 
         if self.acpki:
-            self.config["KI_IMPL"] = "acp"
+            self.rustc_cfg["ki_impl"] = "acp"
             self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
                                                          bus=self.ps7.s_axi_acp,
                                                          user=self.ps7.s_axi_acp_user,
                                                          evento=self.ps7.event.o)
             self.csr_devices.append("rtio")
         else:
-            self.config["KI_IMPL"] = "csr"
+            self.rustc_cfg["ki_impl"] = "csr"
             self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
             self.csr_devices.append("rtio")
 
@@ -304,7 +306,7 @@ class GenericMaster(SoCCore):
         self.csr_devices.append("rtio_analyzer")
 
         if has_grabber:
-            self.config["HAS_GRABBER"] = None
+            self.rustc_cfg["has_grabber"] = None
             self.add_csr_group("grabber", self.grabber_csr_group)
         
 
@@ -321,6 +323,9 @@ class GenericSatellite(SoCCore):
         clk_freq = description["rtio_frequency"]
 
         self.acpki = acpki
+        self.rustc_cfg = dict()
+
+        self.rustc_cfg["hw_rev"] = description["hw_rev"]
 
         platform = kasli_soc.Platform()
         platform.toolchain.bitstream_commands.extend([
@@ -331,8 +336,6 @@ class GenericSatellite(SoCCore):
             ident = "acpki_" + ident
         SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
 
-        self.config["HW_REV"] = description["hw_rev"]
-
         data_pads = [platform.request("sfp", i) for i in range(4)]
         
         self.submodules.gt_drtio = gtx_7series.GTX(
@@ -417,21 +420,21 @@ class GenericSatellite(SoCCore):
             # and registered in PS interface
             # manually, because software refers to rx/tx by halves of entire memory block, not names
             self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, mem_size * 2)
-        self.config["HAS_DRTIO"] = None
+        self.rustc_cfg["has_drtio"] = None
-        self.config["HAS_DRTIO_ROUTING"] = None
+        self.rustc_cfg["has_drtio_routing"] = None
         self.add_csr_group("drtioaux", drtioaux_csr_group)
         self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
         self.add_csr_group("drtiorep", drtiorep_csr_group)
 
         if self.acpki:
-            self.config["KI_IMPL"] = "acp"
+            self.rustc_cfg["ki_impl"] = "acp"
             self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
                                                          bus=self.ps7.s_axi_acp,
                                                          user=self.ps7.s_axi_acp_user,
                                                          evento=self.ps7.event.o)
             self.csr_devices.append("rtio")
         else:
-            self.config["KI_IMPL"] = "csr"
+            self.rustc_cfg["ki_impl"] = "csr"
             self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
             self.csr_devices.append("rtio")
 
@@ -458,7 +461,7 @@ class GenericSatellite(SoCCore):
         self.csr_devices.append("rtio_analyzer")
 
         rtio_clk_period = 1e9/clk_freq
-        self.config["RTIO_FREQUENCY"] = str(clk_freq/1e6)
+        self.rustc_cfg["rtio_frequency"] = str(clk_freq/1e6)
 
         self.submodules.siphaser = SiPhaser7Series(
             si5324_clkin=platform.request("cdr_clk"),
@@ -466,15 +469,16 @@ class GenericSatellite(SoCCore):
             ultrascale=False,
             rtio_clk_freq=self.gt_drtio.rtio_clk_freq)
         self.csr_devices.append("siphaser")
-        self.config["HAS_SI5324"] = None
+        self.rustc_cfg["has_si5324"] = None
-        self.config["SI5324_SOFT_RESET"] = None
+        self.rustc_cfg["has_siphaser"] = None
+        self.rustc_cfg["si5324_soft_reset"] = None
 
         gtx0 = self.gt_drtio.gtxs[0]
         platform.add_false_path_constraints(
             gtx0.txoutclk, gtx0.rxoutclk)
 
         if has_grabber:
-            self.config["HAS_GRABBER"] = None
+            self.rustc_cfg["has_grabber"] = None
             self.add_csr_group("grabber", self.grabber_csr_group)
             # no RTIO CRG here
         
@@ -499,14 +503,11 @@ def write_csr_file(soc, filename):
 
 def write_rustc_cfg_file(soc, filename):
     with open(filename, "w") as f:
-        for name, origin, busword, obj in soc.get_csr_regions():
+        for k, v in sorted(soc.rustc_cfg.items(), key=itemgetter(0)):
-            f.write("has_{}\n".format(name.lower()))
+            if v is None:
-        for name, value in soc.get_constants():
+                f.write("{}\n".format(k))
-            if name.upper().startswith("CONFIG_"):
+            else:
-                if value is None:
+                f.write("{}=\"{}\"\n".format(k, v))
-                    f.write("{}\n".format(name.lower()[7:]))
-                else:
-                    f.write("{}=\"{}\"\n".format(name.lower()[7:], str(value)))
 
 
 def main():

src/libboard_artiq/src/io_expander.rs

@@ -152,7 +152,6 @@ impl IoExpander {
     }
 
     pub fn service(&mut self, i2c: &mut i2c::I2c) -> Result<(), &'static str> {
-        #[cfg(has_virtual_leds)]        
         for (led, port, bit) in self.virtual_led_mapping.iter() {
             let level = unsafe { csr::virtual_leds::status_read() >> led & 1 };
             self.set(*port, *bit, level != 0);

src/runtime/src/main.rs

@@ -145,7 +145,6 @@ pub fn main_core0() {
     i2c::init();
     let i2c_bus = unsafe { (i2c::I2C_BUS).as_mut().unwrap() };
 
-    #[cfg(feature = "target_kasli_soc")]
     let (mut io_expander0, mut io_expander1);
     #[cfg(feature = "target_kasli_soc")]
     {

src/satman/src/main.rs

@@ -223,8 +223,8 @@ fn process_aux_packet(
 
         drtioaux::Packet::MonitorRequest {
             destination: _destination,
-            channel,
+            channel: _channel,
-            probe,
+            probe: _probe,
         } => {
             forward!(_routing_table, _destination, *_rank, _repeaters, &packet, timer);
             let value;
@@ -244,9 +244,9 @@ fn process_aux_packet(
         }
         drtioaux::Packet::InjectionRequest {
             destination: _destination,
-            channel,
+            channel: _channel,
-            overrd,
+            overrd: _overrd,
-            value,
+            value: _value,
         } => {
             forward!(_routing_table, _destination, *_rank, _repeaters, &packet, timer);
             #[cfg(has_rtio_moninj)]
@@ -259,8 +259,8 @@ fn process_aux_packet(
         }
         drtioaux::Packet::InjectionStatusRequest {
             destination: _destination,
-            channel,
+            channel: _channel,
-            overrd,
+            overrd: _overrd,
         } => {
             forward!(_routing_table, _destination, *_rank, _repeaters, &packet, timer);
             let value;
@@ -612,7 +612,6 @@ pub extern "C" fn main_core0() -> i32 {
     let mut i2c = I2c::i2c0();
     i2c.init().expect("I2C initialization failed");
 
-    #[cfg(feature = "target_kasli_soc")]
     let (mut io_expander0, mut io_expander1);
     #[cfg(feature = "target_kasli_soc")]
     {