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artiq-zynq
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Code Pull Requests Activity
793 Commits 16 Branches 0 Tags 4.2 MiB
Commit Graph

537 Commits

Author SHA1 Message Date
morgan e055a11e1c cxp downconn: cleanup comma detector 2024-08-09 16:52:13 +08:00
morgan 1f8ef6bf96 cxp downconn: use auto aligner 
cxp downconn: fix autoaligner checking
 2024-08-09 15:37:45 +08:00
morgan 0e69c5d5ba cxp downconn: refactor bruteforce aligner 2024-08-09 15:37:22 +08:00
morgan dbce74d831 cxp downconn: cleanup & use bruteforce aligner 2024-08-09 15:37:22 +08:00
morgan 2aef11143a cxp downconn fw: doc clean up 2024-08-02 12:40:16 +08:00
morgan 77bff39212 cxp downconn fw: add manual alignment test 2024-08-02 12:36:46 +08:00
morgan 160fcc657a cxp downconn: remove bruteforce aligner 2024-08-02 12:36:46 +08:00
morgan bf1fd2d79b cxp downconn: add manual alignment & rxrestart 2024-08-02 12:36:46 +08:00
morgan 452c3cee64 cxp downconn fw: add CXP datarate update printout 2024-08-01 17:38:12 +08:00
morgan 4436dc930e cxp downconn fw: add qpll linerate change 2024-08-01 12:33:22 +08:00
morgan 5a40422f1d cxp downconn: fix tx reset & cleanup 2024-08-01 11:21:36 +08:00
morgan e0369d2eb2 cxp downconn fw: add DRP for linerate 2024-07-31 16:10:25 +08:00
morgan 1e87428c68 cxp downconn: add DRP for tx/rx divider 2024-07-31 16:10:06 +08:00
morgan 0e4fb4cbfe cxp downconn fw: add QPLL setup 2024-07-29 17:23:00 +08:00
morgan ccd3e6618a cxp downconn: replace QPLL with CPLL 
cxp downconn: add QPLL with its reset CSR
cxp downconn: set QPLL as CLK source for GTX
cxp downconn: remove PLL_reset signal from tx_init to prevent race
condition
cxp downconn: rename cxp_gtx to GTX
 2024-07-29 17:22:32 +08:00
morgan 563e06ca8d cxp upconn: disable debug sma & pmod output 2024-07-29 17:20:10 +08:00
morgan 57d6e9a669 cxp downconn fw: update csr function name 2024-07-26 17:36:29 +08:00
morgan 1f0154d5b2 cxp: remove all cxp downconn interface 2024-07-26 17:36:16 +08:00
morgan a41e78d3d3 cxp downconn: add csr interface here 2024-07-26 17:36:06 +08:00
morgan 52f77a6331 cxp downconn fw: remove data[4:8] 2024-07-26 17:01:54 +08:00
morgan 1a210a010a cxp: remove data[4:8] 2024-07-26 17:01:26 +08:00
morgan 398eb135c7 cxp downconn: push IDLE word to buf b4 tx&rx init 2024-07-26 16:26:08 +08:00
morgan 865434763d cxp downconn: fix bruteforcealigner 2024-07-26 16:24:18 +08:00
morgan 4ba1c5ef2e cxp downconn fw: add idle data 2024-07-26 15:24:59 +08:00
morgan faef1d2dff cxp downconn: add interface for buildin aligner 2024-07-26 15:24:58 +08:00
morgan 20e388d043 cxp downconn: explore cpll & txusrclk_pll divider 2024-07-25 17:39:11 +08:00
morgan 6c53447808 cxp downconn firmware: init 
cxp down fw: cleanup
 2024-07-23 17:43:06 +08:00
morgan 14aa81c8a2 cxp upconn firmware: init 2024-07-23 17:09:33 +08:00
morgan 82af01350f cxp: add upconn, downconn & crc 
cxp: add crc32 for cxp
cxp: add upconn & downconn
 2024-07-23 17:09:22 +08:00
morgan 1f033d605c cxp upconn: add low speed serial 
cxp upconn: add low speed serial
cxp upconn: add pll for bitrate2x mode
cxp upconn: add tx_fifos & idle with encoder
cxp upconn: add priority packet that send in word/char boundary
 2024-07-23 17:08:33 +08:00
morgan 7d5e3c1ef9 cxp downconn: add high speed serial 
cxp downconn: add bruteforcephase aligner
cxp downconn: add gtx with mmcm for TXUSRCLK freq requirement
cxp downconn: add loopback mode parameter for testing
 2024-07-23 17:08:33 +08:00
morgan 95ec9b1253 zc706: add CXP_DEMO variant 
cxp fmc: add USER LED to allow compilation
cxp fmc: add debug pmod pads
 2024-07-23 17:01:29 +08:00
morgan abd9157065 fmc: add cxp_4r_fmc adepter io 2024-07-23 17:01:23 +08:00
morgan 586fd2f17e Gateware: remove redundant si549.py & wrpll.py 2024-05-30 15:27:16 +08:00
morgan 377f8779a0 kasli soc: refactor to use wrpll from artiq 2024-05-30 15:25:33 +08:00
mwojcik 2b2ebb5354 aux: increase max payload size 2024-05-20 15:20:06 +08:00
morgan 35ea0ed2ca WRPLL: add filter for DRTIO 100MHz 2024-05-08 18:50:55 +08:00
morgan cdf4ff24c0 WRPLL: replace PI controller with new filter 2024-05-08 18:50:55 +08:00
morgan 285b02c4b1 WRPLL: remove anti-windup 2024-05-08 18:50:55 +08:00
morgan 53cb592d19 kasli soc: add rtio_frequency cfg for runtime 2024-05-08 16:14:56 +08:00
morgan 1d603c73b7 DDMTD: replace 1st edge to median edge deglitcher 2024-04-29 13:05:02 +08:00
morgan 61315c29b9 Si549: recalibrate TAG_OFFSET for ISERDESE2 2024-04-29 13:03:30 +08:00
morgan 3f57de6ec7 DDMTD: replace FD with ISERDESE2 2024-04-29 13:03:30 +08:00
morgan cca23aa2a5 wrpll runtime: reduce mmcm output jitter 
rtio_clocking: update mmcm setting to use HIGH bandwidth
 2024-04-29 11:20:50 +08:00
morgan 2bbaea3ad5 SMAFreqMulti: set mmcm bw to HIGH for lower jitter 2024-04-29 11:20:50 +08:00
mwojcik 0a19f8fb89 satman: revert async flag changes 2024-04-26 11:37:14 +08:00
mwojcik a30c7d1f3a runtime: drtio aux refactoring, revert async flag 2024-04-26 11:37:14 +08:00
mwojcik 2d10503c20 libboard_artiq: support multiple aux rx buffers 2024-04-24 17:12:57 +08:00
mwojcik 92a29051f7 drtio_aux_controller: support aux_buffer_count 2024-04-24 17:12:39 +08:00
morgan 14fa038118 Firmware: Runtime WRPLL 
runtime: drive CLK_SEL to true when si549 is used
runtime & libboard_artiq: allow standalone to use io_expander
si549: add bit bang mmcm dynamic configuration
si549: add frequency counter for refclk
rtio_clocking & si549: add 125Mhz wrpll refclk setup
 2024-04-12 16:38:46 +08:00