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Commit Graph

103 Commits

Author SHA1 Message Date
morgan 6b50d83e67 pipeline GW: add test packet 2024-09-11 10:16:35 +08:00
morgan b2ce43155e pipeline GW: clean up variable naming 2024-09-10 16:43:54 +08:00
morgan d81c770e54 upconn GW: clean up 2024-09-10 12:17:51 +08:00
morgan 38485aec56 cxp: remove unused import 2024-09-09 10:51:27 +08:00
morgan fa674e32f5 upconn GW: rename variable 2024-09-09 10:08:26 +08:00
morgan 8a6e89b2d8 zc706: add CXP_DEMO variant 
zc706: add fmc pads
zc706: add constraint to fix comma alignment & setup/hold time issue
 2024-09-09 10:08:26 +08:00
morgan f0dda0fcf7 cxp: add upconn interface, downconn PHY & crc 
testing: add CSR control for tx trigger & trigger ack
upconn: connect trigger, trigger ack & command_packet to UpConnPHY
downconn: add GTX PHY
 2024-09-09 10:08:26 +08:00
morgan 04932d630f cxp pipeline: packet handling pipeline 
tx pipeline: add CRC32 inserter
tx pipeline: add start & end of packet code inserter
tx pipeline: add packet wrapper for start & stop packet indication
tx pipeline: add code source for trigger & trigger ack packet
tx pipeline: add packet for trigger & trigger ack
tx pipeline: add tx_command_packet for firmware
tx command packet: add fifo to store control packet
 2024-09-09 10:08:26 +08:00
morgan d9fb50c12e cxp upconn gw: add low speed serial PHY 
testing: add debug fifo output b4 encoder
cxp upconn: add low speed serial
cxp upconn: add reset, tx_busy, tx_enable
cxp upconn: add clockgen module for 20.83Mbps & 41.66Mbps using counters
cxp upconn: add oserdes using CEInserter
cxp upconn: add packet scheduler with CEInserter
scheduler: send priority packet during word/char boundary
scheduler: send IDLE every 10000 words
scheduler: encode packet before sending to oserdes
 2024-09-09 10:08:26 +08:00
morgan fa5ede6174 cxp downconn gw: add gtx up to 12.5Gbps 
testing: add txusrclk mmcm & loopback mode
testing: add debug output
downconn: add GTX and QPLL support
downconn: add DRP for GTX and QPLL to support all CXP linerates
GTX: add gtx with mmcm for TXUSRCLK freq requirement
GTX: add loopback mode parameter for testing
GTX: add gtx with 40bits internal width
GTX: use built-in comma aligner
GTX: add comma checker to ensure comma is aligner on highest linerate
GTX: set QPLL as CLK source for GTX
 2024-09-09 10:08:26 +08:00
morgan ce0f302b22 fmc: add cxp_4r_fmc adepter io 2024-09-09 10:08:26 +08:00
mwojcik 23857eef63 allow toggling SED spread with flash config key 2024-07-09 18:11:20 +08:00
morgan 586fd2f17e Gateware: remove redundant si549.py & wrpll.py 2024-05-30 15:27:16 +08:00
morgan 377f8779a0 kasli soc: refactor to use wrpll from artiq 2024-05-30 15:25:33 +08:00
morgan 53cb592d19 kasli soc: add rtio_frequency cfg for runtime 2024-05-08 16:14:56 +08:00
morgan 1d603c73b7 DDMTD: replace 1st edge to median edge deglitcher 2024-04-29 13:05:02 +08:00
morgan 3f57de6ec7 DDMTD: replace FD with ISERDESE2 2024-04-29 13:03:30 +08:00
morgan 2bbaea3ad5 SMAFreqMulti: set mmcm bw to HIGH for lower jitter 2024-04-29 11:20:50 +08:00
mwojcik 92a29051f7 drtio_aux_controller: support aux_buffer_count 2024-04-24 17:12:39 +08:00
morgan 7827c7b803 Gateware: kasli_soc WRPLL setup 
kasli_soc: use enable_wrpll from json to switch from si5324 to si549
kasli_soc: add wrpll for all variants
kasli_soc: add gtx & main tag nFIQ for all variants
kasli_soc: add clk_synth_se for master & satellite
kasli_soc: add wrpll_refclk for runtime
kasli_soc: add skewtester for satman
kasli_soc: add WRPLL_REF_CLK config for firmware
 2024-04-11 15:18:10 +08:00
morgan e4d8d44c7c Gateware: WRPLL 
ddmtd: add DDMTD and deglitcher
wrpll: add helper clockdomain
wrpll: add frequency counter
wrpll: add skewtester
wrpll: add gtx & main tag collection
wrpll: add gtx & main tag eventmanager for shared peripheral interrupt
wrpll: add SMA frequency multiplier to generate 125Mhz refclk
si549: add i2c and adpll programmer
 2024-04-11 15:18:04 +08:00
linuswck e1b2c45813 kasli_soc & zc706: Fix GTX Clock Path during INIT 2023-11-07 18:55:08 +08:00
linuswck e6372b9766 zynq_clocking: Allow ext signal to set cur_clk csr 
- for example, current_clock csr can be connected to tx_init.done
 2023-11-07 18:55:08 +08:00
linuswck 07044752b6 zynq_clocking: add ext_async_rst to AsyncRstSYNCR 2023-11-07 18:55:08 +08:00
linuswck 79fc5a7789 zynq_clocking: expose mmcm_locked for SYSCRG 
- mmcm_locked -> self.mmcm_locked
 2023-11-07 18:55:08 +08:00
Egor Savkin b768d5648c Add grabber module 
Signed-off-by: Egor Savkin <es@m-labs.hk>
 2023-10-16 14:35:20 +08:00
linuswck 136e24f597 kasli-soc: Add BUFG to the IBUFGDS for MMCM CLKIN1 
- Fix Vivado Compilation Error [DRC REQP-119]
- MMCME2_ADV CLKIN1 and CLKIN2 are now driven from the same source type (BUFG)
 2023-10-11 16:45:26 +08:00
linuswck b15322b6ba kasli_soc: Add support for shuttler on gateware 
- Port from artiq repo
- Add EEM_DRTIO gateware
 2023-10-10 11:22:05 +08:00
linuswck 8fd1306145 zynq_clocking: Add sys5x, 208MHz CLK & IDELAYCTRL 
- Port from artiq repo
- Generate sys5x for for EEM Serdes, 208MHz REF Clock for IDELAYCTRL
- Add IDELAYCTRL for IDEALYE2 in EEM Serdes
 2023-10-10 11:21:34 +08:00
mwojcik 49205eea17 satellite gateware: add kernel rtio to cri 2023-10-09 11:36:23 +08:00
sven-oxionics 656cbf4546 kasli_soc: use sed_lanes value from HW description 
https://github.com/m-labs/artiq/pull/1745 added a field for setting the number of SED lanes to the HW description. This commit makes it so that the setting is used for Kasli Soc as well.
 2023-10-06 15:37:56 +01:00
mwojcik ae3099dd8e kasli_soc: support 100MHz clock 2023-10-06 16:27:25 +08:00
morgan b3856e879b refactor `write_rustc_cfg_file()` 2023-09-11 11:48:19 +08:00
morgan 1ccae0d442 consolidate all `write..file()` into `config.py` 2023-09-11 11:48:19 +08:00
morgan 2c19f4ac31 replace rustc_cfg[ ] & change write_rustc_cfg_file 2023-09-11 11:48:19 +08:00
MorganTL 0e6309b95e change write_rustc_cfg_file to follow artiq repo 2023-08-30 14:56:12 +08:00
morgan 622d267d55 add virtual LEDs, improve IO expander setup, drive TX_DISABLE 
Co-authored-by: morgan <mc@m-labs.hk>
Co-committed-by: morgan <mc@m-labs.hk>
 2023-08-28 16:08:10 +08:00
linuswck 4ae8557018 drtio: remame drtio_transceiver to gt_drtio 
Co-authored-by: linuswck <linuswck@m-labs.hk>
Co-committed-by: linuswck <linuswck@m-labs.hk>
 2023-08-28 13:05:40 +08:00
Sebastien Bourdeauducq ca17cd419e Revert "kasli_soc: add SFP0..3 LED indication" 
This reverts commit 5111778363.
 2023-08-03 10:42:09 +08:00
morgan 5111778363 kasli_soc: add SFP0..3 LED indication 
Co-authored-by: morgan <mc@m-labs.hk>
Co-committed-by: morgan <mc@m-labs.hk>
 2023-07-24 16:30:14 +08:00
Sebastien Bourdeauducq ee438105b2 json: base -> drtio_role 2023-06-16 17:03:25 +08:00
Denis Ovchinnikov 63594d7e3d update configuration of IBUFDS_GTE2 
Input clock is terminated internally with 50 Ohm on each leg and to 4/5 MGTAVCC.
 2023-05-30 12:08:41 +08:00
mwojcik ad076dd4e9 zc706: fix satellite analyzer target 2023-05-24 09:52:16 +08:00
mwojcik c536a70890 satellite gateware: add rtio analyzer 2023-05-22 15:23:24 +08:00
mwojcik b747abe83c qc2: add 4 edge counters to the end of rtio 2023-04-03 12:25:07 +08:00
mwojcik 4b1ce1a6ff satellites: add rtio_dma, connect as cri master 2023-03-21 15:54:58 +08:00
mwojcik dce37a52aa KasliSoC satellite: fix serdes timing 2023-02-20 13:07:42 +08:00
mwojcik 46b2687d70 RTIO/SYS Clock merge 
Co-authored-by: mwojcik <mw@m-labs.hk>
Co-committed-by: mwojcik <mw@m-labs.hk>
 2023-02-17 15:52:43 +08:00
mwojcik 19e60073de kasli_soc: ident = variant name 2022-10-21 11:55:24 +08:00
mwojcik efc432352e zc706: no syncrtio for master, fixes hangs (#188) 2022-05-03 14:36:10 +08:00