forked from M-Labs/artiq-zynq
cxp upconn fw: test out crc32inserter pipeline
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@ -5,15 +5,17 @@ use crate::pl::csr;
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pub fn pipeline_test(timer: &mut GlobalTimer) {
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pub fn pipeline_test(timer: &mut GlobalTimer) {
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let arr = [
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let arr = [
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0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08
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// 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08
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// 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, // CXP CRC-32
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0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, // CXP CRC-32
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// 0x56, 0x86, 0x5D, 0x6f,
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// 0x56, 0x86, 0x5D, 0x6f,
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];
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];
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const LEN: usize = 12;
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const LEN: usize = 20;
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let mut pak_arr: [u8; LEN] = [0; LEN];
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let mut pak_arr: [u8; LEN] = [0; LEN];
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unsafe {
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unsafe {
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csr::cxp::txcore_din_len_write(arr.len() as u8);
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for a in arr.iter() {
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for a in arr.iter() {
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while csr::cxp::txcore_din_ready_read() == 0 {}
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while csr::cxp::txcore_din_ready_read() == 0 {}
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// println!("{:#04X}", *a);
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// println!("{:#04X}", *a);
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