forked from M-Labs/artiq-zynq
pipeline GW: remove cxp
pipeline GW: fix data loss when downstream not ack
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@ -2,7 +2,6 @@ from migen import *
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from migen.genlib.cdc import MultiReg
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from misoc.interconnect.csr import *
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from misoc.interconnect import stream
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from misoc.cores.liteeth_mini.mac.crc import LiteEthMACCRCEngine, LiteEthMACCRCChecker
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from functools import reduce
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from itertools import combinations
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@ -291,7 +290,6 @@ class RX_Debug_Buffer(Module,AutoCSR):
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class Duplicated_Char_Decoder(Module):
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def __init__(self):
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self.sink = stream.Endpoint(word_layout)
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self.buffer = stream.Endpoint(word_layout)
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self.source = stream.Endpoint(word_layout_dchar)
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# # #
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@ -314,22 +312,23 @@ class Duplicated_Char_Decoder(Module):
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# Hence, a pipeline approach is needed to avoid any s/h violation, where the majority voting result are pre-calculate and injected into the bus immediate after the PHY.
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# And any downstream modules can access the voting result without implementing the voting logic inside the decoder
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# cycle 1 - buffer data & calculate intermediate result
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buffer = stream.Endpoint(word_layout)
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self.sync += [
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self.sink.ack.eq(self.buffer.ack),
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self.buffer.stb.eq(self.sink.stb),
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If(self.sink.stb,
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self.buffer.data.eq(self.sink.data),
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self.buffer.k.eq(self.sink.k),
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),
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If((~buffer.stb | buffer.ack),
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buffer.stb.eq(self.sink.stb),
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buffer.payload.eq(self.sink.payload),
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)
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]
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self.comb += self.sink.ack.eq(~buffer.stb | buffer.ack)
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# cycle 1 - calculate ABC, ABD, ACD & BCD
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# calculate ABC, ABD, ACD, BCD
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char = [[self.sink.data[i*8:(i+1)*8], self.sink.k[i]] for i in range(4)]
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voters = [Record([("data", 8), ("k", 1)]) for _ in range(4)]
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for i, comb in enumerate(combinations(char, 3)):
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self.sync += [
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If(self.sink.stb,
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If((~buffer.stb | buffer.ack),
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voters[i].data.eq(reduce(and_, [code[0] for code in comb])),
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voters[i].k.eq(reduce(and_, [code[1] for code in comb])),
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)
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@ -338,15 +337,16 @@ class Duplicated_Char_Decoder(Module):
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# cycle 2 - inject the voting result
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self.sync += [
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self.buffer.ack.eq(self.source.ack),
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self.source.stb.eq(self.buffer.stb),
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If(self.buffer.stb,
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self.source.data.eq(self.buffer.data),
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self.source.k.eq(self.buffer.k),
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If((~self.source.stb | self.source.ack),
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self.source.stb.eq(buffer.stb),
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self.source.data.eq(buffer.data),
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self.source.k.eq(buffer.k),
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self.source.dchar.eq(Replicate(reduce(or_, [v.data for v in voters]), 4)),
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self.source.dchar_k.eq(Replicate(reduce(or_, [v.k for v in voters]), 4)),
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),
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)
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]
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self.comb += buffer.ack.eq(~self.source.stb | self.source.ack)
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@FullMemoryWE()
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class RX_Bootstrap(Module):
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@ -523,34 +523,3 @@ class Trigger_Ack_Checker(Module, AutoCSR):
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)
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)
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)
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@ResetInserter()
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@CEInserter()
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class CXPCRC32(Module):
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# Section 9.2.2.2 (CXP-001-2021)
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width = 32
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polynom = 0x04C11DB7
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seed = 2**width-1
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check = 0x00000000
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def __init__(self, data_width):
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self.data = Signal(data_width)
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self.value = Signal(self.width)
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self.error = Signal()
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# # #
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self.submodules.engine = LiteEthMACCRCEngine(data_width, self.width, self.polynom)
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reg = Signal(self.width, reset=self.seed)
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self.sync += reg.eq(self.engine.next)
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self.comb += [
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self.engine.data.eq(self.data),
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self.engine.last.eq(reg),
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self.value.eq(reg[::-1]),
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self.error.eq(self.engine.next != self.check)
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]
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# For verifying crc in stream data packet
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class CXPCRC32Checker(LiteEthMACCRCChecker):
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def __init__(self, layout):
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LiteEthMACCRCChecker.__init__(self, CXPCRC32, layout)
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