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cxp downconn: add interface for buildin aligner

This commit is contained in:
morgan 2024-07-26 12:04:33 +08:00
parent 20e388d043
commit faef1d2dff
1 changed files with 55 additions and 17 deletions
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64
src/gateware/cxp.py
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@ -11,8 +11,8 @@ class CXP(Module, AutoCSR):
def __init__(self, refclk, pads, sys_clk_freq, debug_sma, pmod_pads):
nchannels = len(pads)
self.rx_start_init = CSRStorage()
self.rx_restart = CSRStatus()
self.rx_bypass_clk_alignment = CSRStorage()
self.rx_restart = CSRStorage()
self.rx_data_alignment = CSRStorage()
self.tx_start_init = CSRStorage()
self.tx_restart = CSRStorage()
@ -25,8 +25,20 @@ class CXP(Module, AutoCSR):
self.data_0 = CSRStorage(8)
self.data_1 = CSRStorage(8)
self.data_2 = CSRStorage(8)
self.data_3 = CSRStorage(8)
self.data_4 = CSRStorage(8)
self.data_5 = CSRStorage(8)
self.data_6 = CSRStorage(8)
self.data_7 = CSRStorage(8)
self.control_bit_0 = CSRStorage()
self.control_bit_1 = CSRStorage()
self.control_bit_2 = CSRStorage()
self.control_bit_3 = CSRStorage()
self.control_bit_4 = CSRStorage()
self.control_bit_5 = CSRStorage()
self.control_bit_6 = CSRStorage()
self.control_bit_7 = CSRStorage()
self.encoded_0 = CSRStatus(10)
self.encoded_1 = CSRStatus(10)
@ -55,25 +67,50 @@ class CXP(Module, AutoCSR):
# DEBUG:loopback
self.sync += gtx.loopback_mode.eq(self.loopback_mode.storage)
# # ! debug sma
# self.specials += [
# Instance("OBUF", i_I=gtx.rxoutclk, o_O=debug_sma.p_tx),
# Instance("OBUF", i_I=gtx.cd_cxp_gtx_tx.clk, o_O=debug_sma.n_rx)
# ]
# DEBUG:SMA
self.specials += [
Instance("OBUF", i_I=gtx.rxoutclk, o_O=debug_sma.p_tx),
Instance("OBUF", i_I=gtx.cd_cxp_gtx_tx.clk, o_O=debug_sma.n_rx)
]
self.comb += [
self.txinit_phaligndone.status.eq(self.gtx.tx_init.Xxphaligndone),
self.rxinit_phaligndone.status.eq(self.gtx.rx_init.Xxphaligndone),
# self.rxinit_phaligndone.status.eq(self.gtx.rx_init.Xxphaligndone),
self.rx_ready.status.eq(self.gtx.rx_ready),
]
counter_max = 4
counter = Signal(max=counter_max)
self.sync.cxp_gtx_tx += [
If(counter == 0,
self.gtx.encoder.d[0].eq(self.data_0.storage),
self.gtx.encoder.k[0].eq(self.control_bit_0.storage),
self.encoded_0.status.eq(self.gtx.encoder.output[0]),
self.gtx.encoder.d[1].eq(self.data_1.storage),
self.gtx.encoder.k[1].eq(self.control_bit_1.storage),
counter.eq(counter+1),
).Elif(counter == 1,
self.gtx.encoder.d[0].eq(self.data_2.storage),
self.gtx.encoder.k[0].eq(self.control_bit_2.storage),
self.gtx.encoder.d[1].eq(self.data_3.storage),
self.gtx.encoder.k[1].eq(self.control_bit_3.storage),
counter.eq(0),
),
# ).Elif(counter == 2,
# self.gtx.encoder.d[0].eq(self.data_4.storage),
# self.gtx.encoder.k[0].eq(self.control_bit_4.storage),
# self.gtx.encoder.d[1].eq(self.data_5.storage),
# self.gtx.encoder.k[1].eq(self.control_bit_5.storage),
# counter.eq(counter+1),
# ).Elif(counter == 3,
# self.gtx.encoder.d[0].eq(self.data_6.storage),
# self.gtx.encoder.k[0].eq(self.control_bit_6.storage),
# self.gtx.encoder.d[1].eq(self.data_7.storage),
# self.gtx.encoder.k[1].eq(self.control_bit_7.storage),
# counter.eq(0),
# ),
self.encoded_0.status.eq(self.gtx.encoder.output[0]),
self.encoded_1.status.eq(self.gtx.encoder.output[1]),
]
self.sync.cxp_gtx_rx += [
@ -113,11 +150,12 @@ class CXP(Module, AutoCSR):
self.comb += [
gtx.rx_init.clk_path_ready.eq(self.rx_start_init.storage),
gtx.tx_init.clk_path_ready.eq(self.tx_start_init.storage),
gtx.txenable.eq(self.txenable.storage[0]),
gtx.tx_restart.eq(self.tx_restart.storage),
gtx.rx_restart.eq(self.rx_restart.storage),
gtx.tx_init.clk_path_ready.eq(self.tx_start_init.storage),
gtx.rx_init.clk_path_ready.eq(self.rx_start_init.storage),
gtx.rx_alignment_en.eq(self.rx_data_alignment.storage),
]
# TODO: Connect multilane cxp_tx