forked from M-Labs/artiq-zynq
cxp downconn: add interface for buildin aligner
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20e388d043
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faef1d2dff
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@ -11,8 +11,8 @@ class CXP(Module, AutoCSR):
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def __init__(self, refclk, pads, sys_clk_freq, debug_sma, pmod_pads):
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def __init__(self, refclk, pads, sys_clk_freq, debug_sma, pmod_pads):
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nchannels = len(pads)
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nchannels = len(pads)
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self.rx_start_init = CSRStorage()
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self.rx_start_init = CSRStorage()
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self.rx_restart = CSRStatus()
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self.rx_restart = CSRStorage()
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self.rx_bypass_clk_alignment = CSRStorage()
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self.rx_data_alignment = CSRStorage()
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self.tx_start_init = CSRStorage()
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self.tx_start_init = CSRStorage()
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self.tx_restart = CSRStorage()
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self.tx_restart = CSRStorage()
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@ -25,8 +25,20 @@ class CXP(Module, AutoCSR):
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self.data_0 = CSRStorage(8)
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self.data_0 = CSRStorage(8)
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self.data_1 = CSRStorage(8)
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self.data_1 = CSRStorage(8)
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self.data_2 = CSRStorage(8)
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self.data_3 = CSRStorage(8)
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self.data_4 = CSRStorage(8)
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self.data_5 = CSRStorage(8)
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self.data_6 = CSRStorage(8)
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self.data_7 = CSRStorage(8)
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self.control_bit_0 = CSRStorage()
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self.control_bit_0 = CSRStorage()
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self.control_bit_1 = CSRStorage()
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self.control_bit_1 = CSRStorage()
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self.control_bit_2 = CSRStorage()
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self.control_bit_3 = CSRStorage()
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self.control_bit_4 = CSRStorage()
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self.control_bit_5 = CSRStorage()
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self.control_bit_6 = CSRStorage()
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self.control_bit_7 = CSRStorage()
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self.encoded_0 = CSRStatus(10)
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self.encoded_0 = CSRStatus(10)
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self.encoded_1 = CSRStatus(10)
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self.encoded_1 = CSRStatus(10)
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@ -55,25 +67,50 @@ class CXP(Module, AutoCSR):
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# DEBUG:loopback
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# DEBUG:loopback
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self.sync += gtx.loopback_mode.eq(self.loopback_mode.storage)
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self.sync += gtx.loopback_mode.eq(self.loopback_mode.storage)
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# # ! debug sma
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# DEBUG:SMA
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# self.specials += [
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self.specials += [
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# Instance("OBUF", i_I=gtx.rxoutclk, o_O=debug_sma.p_tx),
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Instance("OBUF", i_I=gtx.rxoutclk, o_O=debug_sma.p_tx),
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# Instance("OBUF", i_I=gtx.cd_cxp_gtx_tx.clk, o_O=debug_sma.n_rx)
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Instance("OBUF", i_I=gtx.cd_cxp_gtx_tx.clk, o_O=debug_sma.n_rx)
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# ]
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]
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self.comb += [
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self.comb += [
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self.txinit_phaligndone.status.eq(self.gtx.tx_init.Xxphaligndone),
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self.txinit_phaligndone.status.eq(self.gtx.tx_init.Xxphaligndone),
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self.rxinit_phaligndone.status.eq(self.gtx.rx_init.Xxphaligndone),
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# self.rxinit_phaligndone.status.eq(self.gtx.rx_init.Xxphaligndone),
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self.rx_ready.status.eq(self.gtx.rx_ready),
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self.rx_ready.status.eq(self.gtx.rx_ready),
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]
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]
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self.sync.cxp_gtx_tx += [
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self.gtx.encoder.d[0].eq(self.data_0.storage),
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self.gtx.encoder.k[0].eq(self.control_bit_0.storage),
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self.encoded_0.status.eq(self.gtx.encoder.output[0]),
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self.gtx.encoder.d[1].eq(self.data_1.storage),
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counter_max = 4
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self.gtx.encoder.k[1].eq(self.control_bit_1.storage),
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counter = Signal(max=counter_max)
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self.sync.cxp_gtx_tx += [
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If(counter == 0,
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self.gtx.encoder.d[0].eq(self.data_0.storage),
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self.gtx.encoder.k[0].eq(self.control_bit_0.storage),
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self.gtx.encoder.d[1].eq(self.data_1.storage),
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self.gtx.encoder.k[1].eq(self.control_bit_1.storage),
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counter.eq(counter+1),
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).Elif(counter == 1,
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self.gtx.encoder.d[0].eq(self.data_2.storage),
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self.gtx.encoder.k[0].eq(self.control_bit_2.storage),
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self.gtx.encoder.d[1].eq(self.data_3.storage),
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self.gtx.encoder.k[1].eq(self.control_bit_3.storage),
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counter.eq(0),
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),
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# ).Elif(counter == 2,
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# self.gtx.encoder.d[0].eq(self.data_4.storage),
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# self.gtx.encoder.k[0].eq(self.control_bit_4.storage),
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# self.gtx.encoder.d[1].eq(self.data_5.storage),
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# self.gtx.encoder.k[1].eq(self.control_bit_5.storage),
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# counter.eq(counter+1),
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# ).Elif(counter == 3,
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# self.gtx.encoder.d[0].eq(self.data_6.storage),
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# self.gtx.encoder.k[0].eq(self.control_bit_6.storage),
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# self.gtx.encoder.d[1].eq(self.data_7.storage),
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# self.gtx.encoder.k[1].eq(self.control_bit_7.storage),
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# counter.eq(0),
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# ),
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self.encoded_0.status.eq(self.gtx.encoder.output[0]),
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self.encoded_1.status.eq(self.gtx.encoder.output[1]),
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self.encoded_1.status.eq(self.gtx.encoder.output[1]),
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]
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]
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self.sync.cxp_gtx_rx += [
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self.sync.cxp_gtx_rx += [
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@ -113,11 +150,12 @@ class CXP(Module, AutoCSR):
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self.comb += [
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self.comb += [
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gtx.rx_init.clk_path_ready.eq(self.rx_start_init.storage),
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gtx.tx_init.clk_path_ready.eq(self.tx_start_init.storage),
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gtx.txenable.eq(self.txenable.storage[0]),
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gtx.txenable.eq(self.txenable.storage[0]),
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gtx.tx_restart.eq(self.tx_restart.storage),
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gtx.tx_restart.eq(self.tx_restart.storage),
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gtx.rx_restart.eq(self.rx_restart.storage),
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gtx.tx_init.clk_path_ready.eq(self.tx_start_init.storage),
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gtx.rx_init.clk_path_ready.eq(self.rx_start_init.storage),
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gtx.rx_alignment_en.eq(self.rx_data_alignment.storage),
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]
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]
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# TODO: Connect multilane cxp_tx
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# TODO: Connect multilane cxp_tx
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