diff --git a/src/gateware/cxp_upconn.py b/src/gateware/cxp_upconn.py
index d788be4..44ca0c1 100644
--- a/src/gateware/cxp_upconn.py
+++ b/src/gateware/cxp_upconn.py
@@ -95,7 +95,7 @@ class SERDES_10bits(Module):
 @ResetInserter()
 @CEInserter()
 class Packets_Scheduler(Module):
-    def __init__(self, tx_fifos, debug_buf):
+    def __init__(self, interface, debug_buf):
         self.tx_enable = Signal()
 
         self.oe = Signal()
@@ -109,7 +109,7 @@ class Packets_Scheduler(Module):
         tx_wordcount = Signal(max=10000)
 
         idling = Signal()
-        priorities = Signal.like(tx_fifos.pe.o)
+        priorities = Signal.like(interface.pe.o)
 
         # DEBUG:
         self.idling = Signal()
@@ -146,17 +146,17 @@ class Packets_Scheduler(Module):
         self.sync += [
             If(self.oe,
                 encoder.disp_in.eq(encoder.disp_out),
-                If((~tx_fifos.pe.n) & (tx_fifos.pe.o == 0),
+                If((~interface.pe.n) & (interface.pe.o == 0),
                     # trigger packets are inserted at char boundary and don't contribute to word count
-                    tx_fifos.source_ack[0].eq(1),
-                    encoder.d.eq(tx_fifos.source_data[0]),
-                    encoder.k.eq(tx_fifos.source_k[0]),
+                    interface.sink_ack[0].eq(1),
+                    encoder.d.eq(interface.sink_data[0]),
+                    encoder.k.eq(interface.sink_k[0]),
 
                     # DEBUG:
                     If(debug_buf.sink_ack,
                         debug_buf.sink_stb.eq(1),
-                        debug_buf.sink_data.eq(tx_fifos.source_data[0]),
-                        debug_buf.sink_k.eq(tx_fifos.source_k[0]),
+                        debug_buf.sink_data.eq(interface.sink_data[0]),
+                        debug_buf.sink_k.eq(interface.sink_k[0]),
                     )
                 ).Else(
                     If(tx_charcount == 3,
@@ -164,20 +164,20 @@ class Packets_Scheduler(Module):
 
                         # Section 9.2.4 (CXP-001-2021)
                         # other priorities packets are inserted at word boundary
-                        If((~tx_fifos.pe.n) & (tx_wordcount != 9999),
+                        If((~interface.pe.n) & (tx_wordcount != 9999),
                             idling.eq(0),
-                            priorities.eq(tx_fifos.pe.o),
+                            priorities.eq(interface.pe.o),
                             tx_wordcount.eq(tx_wordcount + 1),
 
-                            tx_fifos.source_ack[tx_fifos.pe.o].eq(1),
-                            encoder.d.eq(tx_fifos.source_data[tx_fifos.pe.o]),
-                            encoder.k.eq(tx_fifos.source_k[tx_fifos.pe.o]),
+                            interface.sink_ack[interface.pe.o].eq(1),
+                            encoder.d.eq(interface.sink_data[interface.pe.o]),
+                            encoder.k.eq(interface.sink_k[interface.pe.o]),
 
                             # DEBUG:
                             If(debug_buf.sink_ack,
                                 debug_buf.sink_stb.eq(1),
-                                debug_buf.sink_data.eq(tx_fifos.source_data[tx_fifos.pe.o]),
-                                debug_buf.sink_k.eq(tx_fifos.source_k[tx_fifos.pe.o]),
+                                debug_buf.sink_data.eq(interface.sink_data[interface.pe.o]),
+                                debug_buf.sink_k.eq(interface.sink_k[interface.pe.o]),
                             )
                         ).Else(
                             # Section 9.2.5.1 (CXP-001-2021)
@@ -198,15 +198,15 @@ class Packets_Scheduler(Module):
                     ).Else(
                         tx_charcount.eq(tx_charcount + 1),
                         If(~idling,
-                            tx_fifos.source_ack[priorities].eq(1),
-                            encoder.d.eq(tx_fifos.source_data[priorities]),
-                            encoder.k.eq(tx_fifos.source_k[priorities]),
+                            interface.sink_ack[priorities].eq(1),
+                            encoder.d.eq(interface.sink_data[priorities]),
+                            encoder.k.eq(interface.sink_k[priorities]),
 
                             # DEBUG:
                             If(debug_buf.sink_ack,
                                 debug_buf.sink_stb.eq(1),
-                                debug_buf.sink_data.eq(tx_fifos.source_data[priorities]),
-                                debug_buf.sink_k.eq(tx_fifos.source_k[priorities]),
+                                debug_buf.sink_data.eq(interface.sink_data[priorities]),
+                                debug_buf.sink_k.eq(interface.sink_k[priorities]),
                             )
                         ).Else(
                             encoder.d.eq(IDLE_CHARS[tx_charcount + 1][0]),
@@ -227,10 +227,10 @@ class Packets_Scheduler(Module):
 class PHY_Interface(Module):
     def __init__(self, layout, nsink):
 
-        self.source_stb = Signal(nsink)
-        self.source_ack = Array(Signal() for _ in range(nsink))
-        self.source_data = Array(Signal(8) for _ in range(nsink))
-        self.source_k = Array(Signal() for _ in range(nsink))
+        self.sink_stb = Signal(nsink)
+        self.sink_ack = Array(Signal() for _ in range(nsink))
+        self.sink_data = Array(Signal(8) for _ in range(nsink))
+        self.sink_k = Array(Signal() for _ in range(nsink))
 
         # # #
 
@@ -240,23 +240,23 @@ class PHY_Interface(Module):
             self.sinks += [sink]
 
             self.sync += [
-                If(self.source_ack[i], 
+                If(self.sink_ack[i], 
                     # reset ack after asserted 
                     # since upconn clk run much slower, the ack will be high for longer than expected which will result in data loss
-                    self.source_ack[i].eq(0),
+                    self.sink_ack[i].eq(0),
                     sink.ack.eq(1),
                 ).Else(
                     sink.ack.eq(0),
                 ),
 
-                self.source_stb[i].eq(sink.stb),
-                self.source_data[i].eq(sink.data),
-                self.source_k[i].eq(sink.k),
+                self.sink_stb[i].eq(sink.stb),
+                self.sink_data[i].eq(sink.data),
+                self.sink_k[i].eq(sink.k),
             ]
 
         # FIFOs transmission priority
         self.submodules.pe = PriorityEncoder(nsink)
-        self.comb += self.pe.i.eq(self.source_stb)
+        self.comb += self.pe.i.eq(self.sink_stb)
 
 class Debug_buffer(Module,AutoCSR):
     def __init__(self, layout):
@@ -322,7 +322,7 @@ class CXP_UpConn_PHY(Module, AutoCSR):
         self.submodules.serdes = serdes = SERDES_10bits(pad)
 
         self.comb += [
-            self.tx_busy.eq(interface.source_stb != 0),
+            self.tx_busy.eq(interface.sink_stb != 0),
 
             cg.reset.eq(self.clk_reset),
             cg.freq2x_enable.eq(self.bitrate2x_enable),