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cxp GW: add ring buffer interface

This commit is contained in:
morgan 2024-10-07 13:15:27 +08:00
parent 24a1f27705
commit f9da1dddf9
1 changed files with 12 additions and 13 deletions
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25
src/gateware/cxp.py
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@ -213,20 +213,14 @@ class DownConn_Interface(Module, AutoCSR):
self.decoder_error = CSR()
self.test_error = CSR()
self.submodules.new_packet_ps = new_packet_ps = PulseSynchronizer("cxp_gtx_rx", "sys")
self.submodules.decode_err_ps = decode_err_ps = PulseSynchronizer("cxp_gtx_rx", "sys")
self.submodules.test_err_ps = test_err_ps = PulseSynchronizer("cxp_gtx_rx", "sys")
decode_err_ps = PulseSynchronizer("cxp_gtx_rx", "sys")
test_err_ps = PulseSynchronizer("cxp_gtx_rx", "sys")
self.submodules += decode_err_ps, test_err_ps
self.comb += [
new_packet_ps.i.eq(packet_decoder.new_packet),
decode_err_ps.i.eq(packet_decoder.decode_err),
test_err_ps.i.eq(packet_decoder.test_err),
]
self.sync += [
If(new_packet_ps.o,
self.new_rx_packet.w.eq(1),
).Elif(self.new_rx_packet.re,
self.new_rx_packet.w.eq(0),
),
If(decode_err_ps.o,
self.decoder_error.w.eq(1),
).Elif(self.decoder_error.re,
@ -242,13 +236,18 @@ class DownConn_Interface(Module, AutoCSR):
# Cicular buffer interface
self.packet_type = CSRStatus(8)
self.write_pointer = CSRStatus(bits_for(buffer_depth)) # for firmware to sync with buffer
self.pending_packet = CSR()
self.read_ptr = CSRStatus(log2_int(buffer_count))
self.specials += [
MultiReg(packet_decoder.packet_type, self.packet_type.status),
MultiReg(packet_decoder.write_ptr, self.write_pointer.status),
self.specials += MultiReg(packet_decoder.packet_type, self.packet_type.status),
self.sync += [
self.pending_packet.w.eq(self.read_ptr.status != packet_decoder.write_ptr_sys),
If(self.pending_packet.re & self.pending_packet.w,
self.read_ptr.status.eq(self.read_ptr.status + 1),
)
]
# DEBUG: remove this cdc fifo
cdc_fifo = stream.AsyncFIFO(word_layout, 512)
self.submodules += ClockDomainsRenamer({"write": "cxp_gtx_rx", "read": "sys"})(cdc_fifo)