From f8a2920033cd71b8302aea6ffe0a55e8a4de1590 Mon Sep 17 00:00:00 2001
From: morgan <mc@m-labs.hk>
Date: Tue, 23 Jul 2024 16:40:17 +0800
Subject: [PATCH] cxp upconn firmware: init

---
 src/libboard_artiq/src/cxp_upconn.rs | 88 ++++++++++++++++++++++++++++
 src/libboard_artiq/src/lib.rs        |  2 +
 2 files changed, 90 insertions(+)
 create mode 100644 src/libboard_artiq/src/cxp_upconn.rs

diff --git a/src/libboard_artiq/src/cxp_upconn.rs b/src/libboard_artiq/src/cxp_upconn.rs
new file mode 100644
index 0000000..06f8be3
--- /dev/null
+++ b/src/libboard_artiq/src/cxp_upconn.rs
@@ -0,0 +1,88 @@
+use embedded_hal::prelude::_embedded_hal_blocking_delay_DelayUs;
+use libboard_zynq::{println, timer::GlobalTimer};
+
+use crate::pl::csr;
+
+pub fn crc_test() {
+    let arr = [
+        0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, // CXP CRC-32
+        0x56, 0x86, 0x5D, 0x6f,
+    ];
+    let mut crc: u32; // seed = 0xFFFFFFFF
+
+    unsafe {
+        csr::cxp::crc_en_write(1);
+
+        for a in arr.iter() {
+            csr::cxp::crc_data_write(*a);
+            crc = csr::cxp::crc_value_read();
+            println!("input = {:#04x}", *a);
+            println!("CRC NOT(val.reverse) = {:#010x}", !crc.reverse_bits());
+            // since the input bit are reversed when entering the crc engine, the output char need to be reversed to cancel out on the receiver side
+            println!("CRC CXP = {:#010x}", crc);
+        }
+    }
+}
+
+pub fn tx_test(timer: &mut GlobalTimer) {
+    // the 8bit shift is k symbol
+    // const K28_1: u16 = 0x3C | (1 << 8);
+    // const K28_5: u16 = 0xBC | (1 << 8);
+    const D31_1: u16 = 0x3F;
+    const D01_1: u16 = 0x21;
+
+    const LEN: usize = 100;
+    let mut arr: [u16; LEN] = [0; LEN];
+
+    unsafe {
+        csr::cxp::upconn_clk_reset_write(1);
+        // csr::cxp::upconn_bitrate2x_enable_write(1);
+        csr::cxp::upconn_clk_reset_write(0);
+        loop {
+            // TODO: verify the char & word boundary thingy
+            for _ in 0..8 {
+                csr::cxp::upconn_symbol1_write(D01_1);
+            }
+
+            for _ in 0..4 {
+                csr::cxp::upconn_symbol2_write(D31_1);
+            }
+
+            timer.delay_us(1);
+            csr::cxp::upconn_tx_enable_write(1);
+
+            for i in 0..LEN {
+                arr[i] = get_encoded();
+            }
+            for i in 0..LEN {
+                match arr[i] {
+                    0b1010111001 | 0b0101001001 => {
+                        println!("encoded = {:#012b} D31.1", arr[i])
+                    }
+                    0b0111011001 | 0b1000101001 => {
+                        println!("encoded = {:#012b} D01.1", arr[i])
+                    }
+                    0b0011111010 | 0b1100000101 => {
+                        println!("encoded = {:#012b} K28.5 start idling....", arr[i])
+                    }
+                    0b0011111001 | 0b1100000110 => {
+                        println!("encoded = {:#012b} K28.1 idling...", arr[i])
+                    }
+                    0b0011101010 => {
+                        println!("encoded = {:#012b} D28.5 END idle", arr[i])
+                    }
+                    _ => {
+                        println!("encoded = {:#012b}", arr[i])
+                    }
+                }
+            }
+            println!("-------------------------------------");
+
+            csr::cxp::upconn_tx_enable_write(0);
+            timer.delay_us(2_000_000);
+        }
+    }
+    fn get_encoded() -> u16 {
+        unsafe { csr::cxp::upconn_encoded_data_read().reverse_bits() >> 6 }
+    }
+}
diff --git a/src/libboard_artiq/src/lib.rs b/src/libboard_artiq/src/lib.rs
index 70c4cb6..008c2aa 100644
--- a/src/libboard_artiq/src/lib.rs
+++ b/src/libboard_artiq/src/lib.rs
@@ -42,6 +42,8 @@ pub mod si5324;
 pub mod si549;
 use core::{cmp, str};
 
+#[cfg(has_cxp)]
+pub mod cxp_upconn;
 pub fn identifier_read(buf: &mut [u8]) -> &str {
     unsafe {
         pl::csr::identifier::address_write(0);