forked from M-Labs/artiq-zynq
cxp: cleanup
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@ -179,7 +179,6 @@ class TX_Trigger(Module, AutoCSR):
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self.submodules.buf_out = buf_out = stream.SyncFIFO(layout, 64)
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tx_pipeline = [ code_src, inserter_twice, inserter_once, buf_out]
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# tx_pipeline = [ code_src, inserter_twice, buf_out]
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for s, d in zip(tx_pipeline, tx_pipeline[1:]):
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self.comb += s.source.connect(d.sink)
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