forked from M-Labs/artiq-zynq
cxp upconn fw: add packet writer & packet types
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d77086e733
commit
f49f3dbb55
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@ -1,4 +1,6 @@
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use core_io::{Error as IoError, Read, Write};
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use embedded_hal::prelude::_embedded_hal_blocking_delay_DelayUs;
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use embedded_hal::prelude::_embedded_hal_blocking_delay_DelayUs;
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use io::Cursor;
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use libboard_zynq::{println, timer::GlobalTimer};
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use libboard_zynq::{println, timer::GlobalTimer};
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use crate::pl::csr;
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use crate::pl::csr;
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@ -46,38 +48,6 @@ pub fn trigger_ack_test(timer: &mut GlobalTimer) {
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}
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}
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}
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}
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pub fn pipeline_test(timer: &mut GlobalTimer) {
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let arr = [
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// 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08
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0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00,
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// 0x56, 0x86, 0x5D, 0x6f, // CXP CRC-32
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];
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const LEN: usize = 4 * 8;
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let mut pak_arr: [u8; LEN] = [0; LEN];
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unsafe {
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write(0x02, &arr); // read control command
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// wait for pipelining
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timer.delay_us(1);
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let mut i: usize = 0;
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while csr::cxp::upconn_command_dout_valid_read() == 1 {
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pak_arr[i] = csr::cxp::upconn_command_dout_pak_read();
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// println!("received {:#04X}", pak_arr[i]);
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csr::cxp::upconn_command_inc_write(1);
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i += 1;
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if i == LEN {
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break;
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};
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}
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println!("data packet");
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print_packet(&pak_arr);
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}
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}
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pub fn tx_test(timer: &mut GlobalTimer) {
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pub fn tx_test(timer: &mut GlobalTimer) {
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const LEN: usize = 4 * 30;
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const LEN: usize = 4 * 30;
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let mut pak_arr: [u8; LEN] = [0; LEN];
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let mut pak_arr: [u8; LEN] = [0; LEN];
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@ -121,28 +91,150 @@ pub fn tx_test(timer: &mut GlobalTimer) {
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}
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}
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}
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}
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pub fn write(packet_type: u8, buf: &[u8]) {
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pub enum Packet {
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ControlWrite_u32_no_tag {
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addr: u32,
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data: u32,
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packet_type: u8,
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},
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ControlRead_u32_no_tag {
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addr: u32,
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packet_type: u8,
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},
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ControlWrite_u64_no_tag {
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addr: u32,
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data: u64,
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packet_type: u8,
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},
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ControlRead_u64_no_tag {
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addr: u32,
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packet_type: u8,
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},
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ControlWrite_u32_with_tag {
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addr: u32,
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data: u32,
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packet_type: u8,
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tag: u8,
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},
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ControlRead_u32_with_tag {
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addr: u32,
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packet_type: u8,
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tag: u8,
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},
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ControlWrite_u64_with_tag {
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addr: u32,
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data: u64,
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packet_type: u8,
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tag: u8,
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},
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ControlRead_u64_with_tag {
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addr: u32,
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packet_type: u8,
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tag: u8,
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},
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}
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impl Packet {
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pub fn write_to<W>(&self, writer: &mut W) -> Result<(), IoError>
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where W: Write {
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match *self {
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Packet::ControlWrite_u32_no_tag { addr, data, .. } => {
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writer.write(&[0x01, 0x00, 0x00, 0x04])?;
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writer.write(&addr.to_be_bytes())?;
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writer.write(&data.to_be_bytes())?;
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}
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Packet::ControlRead_u32_no_tag { addr, .. } => {
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writer.write(&[0x00, 0x00, 0x00, 0x04])?;
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writer.write(&addr.to_be_bytes())?;
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}
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_ => {
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// // TODO: placeholder for rust borrow checker
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// writer.write_u32(0x00)?;
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}
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}
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Ok(())
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}
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}
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pub fn send(packet: &Packet) -> Result<(), IoError> {
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const LEN: usize = 4 * 20;
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let mut buffer: [u8; LEN] = [0; LEN];
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let mut writer = Cursor::new(&mut buffer[..]);
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packet.write_to(&mut writer)?;
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// // Pad till offset 4, insert checksum there
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// let padding = (12 - (writer.position() % 8)) % 8;
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// for _ in 0..padding {
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// writer.write_u8(0)?;
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// }
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// let checksum = crc::crc32::checksum_ieee(&writer.get_ref()[0..writer.position()]);
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// writer.write_u32(checksum)?;
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// let mut res: [u8; LEN] = [0; LEN];
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// res.clone_from_slice(&mut write);
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unsafe {
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unsafe {
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// eop = 1 (End of packet) at the last data input
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let len = writer.position();
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csr::cxp::upconn_command_din_len_write(buf.len() as u8);
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csr::cxp::upconn_command_din_len_write(len as u8);
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match *packet {
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Packet::ControlWrite_u32_no_tag { packet_type, .. }
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| Packet::ControlRead_u32_no_tag { packet_type, .. } => {
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csr::cxp::upconn_command_packet_type_write(packet_type);
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csr::cxp::upconn_command_packet_type_write(packet_type);
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for data in buf.iter() {
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}
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_ => {
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println!("packet_type is not inserted!!!!");
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}
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}
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for data in writer.get_ref()[..len].iter() {
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while csr::cxp::upconn_command_din_ready_read() == 0 {}
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while csr::cxp::upconn_command_din_ready_read() == 0 {}
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csr::cxp::upconn_command_din_data_write(*data);
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csr::cxp::upconn_command_din_data_write(*data);
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println!("{:#04X}", *data);
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println!("{:#04X}", *data);
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}
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}
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}
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}
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Ok(())
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}
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}
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pub fn CXP_Control(timer: &mut GlobalTimer) {
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pub fn pipeline_test(timer: &mut GlobalTimer) {
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let addr: u32 = 0x0000_00FF;
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let address: u32 = 0x0000_00FF;
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let tag: u8 = 0x44;
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let tag: u8 = 0x44;
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let d0: u32 = 0x0000_0032;
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let d0: u32 = 0x0000_0032;
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let d1: u64 = 0x0000_0064;
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let d1: u64 = 0x0000_0064;
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// TODO: reference drtioaux_proto.rs
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// send(&Packet::ControlWrite_u32_no_tag {
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// addr: address,
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// data: d0,
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// packet_type: 0x02,
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// });
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// TODO: add firmware CRC & packet type
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// CXP CRC example
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send(&Packet::ControlRead_u32_no_tag {
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addr: 0x00,
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packet_type: 0x02,
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});
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unsafe {
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timer.delay_us(1);
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const LEN: usize = 4 * 8;
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let mut pak_arr: [u8; LEN] = [0; LEN];
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let mut i: usize = 0;
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while csr::cxp::upconn_command_dout_valid_read() == 1 {
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pak_arr[i] = csr::cxp::upconn_command_dout_pak_read();
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// println!("received {:#04X}", pak_arr[i]);
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csr::cxp::upconn_command_inc_write(1);
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i += 1;
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if i == LEN {
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break;
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};
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}
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println!("data packet");
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print_packet(&pak_arr);
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}
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}
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}
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fn print_packet(pak: &[u8]) {
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fn print_packet(pak: &[u8]) {
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