forked from M-Labs/artiq-zynq
cxp downconn: refactor to allow gtx extensions
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2dade34119
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f34f500ed8
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@ -26,6 +26,7 @@ class CXP_DownConn(Module, AutoCSR):
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self.qpll_reset = CSR()
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self.qpll_locked = CSRStatus()
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self.gtxs = []
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# # #
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self.submodules.qpll = qpll = QPLL(refclk, sys_clk_freq)
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@ -34,31 +35,25 @@ class CXP_DownConn(Module, AutoCSR):
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self.qpll_locked.status.eq(qpll.lock),
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]
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nconn = len(pads)
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for i in range(nconn):
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if i != 0:
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break
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gtx = GTX(self.qpll, pads[i], sys_clk_freq, tx_mode="single", rx_mode="single")
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self.gtxs.append(gtx)
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setattr(self.submodules, "gtx"+str(i), gtx)
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# TODO: add extension gtx connections
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# TODO: add connection interface
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# single & master tx_mode can lock with rx in loopback
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self.submodules.gtx = gtx = GTX(self.qpll, pads[0], sys_clk_freq, tx_mode="single", rx_mode="single")
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# NOTE: No need to connect cxp_gtx_tx, we don't use tx anyway (just for loopback)
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# TODO: Connect slave cxp_gtx_rx clock tgt
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# checkout channel interfaces & drtio_gtx
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# checkout GTPTXPhaseAlignement for inspiration
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# GTPTXPhaseAlignement for inspiration
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self.sync += [
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# GTX
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self.txinit_phaligndone.status.eq(gtx.tx_init.Xxphaligndone),
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self.rxinit_phaligndone.status.eq(gtx.rx_init.Xxphaligndone),
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self.rx_ready.status.eq(gtx.rx_ready),
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gtx.txenable.eq(self.txenable.storage[0]),
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gtx.tx_restart.eq(self.tx_restart.re),
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gtx.rx_restart.eq(self.rx_restart.re),
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gtx.tx_init.clk_path_ready.eq(self.tx_start_init.storage),
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gtx.rx_init.clk_path_ready.eq(self.rx_start_init.storage),
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]
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# GTX Channels DRP
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# Connect all GTX connections' DRP
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self.tx_div = CSRStorage(3)
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self.rx_div = CSRStorage(3)
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@ -70,6 +65,19 @@ class CXP_DownConn(Module, AutoCSR):
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self.gtx_dout = CSRStatus(16)
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self.gtx_dready = CSR()
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for gtx in self.gtxs:
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self.sync += [
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self.txinit_phaligndone.status.eq(gtx.tx_init.Xxphaligndone),
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self.rxinit_phaligndone.status.eq(gtx.rx_init.Xxphaligndone),
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self.rx_ready.status.eq(gtx.rx_ready),
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gtx.txenable.eq(self.txenable.storage[0]),
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gtx.tx_restart.eq(self.tx_restart.re),
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gtx.rx_restart.eq(self.rx_restart.re),
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gtx.tx_init.clk_path_ready.eq(self.tx_start_init.storage),
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gtx.rx_init.clk_path_ready.eq(self.rx_start_init.storage),
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]
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self.comb += gtx.dclk.eq(ClockSignal("sys"))
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self.sync += [
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gtx.tx_rate.eq(self.tx_div.storage),
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@ -95,6 +103,9 @@ class CXP_DownConn(Module, AutoCSR):
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),
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]
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# DEBUG: txusrclk PLL DRG
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self.txpll_reset = CSRStorage()
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@ -108,6 +119,7 @@ class CXP_DownConn(Module, AutoCSR):
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self.pll_dout = CSRStatus(16)
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self.pll_dready = CSRStatus()
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for n, gtx in enumerate(self.gtxs):
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self.comb += [
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gtx.txpll_reset.eq(self.txpll_reset.storage),
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gtx.pll_daddr.eq(self.pll_daddr.storage),
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@ -126,6 +138,7 @@ class CXP_DownConn(Module, AutoCSR):
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self.comb += gtx.loopback_mode.eq(self.loopback_mode.storage)
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# DEBUG: IO SMA & PMOD
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if n == 0:
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self.specials += [
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Instance("OBUF", i_I=gtx.cd_cxp_gtx_rx.clk, o_O=debug_sma.p_tx),
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Instance("OBUF", i_I=gtx.cd_cxp_gtx_tx.clk, o_O=debug_sma.n_rx),
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@ -150,14 +163,14 @@ class CXP_DownConn(Module, AutoCSR):
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self.sync.cxp_gtx_tx += [
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self.gtx.encoder.d[0].eq(0xBC),
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self.gtx.encoder.k[0].eq(1),
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self.gtx.encoder.d[1].eq(0x3C),
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self.gtx.encoder.k[1].eq(1),
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self.gtx.encoder.d[2].eq(0x3C),
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self.gtx.encoder.k[2].eq(1),
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self.gtx.encoder.d[3].eq(0xB5),
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self.gtx.encoder.k[3].eq(0),
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gtx.encoder.d[0].eq(0xBC),
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gtx.encoder.k[0].eq(1),
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gtx.encoder.d[1].eq(0x3C),
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gtx.encoder.k[1].eq(1),
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gtx.encoder.d[2].eq(0x3C),
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gtx.encoder.k[2].eq(1),
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gtx.encoder.d[3].eq(0xB5),
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gtx.encoder.k[3].eq(0),
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]
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self.rxdata_0 = CSRStatus(10)
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@ -174,21 +187,21 @@ class CXP_DownConn(Module, AutoCSR):
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self.decoded_k_3 = CSRStatus()
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self.sync.cxp_gtx_rx += [
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self.rxdata_0.status.eq(self.gtx.decoders[0].input),
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self.decoded_data_0.status.eq(self.gtx.decoders[0].d),
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self.decoded_k_0.status.eq(self.gtx.decoders[0].k),
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self.rxdata_0.status.eq(gtx.decoders[0].input),
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self.decoded_data_0.status.eq(gtx.decoders[0].d),
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self.decoded_k_0.status.eq(gtx.decoders[0].k),
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self.rxdata_1.status.eq(self.gtx.decoders[1].input),
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self.decoded_data_1.status.eq(self.gtx.decoders[1].d),
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self.decoded_k_1.status.eq(self.gtx.decoders[1].k),
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self.rxdata_1.status.eq(gtx.decoders[1].input),
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self.decoded_data_1.status.eq(gtx.decoders[1].d),
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self.decoded_k_1.status.eq(gtx.decoders[1].k),
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self.rxdata_2.status.eq(self.gtx.decoders[2].input),
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self.decoded_data_2.status.eq(self.gtx.decoders[2].d),
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self.decoded_k_2.status.eq(self.gtx.decoders[2].k),
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self.rxdata_2.status.eq(gtx.decoders[2].input),
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self.decoded_data_2.status.eq(gtx.decoders[2].d),
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self.decoded_k_2.status.eq(gtx.decoders[2].k),
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self.rxdata_3.status.eq(self.gtx.decoders[3].input),
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self.decoded_data_3.status.eq(self.gtx.decoders[3].d),
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self.decoded_k_3.status.eq(self.gtx.decoders[3].k),
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self.rxdata_3.status.eq(gtx.decoders[3].input),
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self.decoded_data_3.status.eq(gtx.decoders[3].d),
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self.decoded_k_3.status.eq(gtx.decoders[3].k),
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]
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