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cxp: cleanup

This commit is contained in:
morgan 2024-08-29 13:37:35 +08:00
parent 98bb49e1b5
commit f2d8ffbe05
1 changed files with 15 additions and 48 deletions
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63
src/gateware/cxp.py
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@ -75,67 +75,27 @@ class UpConn_Packets(Module, AutoCSR):
upconn.tx_fifos.sink_k[2].eq(self.symbol2.r[8]), upconn.tx_fifos.sink_k[2].eq(self.symbol2.r[8]),
] ]
# TODO: add a packet handler for firmware
# self.packet_type = CSRStorage(8)
# self.data = CSR(8)
# # CRC
# self.packet_start = CSR()
# self.submodules.packet_fsm = packet_fms = FSM(reset_state="IDLE")
# packet_fms.act("IDLE",
# upconn.tx_fifos.sink_stb[2].eq(0),
# If(self.packet_start.re,
# # TODO: load it 4 times
# upconn.tx_fifos.sink_stb[2].eq(1),
# upconn.tx_fifos.sink_data[2].eq(0xFB), # K27.7
# upconn.tx_fifos.sink_k[2].eq(1),
# NextState("LOAD_PACKET_TYPE"),
# )
# )
# packet_fms.act("LOAD_PACKET_TYPE",
# )
# packet_fms.act("LOAD_DATA",
# upconn.tx_fifos.sink_stb[2].eq(self.data.re),
# upconn.tx_fifos.sink_data[2].eq(self.data.r),
# upconn.tx_fifos.sink_k[2].eq(0),
# If()
# )
class CXP_Packet(Module): class CXP_Packet(Module):
def __init__(self, max_packet_length): def __init__(self, max_packet_length):
pass pass
class CXP_CRC(Module, AutoCSR): class CXP_CRC(Module, AutoCSR):
width = 32
polynom = 0x04C11DB7
seed = 2**width-1
def __init__(self, data_width): def __init__(self, data_width):
# Section 9.2.2.2 (CXP-001-2021)
crc_width = 32
polynom = 0x04C11DB7
seed = 2**crc_width-1
self.d = Signal(data_width) self.d = Signal(data_width)
self.stb = Signal() self.stb = Signal()
self.reset = Signal() self.reset = Signal()
self.val = Signal(self.width, reset=self.seed) self.val = Signal(crc_width, reset=seed)
self.data = CSR(data_width)
self.en = CSR()
self.value = CSRStatus(self.width)
self.processed = CSRStatus(self.width)
# # # # # #
self.submodules.engine = LiteEthMACCRCEngine(data_width, self.width, self.polynom) self.submodules.engine = LiteEthMACCRCEngine(data_width, crc_width, polynom)
self.sync += [ self.sync += [
self.val.eq(self.engine.next), self.val.eq(self.engine.next),
@ -143,7 +103,8 @@ class CXP_CRC(Module, AutoCSR):
self.engine.data.eq(self.d), self.engine.data.eq(self.d),
If(self.reset, If(self.reset,
self.engine.last.eq(self.seed), # because the seed is non zero, even if the data is 0x00, the engine output will be change :<
self.engine.last.eq(seed),
# clear reset bit # clear reset bit
self.reset.eq(0), self.reset.eq(0),
).Else( ).Else(
@ -165,6 +126,12 @@ class CXP_CRC(Module, AutoCSR):
p1.eq(self.engine.next[16:24][::-1]), p1.eq(self.engine.next[16:24][::-1]),
p0.eq(self.engine.next[24:32][::-1]), p0.eq(self.engine.next[24:32][::-1]),
] ]
self.data = CSR(data_width)
self.en = CSR()
self.value = CSRStatus(crc_width)
self.processed = CSRStatus(crc_width)
self.sync += [ self.sync += [
self.d.eq(self.data.r), self.d.eq(self.data.r),
self.stb.eq(self.data.re), self.stb.eq(self.data.re),