forked from M-Labs/artiq-zynq
cxp upconn fw: add rest of u32 u64 control packet
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168c75eaf6
commit
f2d7a67da3
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@ -1,4 +1,4 @@
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use core_io::{Error as IoError, Read, Write};
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use core_io::{Error as IoError, Write};
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use crc::crc32;
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use embedded_hal::prelude::_embedded_hal_blocking_delay_DelayUs;
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use io::Cursor;
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@ -92,73 +92,74 @@ pub fn tx_test(timer: &mut GlobalTimer) {
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}
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}
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pub enum Packet {
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ControlWrite_u32_no_tag {
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addr: u32,
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data: u32,
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packet_type: u8,
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},
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ControlRead_u32_no_tag {
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addr: u32,
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packet_type: u8,
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},
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ControlWrite_u64_no_tag {
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addr: u32,
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data: u64,
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packet_type: u8,
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},
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ControlRead_u64_no_tag {
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addr: u32,
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packet_type: u8,
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},
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pub enum Command<T> {
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ControlRead { addr: u32 },
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ControlWrite { addr: u32, data: T },
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ControlReadWithTag { addr: u32, tag: u8 },
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ControlWriteWithTag { addr: u32, data: T, tag: u8 },
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}
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ControlWrite_u32_with_tag {
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addr: u32,
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data: u32,
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packet_type: u8,
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tag: u8,
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},
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ControlRead_u32_with_tag {
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addr: u32,
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packet_type: u8,
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tag: u8,
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},
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ControlWrite_u64_with_tag {
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addr: u32,
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data: u64,
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packet_type: u8,
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tag: u8,
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},
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ControlRead_u64_with_tag {
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addr: u32,
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packet_type: u8,
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tag: u8,
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},
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pub enum Packet {
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ControlU32Reg(Command<u32>),
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ControlU64Reg(Command<u64>),
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}
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impl Packet {
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pub fn write_to<W>(&self, writer: &mut W) -> Result<(), IoError>
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where W: Write {
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match *self {
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Packet::ControlWrite_u32_no_tag {
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addr,
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data,
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packet_type,
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} => {
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writer.write(&[packet_type; 4])?;
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writer.write(&[0x01, 0x00, 0x00, 0x04])?;
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writer.write(&addr.to_be_bytes())?;
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writer.write(&data.to_be_bytes())?;
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}
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Packet::ControlRead_u32_no_tag { addr, packet_type } => {
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writer.write(&[packet_type; 4])?;
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writer.write(&[0x00, 0x00, 0x00, 0x04])?;
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writer.write(&addr.to_be_bytes())?;
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}
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_ => {
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// // TODO: placeholder for rust borrow checker
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// writer.write_u32(0x00)?;
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}
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match self {
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Packet::ControlU32Reg(cmd) => match cmd {
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Command::ControlRead { addr } => {
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writer.write(&[0x02; 4])?;
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writer.write(&[0x00, 0x00, 0x00, 0x04])?;
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writer.write(&addr.to_be_bytes())?;
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}
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Command::ControlWrite { addr, data } => {
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writer.write(&[0x02; 4])?;
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writer.write(&[0x01, 0x00, 0x00, 0x04])?;
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writer.write(&addr.to_be_bytes())?;
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writer.write(&data.to_be_bytes())?;
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}
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Command::ControlReadWithTag { addr, tag } => {
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writer.write(&[0x05; 4])?;
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writer.write(&[*tag; 4])?;
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writer.write(&[0x00, 0x00, 0x00, 0x04])?;
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writer.write(&addr.to_be_bytes())?;
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}
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Command::ControlWriteWithTag { addr, data, tag } => {
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writer.write(&[0x05; 4])?;
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writer.write(&[*tag; 4])?;
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writer.write(&[0x01, 0x00, 0x00, 0x04])?;
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writer.write(&addr.to_be_bytes())?;
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writer.write(&data.to_be_bytes())?;
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}
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},
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Packet::ControlU64Reg(cmd) => match cmd {
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Command::ControlRead { addr } => {
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writer.write(&[0x02; 4])?;
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writer.write(&[0x00, 0x00, 0x00, 0x08])?;
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writer.write(&addr.to_be_bytes())?;
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}
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Command::ControlWrite { addr, data } => {
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writer.write(&[0x02; 4])?;
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writer.write(&[0x01, 0x00, 0x00, 0x08])?;
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writer.write(&addr.to_be_bytes())?;
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writer.write(&data.to_be_bytes())?;
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}
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Command::ControlReadWithTag { addr, tag } => {
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writer.write(&[0x05; 4])?;
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writer.write(&[*tag; 4])?;
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writer.write(&[0x00, 0x00, 0x00, 0x08])?;
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writer.write(&addr.to_be_bytes())?;
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}
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Command::ControlWriteWithTag { addr, data, tag } => {
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writer.write(&[0x05; 4])?;
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writer.write(&[*tag; 4])?;
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writer.write(&[0x01, 0x00, 0x00, 0x08])?;
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writer.write(&addr.to_be_bytes())?;
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writer.write(&data.to_be_bytes())?;
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}
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},
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}
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Ok(())
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}
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@ -171,16 +172,9 @@ pub fn send(packet: &Packet) -> Result<(), IoError> {
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packet.write_to(&mut writer)?;
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// // Pad till offset 4, insert checksum there
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// let padding = (12 - (writer.position() % 8)) % 8;
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// for _ in 0..padding {
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// writer.write_u8(0)?;
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// }
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// Section 9.2.2.2 (CXP-001-2021)
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// CoaXpress use the polynomial of IEEE-802.3 (Ethernet) CRC but the checksum calculation is different
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// Also, the calculation does not include the first 4 bytes of packet_type
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let checksum = crc32::checksum_ieee(&writer.get_ref()[4..writer.position()]);
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writer.write(&(!checksum).to_le_bytes())?;
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@ -197,22 +191,8 @@ pub fn send(packet: &Packet) -> Result<(), IoError> {
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}
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pub fn pipeline_test(timer: &mut GlobalTimer) {
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let address: u32 = 0x0000_00FF;
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let tag: u8 = 0x44;
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let d0: u32 = 0x0000_0032;
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let d1: u64 = 0x0000_0064;
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// send(&Packet::ControlWrite_u32_no_tag {
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// addr: address,
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// data: d0,
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// packet_type: 0x02,
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// });
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// CXP CRC example
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send(&Packet::ControlRead_u32_no_tag {
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addr: 0x00,
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packet_type: 0x02,
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});
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send(&Packet::ControlU32Reg(Command::ControlRead { addr: 0x00 })).expect("Cannot send CoaXpress packet");
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unsafe {
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timer.delay_us(1);
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