From f23ce2ef70ef3d162fd49bb6ab992027f0c3f1fc Mon Sep 17 00:00:00 2001
From: morgan <mc@m-labs.hk>
Date: Fri, 30 Aug 2024 16:07:25 +0800
Subject: [PATCH] cxp pipeline: merge packet start & stop into 1 mod

---
 src/gateware/cxp_pipeline.py | 85 ++++++++++++------------------------
 1 file changed, 28 insertions(+), 57 deletions(-)

diff --git a/src/gateware/cxp_pipeline.py b/src/gateware/cxp_pipeline.py
index 6c8b841..1b2fa6c 100644
--- a/src/gateware/cxp_pipeline.py
+++ b/src/gateware/cxp_pipeline.py
@@ -3,22 +3,13 @@ from misoc.interconnect.csr import *
 from misoc.interconnect import stream
 from misoc.cores.liteeth_mini.mac.crc import LiteEthMACCRCEngine, LiteEthMACCRCInserter 
 
+def K(x, y):
+    return ((y << 5) | x)
+
 class Code_Inserter(Module):
-    """Code inserter
-
-    Inserts data in the front or end of each packet.
-
-    Attributes
-    ----------
-    sink : in
-        Packet octets.
-    source : out
-        Preamble, SFD, and packet octets.
-    """
-
-    def __init__(self, cxp_phy_layout, insert_infront=True, counts=4):
-        self.sink = sink = stream.Endpoint(cxp_phy_layout)
-        self.source = source = stream.Endpoint(cxp_phy_layout)
+    def __init__(self, layout, insert_infront=True, counts=4):
+        self.sink = sink = stream.Endpoint(layout)
+        self.source = source = stream.Endpoint(layout)
 
         self.data = Signal.like(sink.data)
         self.k = Signal.like(sink.k)
@@ -39,25 +30,25 @@ class Code_Inserter(Module):
 
         self.submodules.fsm = fsm = FSM(reset_state="IDLE")
 
-
         if insert_infront:
             fsm.act("IDLE",
-                sink.ack.eq(1), # = writable/not full
+                sink.ack.eq(1),
                 clr_cnt.eq(1),
-                If(sink.stb, # = data input
-                    sink.ack.eq(0), # = full
+                If(sink.stb,
+                    sink.ack.eq(0),
                     NextState("INSERT"),
                 )
             )
 
             fsm.act("INSERT",
-                source.stb.eq(1), # = writing data now
+                sink.ack.eq(0),
+                source.stb.eq(1),
                 source.data.eq(self.data),
                 source.k.eq(self.k),
                 If(cnt == counts - 1,
                     If(source.ack, NextState("COPY"))
                 ).Else(
-                    inc_cnt.eq(source.ack)# = inc_counter only when next pipeline is ready to accept new data
+                    inc_cnt.eq(source.ack)
                 )
             )
 
@@ -90,60 +81,40 @@ class Code_Inserter(Module):
             )
 
             fsm.act("INSERT",
-                source.stb.eq(1), # = writing data now
+                sink.ack.eq(0),
+                source.stb.eq(1),
                 source.data.eq(self.data),
                 source.k.eq(self.k),
                 If(cnt == counts - 1,
                     source.eop.eq(1),
                     If(source.ack, NextState("IDLE"))
                 ).Else(
-                    inc_cnt.eq(source.ack) # = inc_counter only when next pipeline is ready to accept new data
+                    inc_cnt.eq(source.ack)
                 ),
             )
 
-def K(x, y):
-    return ((y << 5) | x)
 
-def D(x, y):
-    return ((y << 5) | x)
-
-class Packet_Start_Inserter(Code_Inserter):
+class Packet_Wrapper(Module):
     def __init__(self, layout):
-        Code_Inserter.__init__(self, layout)
-        self.comb += [
-            self.data.eq(K(27, 7)),
-            self.k.eq(1),
-        ]
+        self.submodules.pak_start = pak_start = Code_Inserter(layout) 
+        self.submodules.pak_end = pak_end = Code_Inserter(layout, insert_infront=False) 
+
+        self.sink = pak_start.sink
+        self.source = pak_end.source
 
-class Packet_End_Inserter(Code_Inserter):
-    def __init__(self, layout):
-        Code_Inserter.__init__(self, layout, insert_infront=False)
         self.comb += [
-            self.data.eq(K(29, 7)),
-            self.k.eq(1),
+            pak_start.data.eq(K(27, 7)),
+            pak_start.k.eq(1),
+            pak_end.data.eq(K(29, 7)),
+            pak_end.k.eq(1),
+
+            pak_start.source.connect(pak_end.sink),
         ]
+        
 
 @ResetInserter()
 @CEInserter()
 class CXPCRC32(Module):
-    """CoaXPress CRC
-
-    Implement an CoaXPress CRC generator/checker.
-
-    Parameters
-    ----------
-    data_width : int
-        Width of the data bus.
-
-    Attributes
-    ----------
-    d : in
-        Data input.
-    value : out
-        CRC value (used for generator).
-    error : out
-        CRC error (used for checker).
-    """
     # Section 9.2.2.2 (CXP-001-2021)
     width = 32
     polynom = 0x04C11DB7