forked from M-Labs/artiq-zynq
downconn GW: rename to gt_refclk
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4a83108637
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@ -13,7 +13,7 @@ from functools import reduce
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from operator import add
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from operator import add
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class CXP_RXPHYs(Module, AutoCSR):
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class CXP_RXPHYs(Module, AutoCSR):
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def __init__(self, refclk, pads, sys_clk_freq, master):
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def __init__(self, gt_refclk, pads, sys_clk_freq, master):
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self.qpll_reset = CSR()
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self.qpll_reset = CSR()
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self.qpll_locked = CSRStatus()
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self.qpll_locked = CSRStatus()
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self.gtx_start_init = CSRStorage()
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self.gtx_start_init = CSRStorage()
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@ -23,7 +23,7 @@ class CXP_RXPHYs(Module, AutoCSR):
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# # #
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# # #
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# For speed higher than 6.6Gbps, QPLL need to be used instead of CPLL - DS191 (v1.18.1) Table 9.1
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# For speed higher than 6.6Gbps, QPLL need to be used instead of CPLL - DS191 (v1.18.1) Table 9.1
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self.submodules.qpll = qpll = QPLL(refclk, sys_clk_freq)
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self.submodules.qpll = qpll = QPLL(gt_refclk, sys_clk_freq)
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self.sync += [
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self.sync += [
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qpll.reset.eq(self.qpll_reset.re),
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qpll.reset.eq(self.qpll_reset.re),
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self.qpll_locked.status.eq(qpll.lock),
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self.qpll_locked.status.eq(qpll.lock),
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@ -70,7 +70,7 @@ class Receiver(Module):
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]
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]
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class QPLL(Module, AutoCSR):
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class QPLL(Module, AutoCSR):
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def __init__(self, refclk, sys_clk_freq):
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def __init__(self, gt_refclk, sys_clk_freq):
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self.clk = Signal()
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self.clk = Signal()
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self.refclk = Signal()
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self.refclk = Signal()
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self.lock = Signal()
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self.lock = Signal()
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@ -101,7 +101,7 @@ class QPLL(Module, AutoCSR):
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self.specials += [
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self.specials += [
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Instance("GTXE2_COMMON",
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Instance("GTXE2_COMMON",
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i_QPLLREFCLKSEL=0b001,
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i_QPLLREFCLKSEL=0b001,
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i_GTREFCLK0=refclk,
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i_GTREFCLK0=gt_refclk,
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i_QPLLPD=0,
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i_QPLLPD=0,
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i_QPLLRESET=self.reset,
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i_QPLLRESET=self.reset,
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