From f0dda0fcf72f7e9f52e65a8b8d63be95e80ba628 Mon Sep 17 00:00:00 2001
From: morgan <mc@m-labs.hk>
Date: Fri, 14 Jun 2024 17:17:56 +0800
Subject: [PATCH] cxp: add upconn interface, downconn PHY & crc

testing: add CSR control for tx trigger & trigger ack
upconn: connect trigger, trigger ack & command_packet to UpConnPHY
downconn: add GTX PHY
---
 src/gateware/cxp.py | 69 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 69 insertions(+)
 create mode 100644 src/gateware/cxp.py

diff --git a/src/gateware/cxp.py b/src/gateware/cxp.py
new file mode 100644
index 0000000..3622726
--- /dev/null
+++ b/src/gateware/cxp.py
@@ -0,0 +1,69 @@
+from migen import *
+from misoc.interconnect.csr import *
+from misoc.interconnect import stream
+
+from cxp_downconn import CXP_DownConn
+from cxp_upconn import CXP_UpConn_PHY
+from cxp_pipeline import *
+
+class CXP(Module, AutoCSR):
+    def __init__(self, refclk, downconn_pads, upconn_pads, sys_clk_freq, debug_sma, pmod_pads):
+        self.submodules.upconn = UpConn_Interface(upconn_pads, sys_clk_freq, debug_sma, pmod_pads)
+
+        self.submodules.downconn = CXP_DownConn(refclk, downconn_pads, sys_clk_freq, debug_sma, pmod_pads)
+        # TODO: support the option high speed upconn
+
+        # TODO: add link layer
+
+        
+class UpConn_Interface(Module, AutoCSR):
+    def __init__(self, upconn_pads, sys_clk_freq, debug_sma, pmod_pads):
+        self.clk_reset = CSRStorage(reset=1)
+        self.bitrate2x_enable = CSRStorage()
+        self.tx_enable = CSRStorage()
+        self.tx_busy = CSRStatus()
+
+        # # #
+
+        layout = [("data", 8), ("k", 1)]
+
+        self.submodules.upconn_phy = upconn_phy = CXP_UpConn_PHY(upconn_pads, sys_clk_freq, debug_sma, pmod_pads, layout)
+
+        self.sync += [
+            upconn_phy.bitrate2x_enable.eq(self.bitrate2x_enable.storage),
+            upconn_phy.tx_enable.eq(self.tx_enable.storage),
+            upconn_phy.clk_reset.eq(self.clk_reset.re),
+            self.tx_busy.status.eq(upconn_phy.tx_busy),
+        ]
+
+
+        # Packet FIFOs with transmission priority
+        # 0: Trigger packet
+        self.submodules.trig = trig = TX_Trigger(layout)
+        self.comb += trig.source.connect(upconn_phy.sinks[0])
+        
+        # DEBUG: INPUT
+        self.trig_stb = CSR()
+        self.trig_delay = CSRStorage(8) 
+        self.linktrigger = CSRStorage(2)
+
+        self.sync += [
+            trig.trig_stb.eq(self.trig_stb.re),
+            trig.delay.eq(self.trig_delay.storage),
+            trig.linktrig_mode.eq(self.linktrigger.storage),
+        ]
+
+        
+        # 1: IO acknowledgment for trigger packet
+        self.submodules.trig_ack = trig_ack = Trigger_ACK(layout)
+        self.comb += trig_ack.source.connect(upconn_phy.sinks[1])
+
+        # DEBUG: INPUT
+        self.ack = CSR()
+        self.sync += trig_ack.ack.eq(self.ack.re),
+
+
+        # 2: All other packets
+        # Control is not timing dependent, all the link layer is done in firmware
+        self.submodules.command = command = TX_Command_Packet(layout)
+        self.comb += command.source.connect(upconn_phy.sinks[2])