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frameline GW: add reg for arbiter & broadcaster

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This commit is contained in:
morgan 2025-01-14 11:36:59 +08:00
parent 26d940fbc3
commit ef9d633e9b
1 changed files with 23 additions and 19 deletions
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42
src/gateware/cxp_frame_pipeline.py
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@ -78,9 +78,11 @@ class Stream_Arbiter(Module):
# When Multiple connections are active, stream packets are transmitted in # When Multiple connections are active, stream packets are transmitted in
# ascending order of Connection ID (which we currently only support ch1->2->3->4). # ascending order of Connection ID (which we currently only support ch1->2->3->4).
# And one connection shall be transmitting data at a time. # And one connection shall be transmitting data at a time.
n_ext_active_r = Signal.like(self.n_ext_active)
self.sync += n_ext_active_r.eq(self.n_ext_active)
fsm.act( fsm.act(
"SWITCH_SOURCE", "SWITCH_SOURCE",
If(read_mask == self.n_ext_active, If(read_mask == n_ext_active_r,
NextValue(read_mask, read_mask.reset), NextValue(read_mask, read_mask.reset),
).Else( ).Else(
NextValue(read_mask, read_mask + 1), NextValue(read_mask, read_mask + 1),
@ -159,31 +161,33 @@ class Stream_Broadcaster(Module):
def __init__(self, n_buffer, default_id=0): def __init__(self, n_buffer, default_id=0):
assert n_buffer > 0 assert n_buffer > 0
self.routing_table = [Signal(char_width) for _ in range(1, n_buffer)] self.routing_ids = [Signal(char_width) for _ in range(1, n_buffer)]
self.sources = [stream.Endpoint(word_layout_dchar) for _ in range(n_buffer)] self.sources = [stream.Endpoint(word_layout_dchar) for _ in range(n_buffer)]
self.sink = stream.Endpoint(word_layout_dchar) self.sink = stream.Endpoint(word_layout_dchar)
# # # # # #
routing_ids_r = [Signal(char_width) for _ in range(1, n_buffer)]
for i, id in enumerate(self.routing_ids):
self.sync += routing_ids_r[i].eq(id)
stream_id = Signal(char_width)
self.stream_id = Signal(char_width) pak_tag = Signal(char_width)
self.pak_tag = Signal(char_width) stream_pak_size = Signal(char_width * 2)
self.stream_pak_size = Signal(char_width * 2)
self.submodules.fsm = fsm = FSM(reset_state="WAIT_HEADER") self.submodules.fsm = fsm = FSM(reset_state="WAIT_HEADER")
fsm.act( fsm.act(
"WAIT_HEADER", "WAIT_HEADER",
NextValue(self.stream_id, self.stream_id.reset), NextValue(stream_id, stream_id.reset),
NextValue(self.pak_tag, self.pak_tag.reset), NextValue(pak_tag, pak_tag.reset),
NextValue(self.stream_pak_size, self.stream_pak_size.reset), NextValue(stream_pak_size, stream_pak_size.reset),
self.sink.ack.eq(1), self.sink.ack.eq(1),
If( If(
self.sink.stb, self.sink.stb,
NextValue(self.stream_id, self.sink.dchar), NextValue(stream_id, self.sink.dchar),
NextState("GET_PAK_TAG"), NextState("GET_PAK_TAG"),
), ),
) )
@ -193,7 +197,7 @@ class Stream_Broadcaster(Module):
self.sink.ack.eq(1), self.sink.ack.eq(1),
If( If(
self.sink.stb, self.sink.stb,
NextValue(self.pak_tag, self.sink.dchar), NextValue(pak_tag, self.sink.dchar),
NextState("GET_PAK_SIZE_0"), NextState("GET_PAK_SIZE_0"),
), ),
) )
@ -203,7 +207,7 @@ class Stream_Broadcaster(Module):
self.sink.ack.eq(1), self.sink.ack.eq(1),
If( If(
self.sink.stb, self.sink.stb,
NextValue(self.stream_pak_size[8:], self.sink.dchar), NextValue(stream_pak_size[8:], self.sink.dchar),
NextState("GET_PAK_SIZE_1"), NextState("GET_PAK_SIZE_1"),
), ),
) )
@ -213,7 +217,7 @@ class Stream_Broadcaster(Module):
self.sink.ack.eq(1), self.sink.ack.eq(1),
If( If(
self.sink.stb, self.sink.stb,
NextValue(self.stream_pak_size[:8], self.sink.dchar), NextValue(stream_pak_size[:8], self.sink.dchar),
NextState("STORE_BUFFER"), NextState("STORE_BUFFER"),
), ),
) )
@ -221,9 +225,9 @@ class Stream_Broadcaster(Module):
# routing decoder # routing decoder
sel = Signal(n_buffer) sel = Signal(n_buffer)
no_match = Signal() no_match = Signal()
self.comb += sel[0].eq(self.stream_id == default_id) self.comb += sel[0].eq(stream_id == default_id)
for i, routing_id in enumerate(self.routing_table): for i, id in enumerate(routing_ids_r):
self.comb += sel[i+1].eq(self.stream_id == routing_id) self.comb += sel[i+1].eq(stream_id == id)
# DEBUG: disrecard the stream id = 0 rule # DEBUG: disrecard the stream id = 0 rule
# self.comb += source_sel[0].eq(self.stream_id == self.routing_table[0]) # self.comb += source_sel[0].eq(self.stream_id == self.routing_table[0])
@ -247,8 +251,8 @@ class Stream_Broadcaster(Module):
), ),
# assume downstream is not blocked # assume downstream is not blocked
If(self.sink.stb, If(self.sink.stb,
NextValue(self.stream_pak_size, self.stream_pak_size - 1), NextValue(stream_pak_size, stream_pak_size - 1),
If(self.stream_pak_size == 0, If(stream_pak_size == 0,
NextState("WAIT_HEADER"), NextState("WAIT_HEADER"),
) )
), ),
@ -628,7 +632,7 @@ class Frame_Packet_Router(Module):
self.submodules.broadcaster = broadcaster = Stream_Broadcaster(n_buffer) self.submodules.broadcaster = broadcaster = Stream_Broadcaster(n_buffer)
for i, s in enumerate(self.routing_table): for i, s in enumerate(self.routing_table):
self.sync += broadcaster.routing_table[i].eq(s) self.sync += broadcaster.routing_ids[i].eq(s)
for i, d in enumerate(downconns): for i, d in enumerate(downconns):
# Assume downconns pipeline already marks the eop # Assume downconns pipeline already marks the eop