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cxp GW: fix extra 1 bits issue

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cxp GW: add docs
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morgan 2025-01-17 13:08:36 +08:00
parent b3e06ccf13
commit ee3cac1efb
1 changed files with 3 additions and 1 deletions
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4
src/gateware/cxp.py
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@ -342,7 +342,9 @@ class CXP_Frame_Pipeline(Module, AutoCSR):
self.sync.rio += [
# TODO: add gating
self.gate_data.i.stb.eq(update),
self.gate_data.i.data.eq(count_sys),
# without the slice, unspecified bits will be 1 for some reason
# i.e. data[count_wdith:] = 0b111111... when using data.eq(count_sys)
self.gate_data.i.data[:count_width].eq(count_sys),
]