From ee3cac1efbc468b9c3b343a065fd2ab9dae8bf16 Mon Sep 17 00:00:00 2001
From: morgan <mc@m-labs.hk>
Date: Fri, 17 Jan 2025 13:08:36 +0800
Subject: [PATCH] cxp GW: fix extra 1 bits issue

cxp GW: add docs
---
 src/gateware/cxp.py | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/gateware/cxp.py b/src/gateware/cxp.py
index becaf32..00cf3b2 100644
--- a/src/gateware/cxp.py
+++ b/src/gateware/cxp.py
@@ -342,7 +342,9 @@ class CXP_Frame_Pipeline(Module, AutoCSR):
             self.sync.rio += [
                 # TODO: add gating
                 self.gate_data.i.stb.eq(update),
-                self.gate_data.i.data.eq(count_sys),
+                # without the slice, unspecified bits will be 1 for some reason
+                # i.e. data[count_wdith:] = 0b111111... when using data.eq(count_sys)
+                self.gate_data.i.data[:count_width].eq(count_sys),
             ]