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cxp GW: rname to rxphys

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morgan 2025-01-14 13:04:12 +08:00
parent 034588ec59
commit ec84a332c7
1 changed files with 4 additions and 4 deletions
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8
src/gateware/cxp.py
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@ -1,10 +1,10 @@
from migen import * from migen import *
from migen.genlib.cdc import MultiReg, PulseSynchronizer, BusSynchronizer from migen.genlib.cdc import MultiReg, PulseSynchronizer
from misoc.interconnect.csr import * from misoc.interconnect.csr import *
from artiq.gateware.rtio import rtlink from artiq.gateware.rtio import rtlink
from cxp_downconn import CXP_DownConn_PHYS from cxp_downconn import CXP_RXPHYs
from cxp_upconn import CXP_TXPHYs from cxp_upconn import CXP_TXPHYs
from cxp_pipeline import * from cxp_pipeline import *
from cxp_frame_pipeline import * from cxp_frame_pipeline import *
@ -18,10 +18,10 @@ class CXP_PHYS(Module, AutoCSR):
assert len(upconn_pads) == len(downconn_pads) assert len(upconn_pads) == len(downconn_pads)
self.submodules.tx = CXP_TXPHYs(upconn_pads, sys_clk_freq, debug_sma, pmod_pads) self.submodules.tx = CXP_TXPHYs(upconn_pads, sys_clk_freq, debug_sma, pmod_pads)
self.submodules.downconn = CXP_DownConn_PHYS(refclk, downconn_pads, sys_clk_freq, debug_sma, pmod_pads) self.submodules.rx = CXP_RXPHYs(refclk, downconn_pads, sys_clk_freq, debug_sma, pmod_pads)
self.phys = [] self.phys = []
for tx, rx in zip(self.tx.phys, self.downconn.rx_phys): for tx, rx in zip(self.tx.phys, self.rx.phys):
phy = SimpleNamespace() phy = SimpleNamespace()
phy.tx, phy.rx = tx, rx phy.tx, phy.rx = tx, rx
self.phys.append(phy) self.phys.append(phy)