forked from M-Labs/artiq-zynq
sim: add frame sim
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from migen import *
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from misoc.interconnect import stream
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from sim_pipeline import *
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from sim_generator import CXPCRC32Inserter
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from src.gateware.cxp_pipeline import *
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class Frame(Module):
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def __init__(self):
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# to construct correct crc and ack/stb signal
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self.submodules.buffer = buffer = stream.SyncFIFO(word_layout, 32)
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self.submodules.crc_inserter = crc_inserter = CXPCRC32Inserter()
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self.submodules.dchar_decoder = dchar_decoder = Duplicated_Char_Decoder()
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self.submodules.stream_pipe = stream_pipe = Stream_Pipeline()
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pipeline = [buffer, crc_inserter, dchar_decoder, stream_pipe]
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for s, d in zip(pipeline, pipeline[1:]):
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self.comb += s.source.connect(d.sink)
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self.sink = pipeline[0].sink
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self.source = pipeline[-1].source
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# no backpressure for sim
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self.sync += self.source.ack.eq(1)
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dut = Frame()
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def check_case(packet=[]):
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print("=================TEST========================")
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sink = dut.sink
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stream_pipe = dut.stream_pipe
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for i, p in enumerate(packet):
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yield sink.data.eq(p["data"])
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yield sink.k.eq(p["k"])
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yield sink.stb.eq(1)
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if "eop" in p:
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yield sink.eop.eq(1)
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else:
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yield sink.eop.eq(0)
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# check cycle result
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yield
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# source = dut.dchar_decoder.source
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source = dut.stream_pipe.frame_extractor.sink
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print(
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f"\nCYCLE#{i} : source char = {yield source.data:#X} k = {yield source.k:#X} stb = {yield source.stb} ack = {yield source.ack} eop = {yield source.eop}"
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# f" source dchar = {yield source.dchar:#X} dchar_k = {yield source.dchar_k:#X}"
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# f"\nCYCLE#{i} : stream id = {yield decoder.stream_id:#X} pak_tag = {yield decoder.pak_tag:#X}"
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# f" stream_pak_size = {yield decoder.stream_pak_size:#X}"
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)
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# crc = downconns[1].generator.crc_inserter.crc
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# crc = dut.double_buffer.crc
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# print(
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# f"CYCLE#{i} : crc error = {yield crc.error:#X} crc value = {yield crc.value:#X}"
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# f" crc data = {yield crc.data:#X} engine next = {yield crc.engine.next:#X} ce = {yield crc.ce}"
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# )
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# extra clk cycles
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cyc = i + 1
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for i in range(cyc, cyc + 50):
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yield sink.data.eq(0)
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yield sink.k.eq(0)
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yield sink.stb.eq(0)
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yield sink.eop.eq(0)
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yield
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print(
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f"\nCYCLE#{i} : source char = {yield source.data:#X} k = {yield source.k:#X} stb = {yield source.stb} ack = {yield source.ack} eop = {yield source.eop}"
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# f" source dchar = {yield source.dchar:#X} dchar_k = {yield source.dchar_k:#X}"
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# f"\nCYCLE#{i} : stream id = {yield decoder.stream_id:#X} pak_tag = {yield decoder.pak_tag:#X}"
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# f" stream_pak_size = {yield decoder.stream_pak_size:#X}"
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)
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metadata = dut.stream_pipe.frame_extractor.metadata
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img_header_layout = [
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"stream_id",
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"source_tag",
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"x_size",
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"x_offset",
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"y_size",
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"y_offset",
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"l_size", # number of data words per image line
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"pixel_format",
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"tap_geo",
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"flag",
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]
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for name in img_header_layout:
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print(f"{name} = {yield getattr(metadata, name):#04X} ", end="")
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print()
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assert True
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def testbench():
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# stream_id = 0x01
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streams = [
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[
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{"data": 0x11111111, "k": Replicate(0, 4)},
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{"data": 0xB105F00D, "k": Replicate(0, 4)},
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],
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[
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{"data": 0x22222222, "k": Replicate(0, 4)},
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{"data": 0xC001BEA0, "k": Replicate(0, 4)},
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],
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[
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{"data": Replicate(KCode["stream_marker"], 4), "k": Replicate(1, 4)},
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{"data": Replicate(C(0x01,char_width), 4), "k": Replicate(0, 4)},
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{"data": Replicate(C(0x02,char_width), 4), "k": Replicate(0, 4)},
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{"data": Replicate(C(0x03,char_width), 4), "k": Replicate(0, 4)},
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{"data": Replicate(C(0x04,char_width), 4), "k": Replicate(0, 4)},
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{"data": Replicate(C(0x05,char_width), 4), "k": Replicate(0, 4)},
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{"data": Replicate(C(0x06,char_width), 4), "k": Replicate(0, 4)},
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{"data": Replicate(C(0x07,char_width), 4), "k": Replicate(0, 4)},
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{"data": Replicate(C(0x08,char_width), 4), "k": Replicate(0, 4)},
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{"data": Replicate(C(0x09,char_width), 4), "k": Replicate(0, 4)},
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{"data": Replicate(C(0x10,char_width), 4), "k": Replicate(0, 4)},
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{"data": Replicate(C(0x11,char_width), 4), "k": Replicate(0, 4)},
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{"data": Replicate(C(0x12,char_width), 4), "k": Replicate(0, 4)},
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{"data": Replicate(C(0x13,char_width), 4), "k": Replicate(0, 4)},
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{"data": Replicate(C(0x14,char_width), 4), "k": Replicate(0, 4)},
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{"data": Replicate(C(0x15,char_width), 4), "k": Replicate(0, 4)},
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{"data": Replicate(C(0x16,char_width), 4), "k": Replicate(0, 4)},
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{"data": Replicate(C(0x17,char_width), 4), "k": Replicate(0, 4)},
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{"data": Replicate(C(0x18,char_width), 4), "k": Replicate(0, 4)},
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{"data": Replicate(C(0x19,char_width), 4), "k": Replicate(0, 4)},
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{"data": Replicate(C(0x20,char_width), 4), "k": Replicate(0, 4)},
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{"data": Replicate(C(0x21,char_width), 4), "k": Replicate(0, 4)},
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{"data": Replicate(C(0x22,char_width), 4), "k": Replicate(0, 4)},
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{"data": Replicate(C(0x23,char_width), 4), "k": Replicate(0, 4)},
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{"data": Replicate(C(0x24,char_width), 4), "k": Replicate(0, 4)},
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],
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]
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packet = []
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for i, s in enumerate(streams):
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s[-1]["eop"] = 0
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packet += [
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{"data": Replicate(C(i % 2, char_width), 4), "k": Replicate(0, 4)},
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{"data": Replicate(C(i, char_width), 4), "k": Replicate(0, 4)},
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{
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"data": Replicate(C(len(s) >> 8 & 0xFF, char_width), 4),
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"k": Replicate(0, 4),
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},
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{"data": Replicate(C(len(s) & 0xFF, char_width), 4), "k": Replicate(0, 4)},
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*s,
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]
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yield from check_case(packet)
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run_simulation(dut, testbench(), vcd_name="sim-cxp.vcd")
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