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cxp upconn:clean up and remove csr

This commit is contained in:
morgan 2024-08-27 11:12:49 +08:00
parent bc0d45cd82
commit e78d0f4083
1 changed files with 9 additions and 26 deletions
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35
src/gateware/cxp_upconn.py
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@ -10,9 +10,9 @@ from misoc.interconnect.csr import *
class CXP_UpConn(Module, AutoCSR): class CXP_UpConn(Module, AutoCSR):
def __init__(self, pad, sys_clk_freq, debug_sma, pmod_pads, fifo_depth, nfifos=3): def __init__(self, pad, sys_clk_freq, debug_sma, pmod_pads, fifo_depth, nfifos=3):
self.clock_domains.cd_cxp_upconn = ClockDomain() self.clock_domains.cd_cxp_upconn = ClockDomain()
self.clk_reset = CSRStorage(reset=1) self.clk_reset = Signal()
self.bitrate2x_enable = CSRStorage() self.bitrate2x_enable = Signal()
self.tx_enable = CSRStorage() self.tx_enable = Signal()
# # # # # #
@ -43,15 +43,15 @@ class CXP_UpConn(Module, AutoCSR):
Instance("BUFGMUX", Instance("BUFGMUX",
i_I0=pll_cxpclk, i_I0=pll_cxpclk,
i_I1=pll_cxpclk2x, i_I1=pll_cxpclk2x,
i_S=self.bitrate2x_enable.storage, i_S=self.bitrate2x_enable,
o_O=self.cd_cxp_upconn.clk o_O=self.cd_cxp_upconn.clk
), ),
AsyncResetSynchronizer(self.cd_cxp_upconn, ~pll_locked | self.clk_reset.storage) AsyncResetSynchronizer(self.cd_cxp_upconn, ~pll_locked | self.clk_reset)
] ]
self.submodules.startup_fsm = startup_fsm = ClockDomainsRenamer("cxp_upconn")(FSM(reset_state="WAIT_TX_ENABLE")) self.submodules.startup_fsm = startup_fsm = ClockDomainsRenamer("cxp_upconn")(FSM(reset_state="WAIT_TX_ENABLE"))
self.submodules.encoder = encoder = ClockDomainsRenamer("cxp_upconn")(SingleEncoder(True)) self.submodules.encoder = encoder = ClockDomainsRenamer("cxp_upconn")(SingleEncoder(True))
self.submodules.tx_fifos = tx_fifos = TxFIFOs(self.nfifos, fifo_depth) self.submodules.tx_fifos = tx_fifos = TxFIFOs(nfifos, fifo_depth)
self.submodules.tx_idle = tx_idle = TxIdle() self.submodules.tx_idle = tx_idle = TxIdle()
o = Signal() o = Signal()
@ -63,12 +63,12 @@ class CXP_UpConn(Module, AutoCSR):
tx_wordcount = Signal(max=10000) tx_wordcount = Signal(max=10000)
tx_reg = Signal(10) tx_reg = Signal(10)
priorities = Signal(max=self.nfifos) priorities = Signal(max=nfifos)
idling = Signal() idling = Signal()
startup_fsm.act("WAIT_TX_ENABLE", startup_fsm.act("WAIT_TX_ENABLE",
If(self.tx_enable.storage, If(self.tx_enable,
NextValue(tx_idle.word_idx, 0), NextValue(tx_idle.word_idx, 0),
NextState("ENCODE_CHAR") NextState("ENCODE_CHAR")
) )
@ -93,7 +93,7 @@ class CXP_UpConn(Module, AutoCSR):
startup_fsm.act("START_TX", startup_fsm.act("START_TX",
tx_en.eq(1), tx_en.eq(1),
If((~self.tx_enable.storage) & (tx_charcount == 3), If((~self.tx_enable) & (tx_charcount == 3),
NextState("WAIT_TX_ENABLE") NextState("WAIT_TX_ENABLE")
) )
) )
@ -199,23 +199,6 @@ class CXP_UpConn(Module, AutoCSR):
Instance("OBUF", i_I=p0, o_O=pmod_pads[6]), Instance("OBUF", i_I=p0, o_O=pmod_pads[6]),
Instance("OBUF", i_I=p3, o_O=pmod_pads[7]), Instance("OBUF", i_I=p3, o_O=pmod_pads[7]),
] ]
self.symbol0 = CSR(9)
self.symbol1 = CSR(9)
self.symbol2 = CSR(9)
self.sync += [
tx_fifos.sink_stb[0].eq(self.symbol0.re),
tx_fifos.sink_data[0].eq(self.symbol0.r[:8]),
tx_fifos.sink_k[0].eq(self.symbol0.r[8]),
tx_fifos.sink_stb[1].eq(self.symbol1.re),
tx_fifos.sink_data[1].eq(self.symbol1.r[:8]),
tx_fifos.sink_k[1].eq(self.symbol1.r[8]),
tx_fifos.sink_stb[2].eq(self.symbol2.re),
tx_fifos.sink_data[2].eq(self.symbol2.r[:8]),
tx_fifos.sink_k[2].eq(self.symbol2.r[8]),
]
class TxFIFOs(Module): class TxFIFOs(Module):
def __init__(self, nfifos, fifo_depth): def __init__(self, nfifos, fifo_depth):