forked from M-Labs/artiq-zynq
cxp upconn: add sink to txphy & cleanup
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00e5d32d45
commit
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@ -1,8 +1,7 @@
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.genlib.cdc import MultiReg
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from misoc.cores.code_8b10b import SingleEncoder, Decoder
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from misoc.cores.code_8b10b import SingleEncoder
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from misoc.interconnect.csr import *
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from misoc.interconnect import stream
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@ -10,9 +9,10 @@ class CXP_UpConn(Module, AutoCSR):
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def __init__(self, pads, tx_fifo_depth=32):
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self.clock_domains.cd_cxp_upconn = ClockDomain()
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self.clk_reset = CSRStorage(reset=1)
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self.bitrate2x_enable = CSRStorage()
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self.tx_fifos = []
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# # #
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pll_locked = Signal()
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@ -48,73 +48,30 @@ class CXP_UpConn(Module, AutoCSR):
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AsyncResetSynchronizer(self.cd_cxp_upconn, ~pll_locked | self.clk_reset.storage)
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]
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self.symbol0 = CSR(9)
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self.symbol1 = CSR(9)
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self.submodules.phy = UpConnTXPHY(pads)
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nfifos = 2
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self.data = [ Signal(8) for _ in range(nfifos)]
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self.k_symbol = [ Signal() for _ in range(nfifos)]
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self.stb = [ Signal() for _ in range(nfifos)]
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self.fifo_full = CSRStatus(nfifos)
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self.tx_fifos = []
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self.tx_encoders = []
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cdr = ClockDomainsRenamer({"write": "sys", "read": "cxp_upconn"})
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# Priority Queue
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# FIFOs with transmission priority
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# 0: Trigger packet
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# 1: IO acknowledgment for trigger packet
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# 2: All other packets
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for i in range(nfifos):
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cdr = ClockDomainsRenamer({"write": "sys", "read": "cxp_upconn"})
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fifo = cdr(stream.AsyncFIFO([("data", 9)], tx_fifo_depth))
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# fifo = stream.SyncFIFO([("data", 9)], tx_fifo_depth)
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self.tx_fifos.append(fifo)
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setattr(self.submodules, "tx_fifo" + str(i), fifo)
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self.sync += [
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fifo.sink.stb.eq(self.stb[i]),
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fifo.sink.data.eq(Cat(self.data[i], self.k_symbol[i])),
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self.fifo_full.status[i].eq(~fifo.sink.ack),
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]
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self.sync += [
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self.stb[0].eq(self.symbol0.re),
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self.data[0].eq(self.symbol0.r[:8]),
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self.k_symbol[0].eq(self.symbol0.r[8]),
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self.stb[1].eq(self.symbol1.re),
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self.data[1].eq(self.symbol1.r[:8]),
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self.k_symbol[1].eq(self.symbol1.r[8]),
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]
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self.tx_fifo0_source_data = CSRStatus(9)
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self.tx_fifo1_source_data = CSRStatus(9)
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self.tx_fifo0_stb = CSRStatus()
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self.tx_fifo1_stb = CSRStatus()
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self.submodules.tx = UpConn_TX(pads)
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self.comb += [
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self.tx_fifo0_source_data.status.eq(self.tx_fifos[0].source.data),
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self.tx_fifo1_source_data.status.eq(self.tx_fifos[1].source.data),
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self.tx_fifo0_stb.status.eq(self.tx_fifos[0].source.stb),
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self.tx_fifo1_stb.status.eq(self.tx_fifos[1].source.stb),
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]
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self.sync.cxp_upconn +=[
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self.tx.data_stb.eq(self.tx_fifos[0].source.stb | self.tx_fifos[1].source.stb),
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self.phy.sink.stb.eq(self.tx_fifos[0].source.stb | self.tx_fifos[1].source.stb),
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self.tx_fifos[0].source.ack.eq(0),
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self.tx_fifos[1].source.ack.eq(0),
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If(self.tx.data_ack,
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If(self.phy.sink.ack,
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If(self.tx_fifos[0].source.stb,
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self.tx.encoder.d.eq(self.tx_fifos[0].source.data[:8]),
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self.tx.encoder.k.eq(self.tx_fifos[0].source.data[8]),
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self.phy.sink.data.eq(self.tx_fifos[0].source.data),
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self.tx_fifos[0].source.ack.eq(1),
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).Elif(self.tx_fifos[1].source.stb,
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self.tx.encoder.d.eq(self.tx_fifos[1].source.data[:8]),
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self.tx.encoder.k.eq(self.tx_fifos[1].source.data[8]),
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self.phy.sink.data.eq(self.tx_fifos[1].source.data),
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self.tx_fifos[1].source.ack.eq(1),
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),
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),
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@ -122,41 +79,52 @@ class CXP_UpConn(Module, AutoCSR):
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# DEBUG: remove pads
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self.specials += Instance("OBUF", i_I=self.cd_cxp_upconn.clk, o_O=pads.n_rx)
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self.symbol0 = CSR(9)
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self.symbol1 = CSR(9)
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class UpConn_TX(Module, AutoCSR):
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self.sync += [
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self.tx_fifos[0].sink.stb.eq(self.symbol0.re),
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self.tx_fifos[0].sink.data.eq(self.symbol0.r),
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self.tx_fifos[1].sink.stb.eq(self.symbol1.re),
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self.tx_fifos[1].sink.data.eq(self.symbol1.r),
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# self.fifo_full[i].eq(~fifo.sink.ack),
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]
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class UpConnTXPHY(Module, AutoCSR):
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def __init__(self, pads):
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self.data_ack = Signal()
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self.data_stb = Signal()
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self.data_out = CSRStatus(10)
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self.sink = stream.Endpoint([("data", 9)])
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# # #
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self.submodules.encoder = ClockDomainsRenamer("cxp_upconn")(SingleEncoder(True))
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self.comb += [
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self.encoder.d.eq(self.sink.data[:8]),
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self.encoder.k.eq(self.sink.data[8])
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]
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o = Signal()
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tx_busy = Signal()
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tx_bitcount = Signal(max=10)
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tx_reg = Signal(10)
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self.specials += Instance("OBUF", i_I=o, o_O=pads.p_tx)
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self.sync.cxp_upconn +=[
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self.data_ack.eq(0),
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self.sink.ack.eq(0),
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If(tx_busy,
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o.eq(tx_reg[0]),
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tx_reg.eq(Cat(tx_reg[1:], 0))
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),
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If(tx_bitcount != 9,
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tx_bitcount.eq(tx_bitcount + 1),
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).Elif(self.data_stb,
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).Elif(self.sink.stb,
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tx_busy.eq(1),
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tx_bitcount.eq(0),
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tx_reg.eq(self.encoder.output),
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self.data_out.status.eq(self.encoder.output),
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self.encoder.disp_in.eq(self.encoder.disp_out),
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self.data_ack.eq(1),
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self.sink.ack.eq(1),
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).Else(
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tx_busy.eq(0),
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o.eq(0)
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)
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]
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self.specials += Instance("OBUF", i_I=o, o_O=pads.p_tx)
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