forked from M-Labs/artiq-zynq
cxp upconn: rename & add cxp_phy_layout
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6e27c371ec
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@ -178,7 +178,7 @@ class Packets_Scheduler(Module):
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class TxFIFOs(Module):
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class TxFIFOs(Module):
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def __init__(self, nfifos, fifo_depth):
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def __init__(self, cxp_phy_layout, nfifos, fifo_depth):
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self.sink_full = Signal(nfifos)
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self.sink_full = Signal(nfifos)
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self.sink_stb = Signal(nfifos)
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self.sink_stb = Signal(nfifos)
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@ -191,10 +191,10 @@ class TxFIFOs(Module):
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# # #
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# # #
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not_empty_reg = Signal(nfifos)
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data_available = Signal(nfifos)
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for i in range(nfifos):
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for i in range(nfifos):
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fifo = stream.SyncFIFO([("data", 8), ("k", 1)], fifo_depth)
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fifo = stream.SyncFIFO(cxp_phy_layout, fifo_depth)
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setattr(self.submodules, "tx_fifo" + str(i), fifo)
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setattr(self.submodules, "tx_fifo" + str(i), fifo)
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@ -212,24 +212,24 @@ class TxFIFOs(Module):
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fifo.source.ack.eq(0),
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fifo.source.ack.eq(0),
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),
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),
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not_empty_reg[i].eq(fifo.source.stb),
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data_available[i].eq(fifo.source.stb),
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self.source_data[i].eq(fifo.source.data),
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self.source_data[i].eq(fifo.source.data),
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self.source_k[i].eq(fifo.source.k),
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self.source_k[i].eq(fifo.source.k),
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]
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]
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# FIFOs transmission priority
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# FIFOs transmission priority
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self.submodules.pe = PriorityEncoder(nfifos)
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self.submodules.pe = PriorityEncoder(nfifos)
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self.comb += self.pe.i.eq(not_empty_reg)
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self.comb += self.pe.i.eq(data_available)
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class CXP_UpConn(Module):
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class CXP_UpConn(Module):
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def __init__(self, pad, sys_clk_freq, debug_sma, pmod_pads, fifo_depth, nfifos=3):
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def __init__(self, pad, sys_clk_freq, debug_sma, pmod_pads, cxp_phy_layout, fifo_depth, nfifos=3):
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self.bitrate2x_enable = Signal()
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self.bitrate2x_enable = Signal()
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self.tx_enable = Signal()
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self.tx_enable = Signal()
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# # #
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# # #
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self.submodules.cg = cg = UpConn_ClockGen(sys_clk_freq)
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self.submodules.cg = cg = UpConn_ClockGen(sys_clk_freq)
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self.submodules.tx_fifos = tx_fifos = TxFIFOs(nfifos, fifo_depth)
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self.submodules.tx_fifos = tx_fifos = TxFIFOs(cxp_phy_layout, nfifos, fifo_depth)
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self.submodules.scheduler = scheduler = CEInserter()(Packets_Scheduler(tx_fifos))
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self.submodules.scheduler = scheduler = CEInserter()(Packets_Scheduler(tx_fifos))
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self.submodules.serdes = serdes = CEInserter()(SERDES_10bits(pad))
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self.submodules.serdes = serdes = CEInserter()(SERDES_10bits(pad))
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@ -260,22 +260,22 @@ class CXP_UpConn(Module):
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p0.eq(scheduler.tx_charcount == 2),
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p0.eq(scheduler.tx_charcount == 2),
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p3.eq(scheduler.tx_charcount == 1),
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p3.eq(scheduler.tx_charcount == 1),
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]
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]
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self.specials += [
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# self.specials += [
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# # debug sma
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# # # debug sma
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Instance("OBUF", i_I=cg.clk, o_O=debug_sma.p_tx),
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# Instance("OBUF", i_I=cg.clk, o_O=debug_sma.p_tx),
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Instance("OBUF", i_I=cg.clk_10x, o_O=debug_sma.n_rx),
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# Instance("OBUF", i_I=cg.clk_10x, o_O=debug_sma.n_rx),
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# # pmod 0-7 pin
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# # # pmod 0-7 pin
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Instance("OBUF", i_I=serdes.o, o_O=pmod_pads[0]),
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# Instance("OBUF", i_I=serdes.o, o_O=pmod_pads[0]),
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Instance("OBUF", i_I=cg.clk_10x, o_O=pmod_pads[1]),
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# Instance("OBUF", i_I=cg.clk_10x, o_O=pmod_pads[1]),
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Instance("OBUF", i_I=~tx_fifos.pe.n, o_O=pmod_pads[2]),
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# Instance("OBUF", i_I=~tx_fifos.pe.n, o_O=pmod_pads[2]),
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Instance("OBUF", i_I=prioity_0, o_O=pmod_pads[3]),
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# Instance("OBUF", i_I=prioity_0, o_O=pmod_pads[3]),
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Instance("OBUF", i_I=word_bound, o_O=pmod_pads[4]),
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# Instance("OBUF", i_I=word_bound, o_O=pmod_pads[4]),
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Instance("OBUF", i_I=scheduler.idling, o_O=pmod_pads[5]),
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# Instance("OBUF", i_I=scheduler.idling, o_O=pmod_pads[5]),
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# Instance("OBUF", i_I=tx_fifos.source_ack[0], o_O=pmod[6]),
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# # Instance("OBUF", i_I=tx_fifos.source_ack[0], o_O=pmod[6]),
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# Instance("OBUF", i_I=tx_fifos.source_ack[2], o_O=pmod[6]),
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# # Instance("OBUF", i_I=tx_fifos.source_ack[2], o_O=pmod[6]),
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# Instance("OBUF", i_I=tx_fifos.source_ack[1], o_O=pmod[7]),
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# # Instance("OBUF", i_I=tx_fifos.source_ack[1], o_O=pmod[7]),
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Instance("OBUF", i_I=p0, o_O=pmod_pads[6]),
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# Instance("OBUF", i_I=p0, o_O=pmod_pads[6]),
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Instance("OBUF", i_I=p3, o_O=pmod_pads[7]),
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# Instance("OBUF", i_I=p3, o_O=pmod_pads[7]),
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]
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# ]
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