morgan
/
artiq-zynq
forked from M-Labs/artiq-zynq
1
0
Fork 0
Code Pull Requests Activity

cxp upconn: rename & add cxp_phy_layout

This commit is contained in:
morgan 2024-08-29 17:39:21 +08:00
parent 6e27c371ec
commit e382654d9e
1 changed files with 24 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

48
src/gateware/cxp_upconn.py
View File

@ -178,7 +178,7 @@ class Packets_Scheduler(Module):
]
class TxFIFOs(Module):
def __init__(self, nfifos, fifo_depth):
def __init__(self, cxp_phy_layout, nfifos, fifo_depth):
self.sink_full = Signal(nfifos)
self.sink_stb = Signal(nfifos)
@ -191,10 +191,10 @@ class TxFIFOs(Module):
# # #
not_empty_reg = Signal(nfifos)
data_available = Signal(nfifos)
for i in range(nfifos):
fifo = stream.SyncFIFO([("data", 8), ("k", 1)], fifo_depth)
fifo = stream.SyncFIFO(cxp_phy_layout, fifo_depth)
setattr(self.submodules, "tx_fifo" + str(i), fifo)
@ -212,24 +212,24 @@ class TxFIFOs(Module):
fifo.source.ack.eq(0),
),
not_empty_reg[i].eq(fifo.source.stb),
data_available[i].eq(fifo.source.stb),
self.source_data[i].eq(fifo.source.data),
self.source_k[i].eq(fifo.source.k),
]
# FIFOs transmission priority
self.submodules.pe = PriorityEncoder(nfifos)
self.comb += self.pe.i.eq(not_empty_reg)
self.comb += self.pe.i.eq(data_available)
class CXP_UpConn(Module):
def __init__(self, pad, sys_clk_freq, debug_sma, pmod_pads, fifo_depth, nfifos=3):
def __init__(self, pad, sys_clk_freq, debug_sma, pmod_pads, cxp_phy_layout, fifo_depth, nfifos=3):
self.bitrate2x_enable = Signal()
self.tx_enable = Signal()
# # #
self.submodules.cg = cg = UpConn_ClockGen(sys_clk_freq)
self.submodules.tx_fifos = tx_fifos = TxFIFOs(nfifos, fifo_depth)
self.submodules.tx_fifos = tx_fifos = TxFIFOs(cxp_phy_layout, nfifos, fifo_depth)
self.submodules.scheduler = scheduler = CEInserter()(Packets_Scheduler(tx_fifos))
self.submodules.serdes = serdes = CEInserter()(SERDES_10bits(pad))
@ -260,22 +260,22 @@ class CXP_UpConn(Module):
p0.eq(scheduler.tx_charcount == 2),
p3.eq(scheduler.tx_charcount == 1),
]
self.specials += [
# # debug sma
Instance("OBUF", i_I=cg.clk, o_O=debug_sma.p_tx),
Instance("OBUF", i_I=cg.clk_10x, o_O=debug_sma.n_rx),
# self.specials += [
# # # debug sma
# Instance("OBUF", i_I=cg.clk, o_O=debug_sma.p_tx),
# Instance("OBUF", i_I=cg.clk_10x, o_O=debug_sma.n_rx),
# # pmod 0-7 pin
Instance("OBUF", i_I=serdes.o, o_O=pmod_pads[0]),
Instance("OBUF", i_I=cg.clk_10x, o_O=pmod_pads[1]),
Instance("OBUF", i_I=~tx_fifos.pe.n, o_O=pmod_pads[2]),
Instance("OBUF", i_I=prioity_0, o_O=pmod_pads[3]),
Instance("OBUF", i_I=word_bound, o_O=pmod_pads[4]),
Instance("OBUF", i_I=scheduler.idling, o_O=pmod_pads[5]),
# Instance("OBUF", i_I=tx_fifos.source_ack[0], o_O=pmod[6]),
# Instance("OBUF", i_I=tx_fifos.source_ack[2], o_O=pmod[6]),
# Instance("OBUF", i_I=tx_fifos.source_ack[1], o_O=pmod[7]),
Instance("OBUF", i_I=p0, o_O=pmod_pads[6]),
Instance("OBUF", i_I=p3, o_O=pmod_pads[7]),
]
# # # pmod 0-7 pin
# Instance("OBUF", i_I=serdes.o, o_O=pmod_pads[0]),
# Instance("OBUF", i_I=cg.clk_10x, o_O=pmod_pads[1]),
# Instance("OBUF", i_I=~tx_fifos.pe.n, o_O=pmod_pads[2]),
# Instance("OBUF", i_I=prioity_0, o_O=pmod_pads[3]),
# Instance("OBUF", i_I=word_bound, o_O=pmod_pads[4]),
# Instance("OBUF", i_I=scheduler.idling, o_O=pmod_pads[5]),
# # Instance("OBUF", i_I=tx_fifos.source_ack[0], o_O=pmod[6]),
# # Instance("OBUF", i_I=tx_fifos.source_ack[2], o_O=pmod[6]),
# # Instance("OBUF", i_I=tx_fifos.source_ack[1], o_O=pmod[7]),
# Instance("OBUF", i_I=p0, o_O=pmod_pads[6]),
# Instance("OBUF", i_I=p3, o_O=pmod_pads[7]),
# ]