forked from M-Labs/artiq-zynq
frameline GW: add pixel format handling
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6a39f475e9
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@ -575,32 +575,24 @@ class Frame_Deserializer(Module):
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self.new_frame = Signal()
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self.new_frame = Signal()
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self.l_size = Signal(3*char_width)
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self.l_size = Signal(3*char_width)
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self.x_size = Signal(3*char_width)
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self.x_size = Signal(3*char_width)
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self.pixel_format = Signal(2*char_width)
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self.source = stream.Endpoint(pixel4x_layout)
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# # #
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# # #
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self.submodules.eol_inserter = eol_inserter = End_Of_Line_Inserter()
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self.submodules.eol_inserter = eol_inserter = End_Of_Line_Inserter()
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self.sync += eol_inserter.l_size.eq(self.l_size),
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self.sync += eol_inserter.l_size.eq(self.l_size),
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self.sink = eol_inserter.sink
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gearboxes = {}
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for s in [8, 10, 12, 14, 16]:
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for s in [8, 10, 12, 14, 16]:
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gearbox = Pixel_Gearbox(s)
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gearbox = Pixel_Gearbox(s)
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gearboxes["mono"+str(s)] = gearbox
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self.submodules += gearbox
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self.submodules += gearbox
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self.sync += gearbox.x_size.eq(self.x_size),
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self.sync += gearbox.x_size.eq(self.x_size),
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self.comb += eol_inserter.source.connect(gearbox.sink)
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self.comb += gearbox.source.ack.eq(1) # simulated a proper consumer, idk why but without this it will destory timing
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# self.submodules.gearbox = gearbox = Custom_Pixel_Gearbox(8)
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# From Table 34 (CXP-001-2021)
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# self.sync += gearbox.x_size.eq(self.x_size),
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# self.comb += eol_inserter.source.connect(gearbox.sink)
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self.sink = eol_inserter.sink
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# self.source = gearbox.source
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# # TODO: use this to control mux
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# Table 34 (CXP-001-2021)
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pix_fmt = {
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pix_fmt = {
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"mono8": 0x0101,
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"mono8": 0x0101,
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"mono10": 0x0102,
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"mono10": 0x0102,
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@ -608,19 +600,21 @@ class Frame_Deserializer(Module):
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"mono14": 0x0104,
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"mono14": 0x0104,
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"mono16": 0x0105,
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"mono16": 0x0105,
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}
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}
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# self.sync += [
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# pixel_format_r.eq(header_decoder.metadata.pixel_format),
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mux_cases = {
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# Case(pixel_format_r,
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"default": [
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# {
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# discard unknown pixel format data
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# pix_fmt["mono8"]: pix_size.eq(8),
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eol_inserter.source.ack.eq(1),
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# pix_fmt["mono10"]: pix_size.eq(10),
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],
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# pix_fmt["mono12"]: pix_size.eq(12),
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}
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# pix_fmt["mono14"]: pix_size.eq(14),
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for fmt in pix_fmt:
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# pix_fmt["mono16"]: pix_size.eq(16),
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mux_cases[pix_fmt[fmt]] = [
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# "default": pix_size.eq(pix_size.reset),
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eol_inserter.source.connect(gearboxes[fmt].sink),
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# }
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gearboxes[fmt].source.connect(self.source),
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# )
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]
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# ]
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self.comb += Case(self.pixel_format, mux_cases)
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class ROI_Pipeline(Module):
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class ROI_Pipeline(Module):
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@ -639,6 +633,7 @@ class ROI_Pipeline(Module):
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deserializer.new_frame.eq(header_decoder.new_frame),
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deserializer.new_frame.eq(header_decoder.new_frame),
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deserializer.l_size.eq(header_decoder.metadata.l_size),
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deserializer.l_size.eq(header_decoder.metadata.l_size),
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deserializer.x_size.eq(header_decoder.metadata.x_size),
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deserializer.x_size.eq(header_decoder.metadata.x_size),
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deserializer.pixel_format.eq(header_decoder.metadata.pixel_format),
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]
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]
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self.pipeline = [buffer, crc_checker, header_decoder, deserializer]
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self.pipeline = [buffer, crc_checker, header_decoder, deserializer]
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@ -647,8 +642,8 @@ class ROI_Pipeline(Module):
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self.sink = self.pipeline[0].sink
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self.sink = self.pipeline[0].sink
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# DEBUG
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# DEBUG
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# self.source = self.pipeline[-1].source
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self.source = self.pipeline[-1].source
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# self.comb += self.source.ack.eq(1) # simulated a proper consumer, idk why but without this it will destory timing
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self.comb += self.source.ack.eq(1) # simulated a proper consumer, idk why but without this it will destory timing
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class Frame_Packet_Router(Module):
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class Frame_Packet_Router(Module):
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# packet size expressed in bits
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# packet size expressed in bits
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