forked from M-Labs/artiq-zynq
cxp downconn fw: add DRP for linerate
This commit is contained in:
parent
1e87428c68
commit
e0369d2eb2
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@ -4,115 +4,440 @@ use log::info;
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use crate::pl::csr;
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use crate::pl::csr;
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pub fn main(timer: &mut GlobalTimer) {
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pub struct CXP_DownConn_Settings {
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pub rxdiv: u8,
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pub qpll_fbdiv: u8,
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}
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#[derive(Clone, Copy)]
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#[allow(non_camel_case_types)]
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pub enum CXP_SPEED {
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CXP_1,
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CXP_2,
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CXP_3,
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CXP_5,
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CXP_6,
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CXP_10,
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CXP_12,
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}
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fn loopback_testing(timer: &mut GlobalTimer, data: u8, control_bit: u8) {
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unsafe {
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unsafe {
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info!("turning on pmc loopback mode...");
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// send K28_5 for CDR to align
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csr::cxp::downconn_loopback_mode_write(0b010); // Near-End PMA Loopback
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const K28_5: u8 = 0xBC;
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const K28_1: u8 = 0x3C;
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const D21_5: u8 = 21 | 5 << 5;
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// brute force aligner only align K28_5 on rxdata[:10]
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// don't send too much K28_5 in case phase is locked on the wrong stuff
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// seems like I need at least 2 K28_5 to work
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loopback_testing(timer, 0x00, 0);
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// NOTE: testing with IDLE word + buildin comma alignment
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}
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// 62.5MHz OK
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// 125MHz OK
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// 156.25MHz OK
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// 250MHz
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// 312.5MHz
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const LEN: usize = 4;
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const DATA: [[u8; LEN]; 2] = [
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// [K28_5, K28_5, K28_5, K28_1, K28_5, K28_5, K28_5, K28_5],
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// [1, 1, 1, 1, 1, 1, 1, 1],
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[K28_5, K28_1, K28_1, D21_5],
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[1, 1, 1, 0],
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];
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fn loopback_testing(timer: &mut GlobalTimer, data: u8, control_bit: u8) {
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// // STEP 1: reset QPLL
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unsafe {
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// csr::cxp::downconn_qpll_reset_write(1);
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// send K28_5 for CDR to align
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// info!("waiting for QPLL/CPLL to lock...");
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const K28_5: u8 = 0xBC;
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// while csr::cxp::downconn_qpll_locked_read() != 1 {}
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const K28_1: u8 = 0x3C;
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// info!("QPLL locked");
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const D21_5: u8 = 21 | 5 << 5;
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// brute force aligner only align K28_5 on rxdata[:10]
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// don't send too much K28_5 in case phase is locked on the wrong stuff
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// seems like I need at least 2 K28_5 to work
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// NOTE: testing with IDLE word + buildin comma alignment
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// STEP 2: setup tx/rx gtx
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// 62.5MHz OK
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csr::cxp::downconn_data_0_write(DATA[0][0]);
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// 125MHz OK
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csr::cxp::downconn_data_1_write(DATA[0][1]);
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// 156.25MHz OK
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csr::cxp::downconn_data_2_write(DATA[0][2]);
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// 250MHz
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csr::cxp::downconn_data_3_write(DATA[0][3]);
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// 312.5MHz
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const LEN: usize = 4;
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const DATA: [[u8; LEN]; 2] = [
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// [K28_5, K28_5, K28_5, K28_1, K28_5, K28_5, K28_5, K28_5],
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// [1, 1, 1, 1, 1, 1, 1, 1],
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[K28_5, K28_1, K28_1, D21_5],
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[1, 1, 1, 0],
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];
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// STEP 1: reset QPLL
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csr::cxp::downconn_control_bit_0_write(DATA[1][0]);
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csr::cxp::downconn_qpll_reset_write(1);
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csr::cxp::downconn_control_bit_1_write(DATA[1][1]);
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info!("waiting for QPLL/CPLL to lock...");
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csr::cxp::downconn_control_bit_2_write(DATA[1][2]);
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while csr::cxp::downconn_qpll_locked_read() != 1 {}
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csr::cxp::downconn_control_bit_3_write(DATA[1][3]);
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info!("QPLL locked");
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// STEP 2: setup tx/rx gtx
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// TEST: change rx linerate
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csr::cxp::downconn_data_0_write(DATA[0][0]);
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// works great
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csr::cxp::downconn_data_1_write(DATA[0][1]);
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csr::cxp::downconn_data_2_write(DATA[0][2]);
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csr::cxp::downconn_data_3_write(DATA[0][3]);
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csr::cxp::downconn_control_bit_0_write(DATA[1][0]);
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// enable cxp gtx clock domains
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csr::cxp::downconn_control_bit_1_write(DATA[1][1]);
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csr::cxp::downconn_control_bit_2_write(DATA[1][2]);
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csr::cxp::downconn_control_bit_3_write(DATA[1][3]);
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// enable cxp gtx clock domains
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info!("waiting for tx setup...");
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csr::cxp::downconn_tx_start_init_write(1);
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timer.delay_us(50_000);
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csr::cxp::downconn_rx_start_init_write(1);
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info!(
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"tx_phaligndone = {} | rx_phaligndone = {}",
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csr::cxp::downconn_txinit_phaligndone_read(),
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csr::cxp::downconn_rxinit_phaligndone_read(),
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);
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info!("waiting for tx setup...");
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// enable txdata tranmission thought MGTXTXP, required by PMA loopback
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timer.delay_us(50_000);
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csr::cxp::downconn_txenable_write(1);
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info!(
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"tx_phaligndone = {} | rx_phaligndone = {}",
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csr::cxp::downconn_txinit_phaligndone_read(),
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csr::cxp::downconn_rxinit_phaligndone_read(),
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);
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// enable txdata tranmission thought MGTXTXP, required by PMA loopback
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info!("waiting for rx to align...");
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csr::cxp::downconn_txenable_write(1);
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while csr::cxp::downconn_rx_ready_read() != 1 {}
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timer.delay_us(50_000);
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info!("rx ready!");
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info!("waiting for rx to align...");
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// csr::cxp::data_3_write(data);
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while csr::cxp::downconn_rx_ready_read() != 1 {}
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// csr::cxp::control_bit_3_write(control_bit);
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timer.delay_us(50_000);
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println!(
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info!("rx ready!");
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"data[0] = {:#04x} control bit = {:#b} encoded = {:#012b}",
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csr::cxp::downconn_data_0_read(),
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csr::cxp::downconn_control_bit_0_read(),
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csr::cxp::downconn_encoded_0_read(),
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);
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println!(
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"data[1] = {:#04x} control bit = {:#b} encoded = {:#012b}",
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csr::cxp::downconn_data_1_read(),
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csr::cxp::downconn_control_bit_1_read(),
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csr::cxp::downconn_encoded_1_read(),
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);
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// csr::cxp::data_3_write(data);
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for _ in 0..20 {
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// csr::cxp::control_bit_3_write(control_bit);
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timer.delay_us(100);
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// println!(
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// "data[0] = {:#012b} data[1] = {:#012b}",
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// csr::cxp::rxdata_0_read(),
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// csr::cxp::rxdata_1_read(),
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// );
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println!(
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println!(
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"data[0] = {:#04x} control bit = {:#b} encoded = {:#012b}",
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"decoded_data[0] = {:#04x} decoded_k[0] = {:#b} decoded_data[1] = {:#04x} decoded_k[1] = {:#b}",
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csr::cxp::downconn_data_0_read(),
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csr::cxp::downconn_decoded_data_0_read(),
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csr::cxp::downconn_control_bit_0_read(),
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csr::cxp::downconn_decoded_k_0_read(),
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csr::cxp::downconn_encoded_0_read(),
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csr::cxp::downconn_decoded_data_1_read(),
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csr::cxp::downconn_decoded_k_1_read(),
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);
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);
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println!(
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"data[1] = {:#04x} control bit = {:#b} encoded = {:#012b}",
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csr::cxp::downconn_data_1_read(),
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csr::cxp::downconn_control_bit_1_read(),
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csr::cxp::downconn_encoded_1_read(),
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);
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for _ in 0..20 {
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timer.delay_us(100);
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// println!(
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// "data[0] = {:#012b} data[1] = {:#012b}",
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// csr::cxp::rxdata_0_read(),
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// csr::cxp::rxdata_1_read(),
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// );
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println!(
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"decoded_data[0] = {:#04x} decoded_k[0] = {:#b} decoded_data[1] = {:#04x} decoded_k[1] = {:#b}",
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csr::cxp::downconn_decoded_data_0_read(),
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csr::cxp::downconn_decoded_k_0_read(),
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csr::cxp::downconn_decoded_data_1_read(),
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csr::cxp::downconn_decoded_k_1_read(),
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);
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}
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}
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}
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}
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}
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}
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}
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pub fn change_linerate() {
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pub fn setup(timer: &mut GlobalTimer, speed: CXP_SPEED) {
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unsafe {
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info!("turning on pmc loopback mode...");
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csr::cxp::downconn_loopback_mode_write(0b010); // Near-End PMA Loopback
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// QPLL setup
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csr::cxp::downconn_qpll_reset_write(1);
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info!("waiting for QPLL/CPLL to lock...");
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while csr::cxp::downconn_qpll_locked_read() != 1 {}
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info!("QPLL locked");
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// tx/rx setup
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csr::cxp::downconn_tx_start_init_write(1);
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csr::cxp::downconn_rx_start_init_write(1);
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info!("waiting for tx setup...");
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timer.delay_us(50_000);
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info!(
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"tx_phaligndone = {} | rx_phaligndone = {}",
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csr::cxp::downconn_txinit_phaligndone_read(),
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csr::cxp::downconn_rxinit_phaligndone_read(),
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);
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}
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change_linerate(timer, speed);
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loopback_testing(timer, 0x00, 0);
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}
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pub fn change_linerate(timer: &mut GlobalTimer, speed: CXP_SPEED) {
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// TODO: switch QPLL divider for RXUSRCLK
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// TODO: switch QPLL divider for RXUSRCLK
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// TODO: switch TX/RXDIV via TX/RXRATE
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// TODO: set TX/RXDIV via TX/RXRATE
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// no need for DRP for this
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change_qpll_settings(speed);
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// TODO: switch pll for TXUSRCLK = freq(linerate)/20
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unsafe {
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// TODO: reset tx&rx for phase alignment
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csr::cxp::downconn_qpll_reset_write(1);
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info!("waiting for QPLL/CPLL to lock...");
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while csr::cxp::downconn_qpll_locked_read() != 1 {}
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info!("QPLL locked");
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}
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// DEBUG: DRP pll for TXUSRCLK = freq(linerate)/20
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let settings = txusrclk::get_txusrclk_config(speed);
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txusrclk::setup(timer, settings);
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// reset tx&rx for phase alignment
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unsafe {
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// csr::cxp::downconn_tx_restart_write(1); // <--- NOTE: changing TXRATE will do reset automatically, no need to manually reset
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csr::cxp::downconn_rx_restart_write(1); // <--- NOTE: this doesn't do anything atm
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}
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}
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fn change_qpll_settings(speed: CXP_SPEED) {
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let divider = match speed {
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CXP_SPEED::CXP_1 => 0b100, // Divided by 8
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CXP_SPEED::CXP_2 | CXP_SPEED::CXP_3 => 0b011, // Divided by 4
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CXP_SPEED::CXP_5 | CXP_SPEED::CXP_6 => 0b010, // Divided by 2
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CXP_SPEED::CXP_10 | CXP_SPEED::CXP_12 => 0b010, // Divided by 1
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};
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unsafe {
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csr::cxp::downconn_rx_div_write(divider);
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csr::cxp::downconn_tx_div_write(divider);
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}
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}
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pub mod txusrclk {
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use super::*;
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pub struct PLLSetting {
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pub clkout0_reg1: u16, //0x08
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pub clkout0_reg2: u16, //0x09
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pub clkfbout_reg1: u16, //0x14
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pub clkfbout_reg2: u16, //0x15
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pub div_reg: u16, //0x16
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pub lock_reg1: u16, //0x18
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pub lock_reg2: u16, //0x19
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pub lock_reg3: u16, //0x1A
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pub power_reg: u16, //0x28
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pub filt_reg1: u16, //0x4E
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pub filt_reg2: u16, //0x4F
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}
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fn one_clock_cycle() {
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unsafe {
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csr::cxp::downconn_pll_dclk_write(1);
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csr::cxp::downconn_pll_dclk_write(0);
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}
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}
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fn set_addr(address: u8) {
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unsafe {
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csr::cxp::downconn_pll_daddr_write(address);
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}
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}
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fn set_data(value: u16) {
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unsafe {
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csr::cxp::downconn_pll_din_write(value);
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}
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}
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fn set_enable(en: bool) {
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unsafe {
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let val = if en { 1 } else { 0 };
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csr::cxp::downconn_pll_den_write(val);
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}
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}
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fn set_write_enable(en: bool) {
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unsafe {
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let val = if en { 1 } else { 0 };
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csr::cxp::downconn_pll_dwen_write(val);
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}
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}
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fn get_data() -> u16 {
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unsafe { csr::cxp::downconn_pll_dout_read() }
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}
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fn drp_ready() -> bool {
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unsafe { csr::cxp::downconn_pll_dready_read() == 1 }
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}
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#[allow(dead_code)]
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fn read(address: u8) -> u16 {
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set_addr(address);
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set_enable(true);
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// Set DADDR on the mmcm and assert DEN for one clock cycle
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one_clock_cycle();
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set_enable(false);
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while !drp_ready() {
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// keep the clock signal until data is ready
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one_clock_cycle();
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}
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get_data()
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}
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fn write(address: u8, value: u16) {
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set_addr(address);
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set_data(value);
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set_write_enable(true);
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set_enable(true);
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// Set DADDR, DI on the mmcm and assert DWE, DEN for one clock cycle
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one_clock_cycle();
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set_write_enable(false);
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set_enable(false);
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while !drp_ready() {
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// keep the clock signal until write is finished
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one_clock_cycle();
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}
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}
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fn reset(rst: bool) {
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unsafe {
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let val = if rst { 1 } else { 0 };
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csr::cxp::downconn_txpll_reset_write(val)
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}
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}
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pub fn setup(timer: &mut GlobalTimer, settings: PLLSetting) {
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if false {
|
||||||
|
info!("0x08 = {:#06x}", read(0x08));
|
||||||
|
info!("0x09 = {:#06x}", read(0x09));
|
||||||
|
info!("0x14 = {:#06x}", read(0x14));
|
||||||
|
info!("0x15 = {:#06x}", read(0x15));
|
||||||
|
info!("0x16 = {:#06x}", read(0x16));
|
||||||
|
info!("0x18 = {:#06x}", read(0x18));
|
||||||
|
info!("0x19 = {:#06x}", read(0x19));
|
||||||
|
info!("0x1A = {:#06x}", read(0x1A));
|
||||||
|
info!("0x28 = {:#06x}", read(0x28));
|
||||||
|
info!("0x4E = {:#06x}", read(0x4E));
|
||||||
|
info!("0x4F = {:#06x}", read(0x4F));
|
||||||
|
} else {
|
||||||
|
// Based on "DRP State Machine" from XAPP888
|
||||||
|
// hold reset HIGH during pll config
|
||||||
|
reset(true);
|
||||||
|
write(0x08, settings.clkout0_reg1);
|
||||||
|
write(0x09, settings.clkout0_reg2);
|
||||||
|
write(0x14, settings.clkfbout_reg1);
|
||||||
|
write(0x15, settings.clkfbout_reg2);
|
||||||
|
write(0x16, settings.div_reg);
|
||||||
|
write(0x18, settings.lock_reg1);
|
||||||
|
write(0x19, settings.lock_reg2);
|
||||||
|
write(0x1A, settings.lock_reg3);
|
||||||
|
write(0x28, settings.power_reg);
|
||||||
|
write(0x4E, settings.filt_reg1);
|
||||||
|
write(0x4F, settings.filt_reg2);
|
||||||
|
reset(false);
|
||||||
|
|
||||||
|
// wait for the pll to lock
|
||||||
|
timer.delay_us(100);
|
||||||
|
|
||||||
|
let locked = unsafe { csr::cxp::downconn_txpll_locked_read() == 1 };
|
||||||
|
info!("txusrclk locked = {}", locked);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
pub fn get_txusrclk_config(speed: CXP_SPEED) -> PLLSetting {
|
||||||
|
match speed {
|
||||||
|
CXP_SPEED::CXP_1 => {
|
||||||
|
// CLKFBOUT_MULT = 8, DIVCLK_DIVIDE = 1 , CLKOUT0_DIVIDE = 16
|
||||||
|
// TXUSRCLK=62.5MHz
|
||||||
|
PLLSetting {
|
||||||
|
clkout0_reg1: 0x1208, //0x08
|
||||||
|
clkout0_reg2: 0x0000, //0x09
|
||||||
|
clkfbout_reg1: 0x1104, //0x14
|
||||||
|
clkfbout_reg2: 0x0000, //0x15
|
||||||
|
div_reg: 0x1041, //0x16
|
||||||
|
lock_reg1: 0x03e8, //0x18
|
||||||
|
lock_reg2: 0x5801, //0x19
|
||||||
|
lock_reg3: 0xdbe9, //0x1A
|
||||||
|
power_reg: 0x0000, //0x28
|
||||||
|
filt_reg1: 0x9808, //0x4E
|
||||||
|
filt_reg2: 0x9100, //0x4F
|
||||||
|
}
|
||||||
|
}
|
||||||
|
CXP_SPEED::CXP_2 => {
|
||||||
|
// CLKFBOUT_MULT = 8, DIVCLK_DIVIDE = 1 , CLKOUT0_DIVIDE = 8
|
||||||
|
// TXUSRCLK=125MHz
|
||||||
|
PLLSetting {
|
||||||
|
clkout0_reg1: 0x1104, //0x08
|
||||||
|
clkout0_reg2: 0x0000, //0x09
|
||||||
|
clkfbout_reg1: 0x1104, //0x14
|
||||||
|
clkfbout_reg2: 0x0000, //0x15
|
||||||
|
div_reg: 0x1041, //0x16
|
||||||
|
lock_reg1: 0x03e8, //0x18
|
||||||
|
lock_reg2: 0x5801, //0x19
|
||||||
|
lock_reg3: 0xdbe9, //0x1A
|
||||||
|
power_reg: 0x0000, //0x28
|
||||||
|
filt_reg1: 0x9808, //0x4E
|
||||||
|
filt_reg2: 0x9100, //0x4F
|
||||||
|
}
|
||||||
|
}
|
||||||
|
CXP_SPEED::CXP_3 => {
|
||||||
|
// CLKFBOUT_MULT = 10, DIVCLK_DIVIDE = 1 , CLKOUT0_DIVIDE = 8
|
||||||
|
// TXUSRCLK=125MHz
|
||||||
|
PLLSetting {
|
||||||
|
clkout0_reg1: 0x1104, //0x08
|
||||||
|
clkout0_reg2: 0x0000, //0x09
|
||||||
|
clkfbout_reg1: 0x1145, //0x14
|
||||||
|
clkfbout_reg2: 0x0000, //0x15
|
||||||
|
div_reg: 0x1041, //0x16
|
||||||
|
lock_reg1: 0x03e8, //0x18
|
||||||
|
lock_reg2: 0x7001, //0x19
|
||||||
|
lock_reg3: 0xf3e9, //0x1A
|
||||||
|
power_reg: 0x0000, //0x28
|
||||||
|
filt_reg1: 0x9908, //0x4E
|
||||||
|
filt_reg2: 0x1900, //0x4F
|
||||||
|
}
|
||||||
|
}
|
||||||
|
CXP_SPEED::CXP_5 => {
|
||||||
|
// CLKFBOUT_MULT = 8, DIVCLK_DIVIDE = 1 , CLKOUT0_DIVIDE = 4
|
||||||
|
// TXUSRCLK=250MHz
|
||||||
|
PLLSetting {
|
||||||
|
clkout0_reg1: 0x1082, //0x08
|
||||||
|
clkout0_reg2: 0x0000, //0x09
|
||||||
|
clkfbout_reg1: 0x1104, //0x14
|
||||||
|
clkfbout_reg2: 0x0000, //0x15
|
||||||
|
div_reg: 0x1041, //0x16
|
||||||
|
lock_reg1: 0x03e8, //0x18
|
||||||
|
lock_reg2: 0x5801, //0x19
|
||||||
|
lock_reg3: 0xdbe9, //0x1A
|
||||||
|
power_reg: 0x0000, //0x28
|
||||||
|
filt_reg1: 0x9808, //0x4E
|
||||||
|
filt_reg2: 0x9100, //0x4F
|
||||||
|
}
|
||||||
|
}
|
||||||
|
CXP_SPEED::CXP_6 => {
|
||||||
|
// CLKFBOUT_MULT = 10, DIVCLK_DIVIDE = 1 , CLKOUT0_DIVIDE = 4
|
||||||
|
// TXUSRCLK=312.5MHz
|
||||||
|
PLLSetting {
|
||||||
|
clkout0_reg1: 0x1082, //0x08
|
||||||
|
clkout0_reg2: 0x0000, //0x09
|
||||||
|
clkfbout_reg1: 0x1145, //0x14
|
||||||
|
clkfbout_reg2: 0x0000, //0x15
|
||||||
|
div_reg: 0x1041, //0x16
|
||||||
|
lock_reg1: 0x03e8, //0x18
|
||||||
|
lock_reg2: 0x7001, //0x19
|
||||||
|
lock_reg3: 0xf3e9, //0x1A
|
||||||
|
power_reg: 0x0000, //0x28
|
||||||
|
filt_reg1: 0x9908, //0x4E
|
||||||
|
filt_reg2: 0x1900, //0x4F
|
||||||
|
}
|
||||||
|
}
|
||||||
|
CXP_SPEED::CXP_10 => {
|
||||||
|
// CLKFBOUT_MULT = 8, DIVCLK_DIVIDE = 1 , CLKOUT0_DIVIDE = 2
|
||||||
|
// TXUSRCLK=500MHz
|
||||||
|
PLLSetting {
|
||||||
|
clkout0_reg1: 0x1041, //0x08
|
||||||
|
clkout0_reg2: 0x0000, //0x09
|
||||||
|
clkfbout_reg1: 0x1104, //0x14
|
||||||
|
clkfbout_reg2: 0x0000, //0x15
|
||||||
|
div_reg: 0x1041, //0x16
|
||||||
|
lock_reg1: 0x03e8, //0x18
|
||||||
|
lock_reg2: 0x5801, //0x19
|
||||||
|
lock_reg3: 0xdbe9, //0x1A
|
||||||
|
power_reg: 0x0000, //0x28
|
||||||
|
filt_reg1: 0x9808, //0x4E
|
||||||
|
filt_reg2: 0x9100, //0x4F
|
||||||
|
}
|
||||||
|
}
|
||||||
|
CXP_SPEED::CXP_12 => {
|
||||||
|
// CLKFBOUT_MULT = 10, DIVCLK_DIVIDE = 1 , CLKOUT0_DIVIDE = 2
|
||||||
|
// TXUSRCLK=625MHz
|
||||||
|
PLLSetting {
|
||||||
|
clkout0_reg1: 0x1041, //0x08
|
||||||
|
clkout0_reg2: 0x0000, //0x09
|
||||||
|
clkfbout_reg1: 0x1145, //0x14
|
||||||
|
clkfbout_reg2: 0x0000, //0x15
|
||||||
|
div_reg: 0x1041, //0x16
|
||||||
|
lock_reg1: 0x03e8, //0x18
|
||||||
|
lock_reg2: 0x7001, //0x19
|
||||||
|
lock_reg3: 0xf3e9, //0x1A
|
||||||
|
power_reg: 0x0000, //0x28
|
||||||
|
filt_reg1: 0x9908, //0x4E
|
||||||
|
filt_reg2: 0x1900, //0x4F
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue