forked from M-Labs/artiq-zynq
kasli_soc: fix si5324 pins routed to GTX
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f9a8c76654
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def4d989cd
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@ -217,7 +217,7 @@ class GenericMaster(SoCCore):
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data_pads = [platform.request("sfp", i) for i in range(4)]
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data_pads = [platform.request("sfp", i) for i in range(4)]
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self.submodules.drtio_transceiver = gtx_7series.GTX(
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self.submodules.drtio_transceiver = gtx_7series.GTX(
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clock_pads=platform.request("clk125_gtp"),
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clock_pads=platform.request("clk_gtp"),
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pads=data_pads,
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pads=data_pads,
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sys_clk_freq=sys_clk_freq)
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sys_clk_freq=sys_clk_freq)
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self.csr_devices.append("drtio_transceiver")
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self.csr_devices.append("drtio_transceiver")
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@ -345,7 +345,7 @@ class GenericSatellite(SoCCore):
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data_pads = [platform.request("sfp", i) for i in range(4)]
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data_pads = [platform.request("sfp", i) for i in range(4)]
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self.submodules.drtio_transceiver = gtx_7series.GTX(
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self.submodules.drtio_transceiver = gtx_7series.GTX(
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clock_pads=platform.request("clk125_gtp"),
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clock_pads=platform.request("clk_gtp"),
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pads=data_pads,
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pads=data_pads,
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sys_clk_freq=sys_clk_freq)
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sys_clk_freq=sys_clk_freq)
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self.csr_devices.append("drtio_transceiver")
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self.csr_devices.append("drtio_transceiver")
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