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frameline GW: update some timinig

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morgan 2025-01-15 16:27:24 +08:00
parent 7c51eb3de9
commit dd75394ed3
1 changed files with 18 additions and 15 deletions
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33
src/gateware/cxp_frame_pipeline.py
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@ -4,8 +4,8 @@ from misoc.interconnect.csr import *
from misoc.interconnect import stream from misoc.interconnect import stream
from misoc.cores.liteeth_mini.mac.crc import LiteEthMACCRCEngine from misoc.cores.liteeth_mini.mac.crc import LiteEthMACCRCEngine
# from cxp_pipeline import * from cxp_pipeline import *
from src.gateware.cxp_pipeline import * # for sim only # from src.gateware.cxp_pipeline import * # for sim only
from types import SimpleNamespace from types import SimpleNamespace
from math import lcm from math import lcm
@ -574,7 +574,11 @@ class Pixel_Coordinate_Tracker(Module):
x_4x = [Signal(len(self.pixel4x[0].x), reset=i) for i in range(4)] x_4x = [Signal(len(self.pixel4x[0].x), reset=i) for i in range(4)]
y_r = Signal(len(self.pixel4x[0].y)) y_r = Signal(len(self.pixel4x[0].y))
self.sync += self.sink.ack.eq(1), y_max = Signal.like(self.y_size)
self.sync += [
self.sink.ack.eq(1),
y_max.eq(self.y_size - 1),
]
for i, (x_r, pix) in enumerate(zip(x_4x, self.pixel4x)): for i, (x_r, pix) in enumerate(zip(x_4x, self.pixel4x)):
self.sync += [ self.sync += [
pix.stb.eq(0), pix.stb.eq(0),
@ -584,8 +588,8 @@ class Pixel_Coordinate_Tracker(Module):
# new line # new line
x_r.eq(x_r.reset), x_r.eq(x_r.reset),
If(y_r == self.y_size - 1, If(y_r == y_max,
pix.eof.eq(y_r == self.y_size - 1), pix.eof.eq(1),
y_r.eq(0), y_r.eq(0),
).Else( ).Else(
y_r.eq(y_r + 1), y_r.eq(y_r + 1),
@ -606,7 +610,6 @@ class ROI(Module):
rectangular region of interest, and reports the total. rectangular region of interest, and reports the total.
""" """
def __init__(self, pixel_4x, count_width): def __init__(self, pixel_4x, count_width):
assert count_width <= 32
assert len(pixel_4x) == 4 assert len(pixel_4x) == 4
self.cfg = Record([ self.cfg = Record([
@ -635,12 +638,6 @@ class ROI(Module):
])) ]))
# x_good = [Signal() for _ in range(4)]
# y_good = [Signal() for _ in range(4)]
# gray = [Signal(len(pixel_4x[0].gray)) for _ in range(4)]
# stb = [Signal() for _ in range(4)]
# count = [Signal(count_len) for _ in range(4)]
for pix, roi in zip(pixel_4x, self.roi_4x): for pix, roi in zip(pixel_4x, self.roi_4x):
self.sync += [ self.sync += [
# stage 1 - generate "good" (in-ROI) signals # stage 1 - generate "good" (in-ROI) signals
@ -673,15 +670,21 @@ class ROI(Module):
] ]
eof = Signal() eof = Signal()
eof_buf = Signal()
count_buf = [Signal(count_width), Signal(count_width)]
# stage 3 - update # stage 3 - update
self.sync += [ self.sync += [
eof.eq(reduce(or_, [pix.eof for pix in pixel_4x])), eof.eq(reduce(or_, [pix.eof for pix in pixel_4x])),
eof_buf.eq(eof),
count_buf[0].eq(self.roi_4x[0].count + self.roi_4x[1].count),
count_buf[1].eq(self.roi_4x[2].count + self.roi_4x[3].count),
self.out.update.eq(0), self.out.update.eq(0),
If(eof, If(eof_buf,
[roi.count.eq(0) for roi in self.roi_4x], [roi.count.eq(0) for roi in self.roi_4x],
self.out.update.eq(1), self.out.update.eq(1),
self.out.count.eq(reduce(add, [roi.count for roi in self.roi_4x])) self.out.count.eq(reduce(add, count_buf))
) )
] ]
@ -740,7 +743,7 @@ class Pixel_Parser(Module):
class ROI_Pipeline(Module): class Pixel_Pipeline(Module):
def __init__(self, res_width, count_width): def __init__(self, res_width, count_width):
# NOTE: csr need to stay outside since this module need to be cdr in the CXP_FRAME_Pipeline module # NOTE: csr need to stay outside since this module need to be cdr in the CXP_FRAME_Pipeline module