morgan/artiq-zynq
1
0
Fork 0
forked from M-Labs/artiq-zynq
Code Pull Requests Activity

cxp GW: update docs

Browse Source
This commit is contained in:
morgan 2025-02-07 15:03:22 +08:00
parent 65cc7f0902
commit dd5a71517b
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/gateware/cxp.py
View File

@ -287,7 +287,7 @@ class CXP_Frame_Pipeline(Module, AutoCSR):
class CXP_Grabber(Module, AutoCSR): class CXP_Grabber(Module, AutoCSR):
# optimal stream packet size is 2 KiB - Section 9.5.2 (CXP-001-2021) # optimal stream packet size is 2 KiB - Section 9.5.2 (CXP-001-2021)
def __init__(self, host, roi_engine_count=8, res_width=16, count_width=31): def __init__(self, host, roi_engine_count=1, res_width=16, count_width=31):
assert count_width <= 31 assert count_width <= 31
self.crc_error = CSR() self.crc_error = CSR()
@ -319,7 +319,7 @@ class CXP_Grabber(Module, AutoCSR):
# select which roi engine can output rtio_input signal # select which roi engine can output rtio_input signal
self.gate_data = rtlink.Interface( self.gate_data = rtlink.Interface(
rtlink.OInterface(roi_engine_count), rtlink.OInterface(roi_engine_count),
# the 32th bits is for sentinel (gate detection) # the extra MSB bits is for sentinel
rtlink.IInterface(count_width+1, timestamped=False) rtlink.IInterface(count_width+1, timestamped=False)
) )