diff --git a/src/gateware/cxp.py b/src/gateware/cxp.py
index d0686f6..8442845 100644
--- a/src/gateware/cxp.py
+++ b/src/gateware/cxp.py
@@ -1,4 +1,5 @@
 from migen import *
+from migen.genlib.cdc import MultiReg, PulseSynchronizer
 from misoc.interconnect.csr import *
 
 from cxp_downconn import CXP_DownConn_PHYS
@@ -180,34 +181,48 @@ class DownConn_Interface(Module, AutoCSR):
         # PHY ---/---> CDC FIFO ---/---> trigger ack ------> packet  ------> debug buffer
         #                                checker             decoder
         #
-        self.submodules.trig_ack_checker = trig_ack_checker = CXP_Trig_Ack_Checker()
-        self.submodules.packet_decoder = packet_decoder = CXP_Data_Packet_Decode()
+        cdr = ClockDomainsRenamer("cxp_gtx_rx")
+
+        # Priority level 1 packet - Trigger ack packet
+        self.submodules.trig_ack_checker = trig_ack_checker = cdr(CXP_Trig_Ack_Checker())
+        
+        self.submodules.trig_ack_ps = trig_ack_ps = PulseSynchronizer("cxp_gtx_rx", "sys")
+        self.comb += trig_ack_ps.i.eq(trig_ack_checker.ack)
 
         self.trig_ack = Signal()
         self.trig_clr = Signal()
-
         # Error are latched
         self.sync += [
-            If(trig_ack_checker.ack,
+            If(trig_ack_ps.o,
                 self.trig_ack.eq(1),
             ).Elif(self.trig_clr,
                 self.trig_ack.eq(0),
             ),
         ]
 
+        # Priority level 2 packet - data, test packet
+        self.submodules.packet_decoder = packet_decoder = cdr(CXP_Data_Packet_Decode())
+
+        self.submodules.decode_err_ps = decode_err_ps = PulseSynchronizer("cxp_gtx_rx", "sys")
+        self.submodules.test_err_ps = test_err_ps = PulseSynchronizer("cxp_gtx_rx", "sys")
+        self.comb += [
+            decode_err_ps.i.eq(packet_decoder.decode_err),
+            test_err_ps.i.eq(packet_decoder.test_err),
+        ]
+
         self.packet_type = CSRStatus(8)
         self.decoder_error = CSR()
         self.test_error = CSR()
         # self.read_pointer = CSR()
 
-        self.comb += self.packet_type.status.eq(packet_decoder.packet_type_rx),
+        self.specials += MultiReg(packet_decoder.packet_type, self.packet_type.status)
         self.sync += [
-            If(packet_decoder.decode_err_rx,
+            If(decode_err_ps.o,
                self.decoder_error.w.eq(1),
             ).Elif(self.decoder_error.re,
                self.decoder_error.w.eq(0),
             ),
-            If(packet_decoder.test_err_rx,
+            If(test_err_ps.o,
                 self.test_error.w.eq(1),
             ).Elif(self.test_error.re,
                 self.test_error.w.eq(0),
@@ -226,7 +241,7 @@ class DownConn_Interface(Module, AutoCSR):
         self.submodules.debug_out = debug_out = RX_Debug_Buffer()
 
         # TODO: move the rx pipeline to cxp_gtx_rx clockdomain
-        rx_pipeline = [phy, cdc_fifo, trig_ack_checker, packet_decoder, debug_out]
+        rx_pipeline = [phy, trig_ack_checker, packet_decoder, cdc_fifo, debug_out]
         for s, d in zip(rx_pipeline, rx_pipeline[1:]):
             self.comb += s.source.connect(d.sink)
         
@@ -244,7 +259,7 @@ class DownConn_Interface(Module, AutoCSR):
 
         self.specials += [
             # # pmod 0-7 pin
-            Instance("OBUF", i_I=packet_decoder.test_err_rx, o_O=pmod_pads[0]),
+            Instance("OBUF", i_I=packet_decoder.test_err, o_O=pmod_pads[0]),
             Instance("OBUF", i_I=pak_start, o_O=pmod_pads[1]),
             # Instance("OBUF", i_I=fifo_in.source.ack, o_O=pmod_pads[2]),
             # Instance("OBUF", i_I=gtx.comma_checker.aligner_en, o_O=pmod_pads[3]),