From da9d43e6750bda2ef0853737f20d267a159972ce Mon Sep 17 00:00:00 2001 From: morgan Date: Wed, 2 Oct 2024 17:42:15 +0800 Subject: [PATCH] cxp GW: add back cdc fifo --- src/gateware/cxp.py | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/gateware/cxp.py b/src/gateware/cxp.py index fdccef3..d0686f6 100644 --- a/src/gateware/cxp.py +++ b/src/gateware/cxp.py @@ -180,7 +180,6 @@ class DownConn_Interface(Module, AutoCSR): # PHY ---/---> CDC FIFO ---/---> trigger ack ------> packet ------> debug buffer # checker decoder # - self.submodules.debug_out = debug_out = RX_Debug_Buffer() self.submodules.trig_ack_checker = trig_ack_checker = CXP_Trig_Ack_Checker() self.submodules.packet_decoder = packet_decoder = CXP_Data_Packet_Decode() @@ -221,8 +220,13 @@ class DownConn_Interface(Module, AutoCSR): ] + # DEBUG: remove this cdc fifo + cdc_fifo = stream.AsyncFIFO(word_layout, 512) + self.submodules += ClockDomainsRenamer({"write": "cxp_gtx_rx", "read": "sys"})(cdc_fifo) + self.submodules.debug_out = debug_out = RX_Debug_Buffer() + # TODO: move the rx pipeline to cxp_gtx_rx clockdomain - rx_pipeline = [phy, trig_ack_checker, packet_decoder, debug_out] + rx_pipeline = [phy, cdc_fifo, trig_ack_checker, packet_decoder, debug_out] for s, d in zip(rx_pipeline, rx_pipeline[1:]): self.comb += s.source.connect(d.sink)