forked from M-Labs/artiq-zynq
cxp: add trig to upconn & remove tx_command_packet
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parent
6d421a1041
commit
d84c7c9523
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@ -8,8 +8,6 @@ from cxp_pipeline import *
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class CXP(Module, AutoCSR):
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def __init__(self, refclk, downconn_pads, upconn_pads, sys_clk_freq, debug_sma, pmod_pads):
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self.submodules.trig = TX_Trigger(cxp_phy_layout())
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self.submodules.upconn = UpConn_Interface(upconn_pads, sys_clk_freq, debug_sma, pmod_pads)
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self.submodules.downconn = CXP_DownConn(refclk, downconn_pads, sys_clk_freq, debug_sma, pmod_pads)
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@ -17,9 +15,6 @@ class CXP(Module, AutoCSR):
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# TODO: add link layer
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# TODO: remove this and put it in upconn_interface
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def cxp_phy_layout():
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return [("data", 8), ("k", 1)]
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class UpConn_Interface(Module, AutoCSR):
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def __init__(self, upconn_pads, sys_clk_freq, debug_sma, pmod_pads, fifos_depth=64):
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@ -31,7 +26,9 @@ class UpConn_Interface(Module, AutoCSR):
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# # #
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self.submodules.upconn_phy = upconn_phy = CXP_UpConn_PHY(upconn_pads, sys_clk_freq, debug_sma, pmod_pads, cxp_phy_layout(), fifos_depth)
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layout = [("data", 8), ("k", 1)]
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self.submodules.upconn_phy = upconn_phy = CXP_UpConn_PHY(upconn_pads, sys_clk_freq, debug_sma, pmod_pads, layout, fifos_depth)
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self.sync += [
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upconn_phy.bitrate2x_enable.eq(self.bitrate2x_enable.storage),
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@ -45,7 +42,35 @@ class UpConn_Interface(Module, AutoCSR):
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# Packet FIFOs with transmission priority
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# 0: Trigger packet
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# NOTE: 0 Trigger packet
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self.submodules.trig = trig = TX_Trigger(layout)
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# DEBUG: INPUT
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self.trig_stb = CSR()
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self.trig_delay = CSRStorage(8)
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self.linktrigger = CSRStorage(2)
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self.sync += [
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trig.trig_stb.eq(self.trig_stb.re),
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trig.delay.eq(self.trig_delay.storage),
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trig.linktrig_mode.eq(self.linktrigger.storage),
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]
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# DEBUG: OUTPUT
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self.submodules.trig_out = trig_out = stream.SyncFIFO(layout, 64)
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self.comb += trig.source.connect(trig_out.sink)
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self.trig_inc = CSR()
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self.trig_dout_pak = CSRStatus(8)
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self.trig_kout_pak = CSRStatus()
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self.trig_dout_valid = CSRStatus()
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self.sync += [
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# output
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trig_out.source.ack.eq(self.trig_inc.re),
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self.trig_dout_pak.status.eq(trig_out.source.data),
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self.trig_kout_pak.status.eq(trig_out.source.k),
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self.trig_dout_valid.status.eq(trig_out.source.stb),
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]
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self.symbol0 = CSR(9)
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self.sync += [
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@ -55,9 +80,9 @@ class UpConn_Interface(Module, AutoCSR):
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]
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# 1: IO acknowledgment for trigger packet
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# NOTE: 1 IO acknowledgment for trigger packet
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self.submodules.trig_ack = trig_ack = Trigger_ACK(cxp_phy_layout())
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self.submodules.trig_ack = trig_ack = Trigger_ACK(layout)
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# DEBUG: INPUT
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self.ack = CSR()
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@ -66,7 +91,7 @@ class UpConn_Interface(Module, AutoCSR):
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]
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# DEBUG: OUTPUT
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self.submodules.trig_ack_out = trig_ack_out = stream.SyncFIFO(cxp_phy_layout(), 64)
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self.submodules.trig_ack_out = trig_ack_out = stream.SyncFIFO(layout, 64)
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self.comb += trig_ack.source.connect(trig_ack_out.sink)
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self.trig_ack_inc = CSR()
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self.trig_ack_dout_pak = CSRStatus(8)
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@ -88,7 +113,7 @@ class UpConn_Interface(Module, AutoCSR):
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upconn_phy.tx_fifos.sink[1].k.eq(self.symbol1.r[8]),
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]
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# 2: All other packets
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# NOTE: 2 All other packets
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# Control is not timing dependent, all the link layer is done in firmware
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# Table 54 (CXP-001-2021)
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@ -99,11 +124,11 @@ class UpConn_Interface(Module, AutoCSR):
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# section 9.6.1.2 (CXP-001-2021)
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# tags implementation is on firmware
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self.submodules.command = command = TX_Command_Packet(pmod_pads)
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self.submodules.command = command = TX_Command_Packet(layout, pmod_pads)
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# DEBUG: OUTPUT
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self.submodules.command_out = command_out = stream.SyncFIFO(cxp_phy_layout(), 64)
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self.submodules.command_out = command_out = stream.SyncFIFO(layout, 64)
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self.comb += command.source.connect(command_out.sink)
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self.command_inc = CSR()
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@ -138,129 +163,3 @@ class UpConn_Interface(Module, AutoCSR):
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upconn_phy.tx_fifos.sink[2].data.eq(self.symbol2.r[:8]),
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upconn_phy.tx_fifos.sink[2].k.eq(self.symbol2.r[8]),
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]
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def K(x, y):
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return ((y << 5) | x)
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# TODO: move this to cxp_pipeline, since it used K(x, y) :<
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class TX_Trigger(Module, AutoCSR):
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def __init__(self, layout):
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# This module is mostly control by gateware
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self.trig_stb = Signal()
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self.delay = Signal(8) # FIXME: use source instead
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self.linktrig_mode = Signal(max=4)
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# # #
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self.submodules.code_src = code_src = Code_Source(layout, counts=3)
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self.comb += [
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code_src.stb.eq(self.trig_stb),
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code_src.data.eq(self.delay),
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code_src.k.eq(0)
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]
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self.submodules.inserter_once = inserter_once = Code_Inserter(layout, counts=1)
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self.submodules.inserter_twice = inserter_twice = Code_Inserter(layout, counts=2)
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self.comb += [
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inserter_once.k.eq(1),
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inserter_twice.k.eq(1),
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If((self.linktrig_mode == 0) | (self.linktrig_mode == 2),
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inserter_once.data.eq(K(28, 2)),
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inserter_twice.data.eq(K(28, 4)),
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).Else(
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inserter_once.data.eq(K(28, 4)),
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inserter_twice.data.eq(K(28, 2)),
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)
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]
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self.submodules.buf_out = buf_out = stream.SyncFIFO(layout, 64)
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tx_pipeline = [ code_src, inserter_twice, inserter_once, buf_out]
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for s, d in zip(tx_pipeline, tx_pipeline[1:]):
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self.comb += s.source.connect(d.sink)
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self.source = tx_pipeline[-1].source
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# DEBUG: INPUT
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self.stb = CSR()
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self.trig_delay = CSRStorage(8)
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self.linktrigger = CSRStorage(2)
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self.sync += [
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self.trig_stb.eq(self.stb.re),
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self.delay.eq(self.trig_delay.storage),
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self.linktrig_mode.eq(self.linktrigger.storage),
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]
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# DEBUG: OUTPUT
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self.inc = CSR()
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self.dout_pak = CSRStatus(8)
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self.kout_pak = CSRStatus()
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self.dout_valid = CSRStatus()
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self.sync += [
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# output
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buf_out.source.ack.eq(self.inc.re),
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self.dout_pak.status.eq(buf_out.source.data),
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self.kout_pak.status.eq(buf_out.source.k),
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self.dout_valid.status.eq(buf_out.source.stb),
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]
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class TX_Command_Packet(Module, AutoCSR):
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def __init__(self, pmod_pads):
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self.packet_type = CSRStorage(8)
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self.din_len = CSRStorage(6)
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self.din_data = CSR(8)
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self.din_k = CSRStorage()
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self.din_ready = CSRStatus()
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# # #
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# a buf is used to simulated a proper endpoint which hold source.stb high as long as data is available
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# otherwise, CSR.re only hold when CSR is written to and it cannot act as a proper source
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self.submodules.buf_in = buf_in = stream.SyncFIFO(cxp_phy_layout(), 2)
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self.submodules.crc_inserter = crc_inserters = CXPCRC32Inserter(cxp_phy_layout())
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self.submodules.pak_type = pak_type = Code_Inserter(cxp_phy_layout())
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self.submodules.pak_wrp = pak_wrp = Packet_Wrapper(cxp_phy_layout())
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len = Signal(6, reset=1)
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self.sync += [
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self.din_ready.status.eq(buf_in.sink.ack),
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buf_in.sink.stb.eq(0),
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If(self.din_data.re,
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If(len == self.din_len.storage,
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len.eq(len.reset),
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buf_in.sink.eop.eq(1),
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).Else(
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len.eq(len + 1),
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buf_in.sink.eop.eq(0),
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),
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buf_in.sink.stb.eq(1),
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buf_in.sink.data.eq(self.din_data.r),
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buf_in.sink.k.eq(self.din_k.storage),
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),
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]
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self.comb += [
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pak_type.data.eq(self.packet_type.storage),
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pak_type.k.eq(0),
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]
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tx_pipeline = [ buf_in, crc_inserters, pak_type, pak_wrp]
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for s, d in zip(tx_pipeline, tx_pipeline[1:]):
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self.comb += s.source.connect(d.sink)
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self.source = tx_pipeline[-1].source
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