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upconn GW: clean up

This commit is contained in:
morgan 2024-09-10 12:17:51 +08:00
parent f83afc7195
commit d81c770e54
1 changed files with 23 additions and 32 deletions
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55
src/gateware/cxp_upconn.py
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@ -93,17 +93,21 @@ class SERDES_10bits(Module):
] ]
@ResetInserter() @ResetInserter()
@CEInserter() class Transmit_Scheduler(Module):
class Packets_Scheduler(Module):
def __init__(self, interface, debug_buf): def __init__(self, interface, debug_buf):
self.tx_enable = Signal() self.tx_enable = Signal()
self.oe = Signal() self.oe = Signal()
self.ce = Signal()
# # # # # #
self.submodules.startup_fsm = startup_fsm = FSM(reset_state="WAIT_TX_ENABLE") self.submodules.startup_fsm = startup_fsm = CEInserter()(FSM(reset_state="WAIT_TX_ENABLE"))
self.submodules.encoder = encoder = SingleEncoder(True) self.submodules.encoder = encoder = CEInserter()(SingleEncoder(True))
self.comb += [
startup_fsm.ce.eq(self.ce),
encoder.ce.eq(self.ce),
]
tx_charcount = Signal(max=4) tx_charcount = Signal(max=4)
tx_wordcount = Signal(max=10000) tx_wordcount = Signal(max=10000)
@ -143,8 +147,13 @@ class Packets_Scheduler(Module):
) )
) )
# hold ack for only one sys clk cycle to prevent data loss
for ack in interface.sink_ack:
self.sync += ack.eq(0)
self.sync += [ self.sync += [
If(self.oe, debug_buf.sink_stb.eq(0),
If(self.oe & self.ce,
encoder.disp_in.eq(encoder.disp_out), encoder.disp_in.eq(encoder.disp_out),
If((~interface.pe.n) & (interface.pe.o == 0), If((~interface.pe.n) & (interface.pe.o == 0),
# trigger packets are inserted at char boundary and don't contribute to word count # trigger packets are inserted at char boundary and don't contribute to word count
@ -198,6 +207,7 @@ class Packets_Scheduler(Module):
).Else( ).Else(
tx_charcount.eq(tx_charcount + 1), tx_charcount.eq(tx_charcount + 1),
If(~idling, If(~idling,
tx_wordcount.eq(tx_wordcount + 1),
interface.sink_ack[priorities].eq(1), interface.sink_ack[priorities].eq(1),
encoder.d.eq(interface.sink_data[priorities]), encoder.d.eq(interface.sink_data[priorities]),
encoder.k.eq(interface.sink_k[priorities]), encoder.k.eq(interface.sink_k[priorities]),
@ -226,8 +236,7 @@ class Packets_Scheduler(Module):
class PHY_Interface(Module): class PHY_Interface(Module):
def __init__(self, layout, nsink): def __init__(self, layout, nsink):
sink_stb = Signal(nsink)
self.sink_stb = Signal(nsink)
self.sink_ack = Array(Signal() for _ in range(nsink)) self.sink_ack = Array(Signal() for _ in range(nsink))
self.sink_data = Array(Signal(8) for _ in range(nsink)) self.sink_data = Array(Signal(8) for _ in range(nsink))
self.sink_k = Array(Signal() for _ in range(nsink)) self.sink_k = Array(Signal() for _ in range(nsink))
@ -239,28 +248,19 @@ class PHY_Interface(Module):
sink = stream.Endpoint(layout) sink = stream.Endpoint(layout)
self.sinks += [sink] self.sinks += [sink]
self.sync += [ self.comb += [
If(self.sink_ack[i], sink.ack.eq(self.sink_ack[i]),
# reset ack after asserted sink_stb[i].eq(sink.stb),
# since upconn clk run much slower, the ack will be high for longer than expected which will result in data loss
self.sink_ack[i].eq(0),
sink.ack.eq(1),
).Else(
sink.ack.eq(0),
),
self.sink_stb[i].eq(sink.stb),
self.sink_data[i].eq(sink.data), self.sink_data[i].eq(sink.data),
self.sink_k[i].eq(sink.k), self.sink_k[i].eq(sink.k),
] ]
# FIFOs transmission priority # FIFOs transmission priority
self.submodules.pe = PriorityEncoder(nsink) self.submodules.pe = PriorityEncoder(nsink)
self.comb += self.pe.i.eq(self.sink_stb) self.comb += self.pe.i.eq(sink_stb)
class Debug_buffer(Module,AutoCSR): class Debug_buffer(Module,AutoCSR):
def __init__(self, layout): def __init__(self, layout):
self.sink_stb = Signal() self.sink_stb = Signal()
self.sink_ack = Signal() self.sink_ack = Signal()
self.sink_data = Signal(8) self.sink_data = Signal(8)
@ -271,19 +271,10 @@ class Debug_buffer(Module,AutoCSR):
self.submodules.buf_out = buf_out = stream.SyncFIFO(layout, 128) self.submodules.buf_out = buf_out = stream.SyncFIFO(layout, 128)
self.sync += [ self.sync += [
If(self.sink_stb, buf_out.sink.stb.eq(self.sink_stb),
# reset ack after asserted
# since upconn clk run much slower, the stb will be high for longer than expected which will result in multiple data entry
self.sink_stb.eq(0),
buf_out.sink.stb.eq(1),
).Else(
buf_out.sink.stb.eq(0),
),
self.sink_ack.eq(buf_out.sink.ack), self.sink_ack.eq(buf_out.sink.ack),
buf_out.sink.data.eq(self.sink_data), buf_out.sink.data.eq(self.sink_data),
buf_out.sink.k.eq(self.sink_k), buf_out.sink.k.eq(self.sink_k),
] ]
self.inc = CSR() self.inc = CSR()
@ -318,11 +309,11 @@ class CXP_UpConn_PHY(Module, AutoCSR):
# DEBUG: # DEBUG:
self.submodules.debug_buf = debug_buf = Debug_buffer(layout) self.submodules.debug_buf = debug_buf = Debug_buffer(layout)
self.submodules.scheduler = scheduler = Packets_Scheduler(interface, debug_buf) self.submodules.scheduler = scheduler = Transmit_Scheduler(interface, debug_buf)
self.submodules.serdes = serdes = SERDES_10bits(pad) self.submodules.serdes = serdes = SERDES_10bits(pad)
self.comb += [ self.comb += [
self.tx_busy.eq(interface.sink_stb != 0), self.tx_busy.eq(~interface.pe.n),
cg.reset.eq(self.clk_reset), cg.reset.eq(self.clk_reset),
cg.freq2x_enable.eq(self.bitrate2x_enable), cg.freq2x_enable.eq(self.bitrate2x_enable),