From d73cd459f0f1fb718fe734baa838641457a7c835 Mon Sep 17 00:00:00 2001 From: morgan Date: Tue, 22 Oct 2024 11:44:19 +0800 Subject: [PATCH] downconn GW: connect cxp_gtxi cd downconn GW: clenaup --- src/gateware/cxp_downconn.py | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/src/gateware/cxp_downconn.py b/src/gateware/cxp_downconn.py index 56ad75a..a414ad1 100644 --- a/src/gateware/cxp_downconn.py +++ b/src/gateware/cxp_downconn.py @@ -40,6 +40,15 @@ class CXP_DownConn_PHYS(Module, AutoCSR): # checkout channel interfaces & drtio_gtx # GTPTXPhaseAlignement for inspiration + # Connect slave i's `cxp_gtx_rx` clock to `cxp_gtx_rxi` clock + for rx in self.rx_phys: + name = "cd_cxp_gtx_rx" + str(i) + setattr(self.clock_domains, name, ClockDomain(name=name)) + self.comb += [ + getattr(self, name).clk.eq(rx.gtx.cd_cxp_gtx_rx.clk), + getattr(self, name).rst.eq(rx.gtx.cd_cxp_gtx_rx.rst) + ] + class Receiver(Module): def __init__(self, qpll, pad, sys_clk_freq, tx_mode, rx_mode, debug_sma, pmod_pads): @@ -51,8 +60,8 @@ class Receiver(Module): self.source.stb.eq(0), If(gtx.rx_ready & self.source.ack & ~((gtx.decoders[0].d == 0xBC) & (gtx.decoders[0].k == 1)), self.source.stb.eq(1), - self.source.data.eq(Cat(gtx.decoders[0].d, gtx.decoders[1].d, gtx.decoders[2].d, gtx.decoders[3].d)), - self.source.k.eq(Cat(gtx.decoders[0].k, gtx.decoders[1].k, gtx.decoders[2].k, gtx.decoders[3].k)), + self.source.data.eq(Cat(gtx.decoders[i].d for i in range(4))), + self.source.k.eq(Cat(gtx.decoders[i].k for i in range(4))), ) ]