diff --git a/src/gateware/cxp.py b/src/gateware/cxp.py
index ca70f05..b682eea 100644
--- a/src/gateware/cxp.py
+++ b/src/gateware/cxp.py
@@ -64,41 +64,44 @@ class RX_Pipeline(Module, AutoCSR):
     def __init__(self, phy, ctrl_buffer_depth, nslot):
         self.ready = CSRStatus()
 
+        self.trigger_ack = CSR()
+
+        self.pending_packet = CSR()
+        self.read_ptr = CSRStatus(log2_int(nslot))
+        self.reader_buffer_err = CSR()
+
+        self.reader_decode_err = CSR()
+        self.test_error_counter = CSRStatus(16)
+        self.test_packet_counter = CSRStatus(16)
+        self.test_counts_reset = CSR()
+
         # # #
 
         gtx = phy.gtx
-
-        # GTX status
         self.sync += self.ready.status.eq(gtx.rx_ready)
 
-        # DEBUG: init status
-        self.rxinit_phaligndone = CSRStatus()
-        self.comb += [
-            self.rxinit_phaligndone.status.eq(gtx.rx_init.Xxphaligndone),
-        ]
+        # # Connect all GTX connections' DRP
+        # self.gtx_daddr = CSRStorage(9)
+        # self.gtx_dread = CSR()
+        # self.gtx_din_stb = CSR()
+        # self.gtx_din = CSRStorage(16)
 
-        # Connect all GTX connections' DRP
-        self.gtx_daddr = CSRStorage(9)
-        self.gtx_dread = CSR()
-        self.gtx_din_stb = CSR()
-        self.gtx_din = CSRStorage(16)
+        # self.gtx_dout = CSRStatus(16)
+        # self.gtx_dready = CSR()
 
-        self.gtx_dout = CSRStatus(16)
-        self.gtx_dready = CSR()
-
-        self.comb += gtx.dclk.eq(ClockSignal("sys"))
-        self.sync += [
-            gtx.daddr.eq(self.gtx_daddr.storage),
-            gtx.den.eq(self.gtx_dread.re | self.gtx_din_stb.re),
-            gtx.dwen.eq(self.gtx_din_stb.re),
-            gtx.din.eq(self.gtx_din.storage),
-            If(gtx.dready,
-                self.gtx_dready.w.eq(1),
-                self.gtx_dout.status.eq(gtx.dout),
-            ).Elif(self.gtx_dready.re,
-                self.gtx_dready.w.eq(0),
-            ),
-        ]
+        # self.comb += gtx.dclk.eq(ClockSignal("sys"))
+        # self.sync += [
+        #     gtx.daddr.eq(self.gtx_daddr.storage),
+        #     gtx.den.eq(self.gtx_dread.re | self.gtx_din_stb.re),
+        #     gtx.dwen.eq(self.gtx_din_stb.re),
+        #     gtx.din.eq(self.gtx_din.storage),
+        #     If(gtx.dready,
+        #         self.gtx_dready.w.eq(1),
+        #         self.gtx_dout.status.eq(gtx.dout),
+        #     ).Elif(self.gtx_dready.re,
+        #         self.gtx_dready.w.eq(0),
+        #     ),
+        # ]
 
 
         # Receiver Pipeline WIP
@@ -129,11 +132,15 @@ class RX_Pipeline(Module, AutoCSR):
             ),
         ]
 
+        # DEBUG: CSR
+        self.sync += [
+            self.trig_clr.eq(self.trigger_ack.re),
+            self.trigger_ack.w.eq(self.trig_ack),
+        ]
+
         # Priority level 2 packet - data, test packet
         self.submodules.reader = reader = cdr(Control_Packet_Reader(ctrl_buffer_depth, nslot))
 
-        self.reader_decode_err = CSR()
-        self.reader_buffer_err = CSR()
 
         decode_err_ps = PulseSynchronizer("cxp_gtx_rx", "sys")
         buffer_err_ps = PulseSynchronizer("cxp_gtx_rx", "sys")
@@ -156,10 +163,6 @@ class RX_Pipeline(Module, AutoCSR):
         ]
 
         # test packet error & packet counters
-        self.test_error_counter = CSRStatus(16)
-        self.test_packet_counter = CSRStatus(16)
-        self.test_counts_reset = CSR()
-
         test_err_cnt_sys = Signal.like(self.test_error_counter.status)
         test_pak_cnt_sys = Signal.like(self.test_packet_counter.status)
         self.sync += [
@@ -193,9 +196,6 @@ class RX_Pipeline(Module, AutoCSR):
         ]
 
         # reader nslot buffer control interface
-        self.pending_packet = CSR()
-        self.read_ptr = CSRStatus(len(reader.read_ptr))
-
         write_ptr_sys = Signal.like(reader.write_ptr)
         
         self.specials += [
@@ -223,12 +223,6 @@ class RX_Pipeline(Module, AutoCSR):
         self.source = rx_pipeline[-1].source
         
 
-        # DEBUG: CSR
-        self.trigger_ack = CSR()
-        self.sync += [
-            self.trig_clr.eq(self.trigger_ack.re),
-            self.trigger_ack.w.eq(self.trig_ack),
-        ]
 
 
         
@@ -255,7 +249,7 @@ class TX_Pipeline(Module, AutoCSR):
         # 0: Trigger packet
         self.submodules.trig = trig = Trigger_Inserter()
         
-
+        # TODO: remove this?
         # 1: IO acknowledgment for trigger packet
         self.submodules.trig_ack = trig_ack = Trigger_ACK_Inserter()